module SeqDect(rst,clk,ip,op);

output reg op;
input clk, rst;
  input [1:0] ip;
reg [1:0] state;
reg [1:0] next_state;

  parameter [1:0] s0=2'b00;
  parameter [1:0] s1=2'b01;
  parameter [1:0] s2=2'b10;

always @(posedge clk, posedge rst)
begin
if (rst)
  state=s0;
    else
  state=next_state;
end

always @(state, next_state)
begin
case(state)
s0:
if (ip==2'b01)
  begin
    next_state=s1;
    op=1'b0;
  end
  else
  begin
    next_state=s0;
    op=1'b0;
  end

    s1:
  if (ip==2'b11)
  begin
    next_state=s2;
    op=1'b1;
  end
  else if (ip==2'b01)
  begin
    next_state=s1;
    op=1'b0;
  end
  else
  begin
    next_state=s0;
    op=1'b0;
  end

    s2:
  if (ip==2'b11)
  begin
    next_state=s2;
    op=1'b1;
  end
  else if (ip==2'b01)
  begin
    next_state=s1;
    op=1'b0;
  end
  else
  begin
    next_state=s0;
    op=1'b0;
  end

    default:
  begin
          next_state=s0;
          op=1'b0;
  end
    endcase
end
endmodule

module SeqDect(rst,clk,ip,op);

   /*io and internal wires*/

    always @(posedge clk, posedge rst)
    begin
    if (rst)
      state<=s0;
        else
      state<=next_state;
    end

    always @(state, ip)
    begin
    case(state)
    /*cases*/
        endcase
    end
    endmodule

module tb();

reg rst;
reg clk;
reg [1:0] ip;
wire op;

SeqDect uut(rst,clk,ip,op);

always #20 clk =~clk;

initial begin
clk=0;
rst=1;
#100
rst=0;
#100
ip = 2'b00;
#100
ip = 2'b01;
#100
ip = 2'b11;
#100
$stop;
end
endmodule