mac_reduced_param_tb.v

`include "mac.v"
`timescale 1us/1us
module mac_tb;

   // parameters
   parameter S_WIDTH=4, W_WIDTH=4, MULT_WIDTH = 8, ACC_PR_WIDTH = 10, ACC_WIDTH = 5;

   // on testbenches, inputs are regs
   reg signed [S_WIDTH-1:0] in1;
   reg signed [W_WIDTH-1:0] in2;
   reg clk;
   reg reset;

   // on testbenches, outputs are wires
   wire signed [ACC_WIDTH-1:0] out;

   //mac MAC1(in1,in2,clk, reset, out);
   mac #(.S_WIDTH(S_WIDTH), .W_WIDTH(W_WIDTH), .MULT_WIDTH(MULT_WIDTH), .ACC_PR_WIDTH(ACC_PR_WIDTH), .ACC_WIDTH(ACC_WIDTH))  MAC1 (in1,in2,clk, reset, out);

   initial begin
      clk = 0;     in1 = 1;   in2 = -1; reset = 0;
      #1 reset = 1;
      #1 reset = 0;

      #(2*2**8) $finish;

   end // initial begin

   always  #1 clk = ~clk;
   //always  #2 in1 = in1+1;
   //always  #(2*2**4) in2 = in2+1;

   initial begin
      $monitor ("%t | in1 = %d | in2 = %d | clk = %d | out = %d", $time, in1, in2, clk, out);
      $dumpfile("dump.vcd");
      $dumpvars();
   end
endmodule // sr_tb