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Ciusss89_draf_1_ar71xx_rb_wapgsc

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Sep 28th, 2017
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  1. diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
  2. index 9b4c53a57877..d92a39e57e50 100644
  3. --- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
  4. +++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
  5. @@ -49,6 +49,7 @@
  6.  #include "dev-eth.h"
  7.  #include "dev-spi.h"
  8.  #include "dev-gpio-buttons.h"
  9. +#include "dev-ap9x-pci.h"
  10.  #include "dev-leds-gpio.h"
  11.  #include "dev-m25p80.h"
  12.  #include "dev-usb.h"
  13. @@ -134,9 +135,11 @@ static struct flash_platform_data rbspi_spi_flash_data = {
  14.  };
  15.  
  16.  /* Several boards only have a single reset button wired to GPIO 16 */
  17. +#define RBSPI_GPIO_BTN_RESET01 1
  18.  #define RBSPI_GPIO_BTN_RESET16 16
  19.  #define RBSPI_GPIO_BTN_RESET20 20
  20.  
  21. +
  22.  static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
  23.     {
  24.         .desc = "Reset button",
  25. @@ -159,6 +162,17 @@ static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
  26.     },
  27.  };
  28.  
  29. +static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
  30. +   {
  31. +       .desc = "Reset button",
  32. +       .type = EV_KEY,
  33. +       .code = KEY_RESTART,
  34. +       .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
  35. +       .gpio = RBSPI_GPIO_BTN_RESET01,
  36. +       .active_low = 1,
  37. +   },
  38. +};
  39. +
  40.  /* RB mAP L-2nD gpios */
  41.  #define RBMAPL_GPIO_LED_POWER  17
  42.  #define RBMAPL_GPIO_LED_USER   14
  43. @@ -933,7 +947,93 @@ static void __init rbmap_setup(void)
  44.     ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
  45.  }
  46.  
  47. +/*
  48. + * RBwAPG-5HacT2HnD board:
  49. + *  -Power : PoE AT - DC.in (12 - 57V)
  50. + *  -SoC   : QCA9556
  51. + *  -Net:  : AR8033
  52. + *  -Phy0  : Built-in SoC, mimo 2x2:2
  53. + *  -Phy1  : QCA9880 3x3
  54. + *  -RAM   : 64 MiB
  55. + *  -FLASH : 16 MiB
  56. + *  -Antennas  : Gain 2dbi ( both bands )
  57. + *  -IC        : ZT2046Q provide a temperature and voltage sensor.
  58. + *
  59. + *
  60. + *  -HWID: wapg-sc
  61. + */
  62. +
  63. +#define RBWAPG_LED1        1
  64. +#define RBWAPG_LED2        8
  65. +#define RBWAPG_LED3        9
  66. +#define RBWAPG_POWERLED        16
  67. +
  68. +#define RBWAPG_GPIO_MDIO_MDC       12
  69. +#define RBWAPG_GPIO_MDIO_DATA      11
  70. +
  71. +#define RBWAPG_MDIO_PHYMASK        0
  72. +
  73. +static struct mdio_gpio_platform_data rbwap_mdio_data = {
  74. +   .mdc        = RBWAPG_GPIO_MDIO_MDC,
  75. +   .mdio       = RBWAPG_GPIO_MDIO_DATA,
  76. +// .phy_mask   = ~BIT(RBWAPG_MDIO_PHYMASK),
  77. +   .phy_mask   = 0,
  78. +};
  79. +
  80. +static struct at803x_platform_data rbwap_ar803x_data = {
  81. +   .disable_smarteee = 0,
  82. +   .enable_rgmii_rx_delay = 0,
  83. +   .enable_rgmii_tx_delay = 0,
  84. +   .fixup_rgmii_tx_delay = 1,
  85. +};
  86. +
  87. +static struct platform_device rbwap_phy_device = {
  88. +   .name   = "mdio-gpio",
  89. +   .id = 1,
  90. +   .dev    = {
  91. +       .platform_data = &rbwap_mdio_data,
  92. +                &rbwap_ar803x_data
  93. +   },
  94. +};
  95. +
  96. +static void __init rbwapg_setup(void)
  97. +{
  98. +   u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI
  99. +       | RBSPI_HAS_TS;
  100. +
  101. +   if (rbspi_platform_setup())
  102. +       return;
  103. +
  104. +   /* Sets SPI and USB */
  105. +   rbspi_peripherals_setup(flags);
  106. +
  107. +   /* SoC setup: MDIO Interface  */
  108. +   ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
  109. +   platform_device_register(&rbwap_phy_device);
  110. +
  111. +   /* Eth setup */
  112. +   ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
  113. +
  114. +   ath79_eth0_data.mii_bus_dev = &rbwap_phy_device.dev;
  115. +   ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
  116. +   ath79_eth0_data.phy_mask = BIT(RBWAPG_MDIO_PHYMASK);
  117. +
  118. +// ath79_eth0_pll_data.pll_1000 = 0x;
  119. +// ath79_eth0_pll_data.pll_100 = 0x;
  120. +// ath79_eth0_pll_data.pll_10 = 0x;
  121. +
  122. +   ath79_eth0_data.speed = SPEED_1000;
  123. +   ath79_eth0_data.duplex = DUPLEX_FULL;
  124. +
  125. +   ath79_register_eth(0);
  126. +
  127. +   /*GPIO*/
  128. +   ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
  129. +       ARRAY_SIZE(rbspi_gpio_keys_reset1),
  130. +       rbspi_gpio_keys_reset1);
  131. +}
  132.  
  133. +MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPG, "wapg-sc", rbwapg_setup)
  134.  MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
  135.  MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
  136.  MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
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