Ciusss89_draf_1_ar71xx_rb_wapgsc

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
index 9b4c53a57877..d92a39e57e50 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
@@ -49,6 +49,7 @@
 #include "dev-eth.h"
 #include "dev-spi.h"
 #include "dev-gpio-buttons.h"
+#include "dev-ap9x-pci.h"
 #include "dev-leds-gpio.h"
 #include "dev-m25p80.h"
 #include "dev-usb.h"
@@ -134,9 +135,11 @@ static struct flash_platform_data rbspi_spi_flash_data = {
 };

 /* Several boards only have a single reset button wired to GPIO 16 */
+#define RBSPI_GPIO_BTN_RESET01 1
 #define RBSPI_GPIO_BTN_RESET16 16
 #define RBSPI_GPIO_BTN_RESET20 20

+
 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
    {
        .desc = "Reset button",
@@ -159,6 +162,17 @@ static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
    },
 };

+static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
+   {
+       .desc = "Reset button",
+       .type = EV_KEY,
+       .code = KEY_RESTART,
+       .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
+       .gpio = RBSPI_GPIO_BTN_RESET01,
+       .active_low = 1,
+   },
+};
+
 /* RB mAP L-2nD gpios */
 #define RBMAPL_GPIO_LED_POWER  17
 #define RBMAPL_GPIO_LED_USER   14
@@ -933,7 +947,93 @@ static void __init rbmap_setup(void)
    ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
 }

+/*
+ * RBwAPG-5HacT2HnD board:
+ *  -Power : PoE AT - DC.in (12 - 57V)
+ *  -SoC   : QCA9556
+ *  -Net:  : AR8033
+ *  -Phy0  : Built-in SoC, mimo 2x2:2
+ *  -Phy1  : QCA9880 3x3
+ *  -RAM   : 64 MiB
+ *  -FLASH : 16 MiB
+ *  -Antennas  : Gain 2dbi ( both bands )
+ *  -IC        : ZT2046Q provide a temperature and voltage sensor.
+ *
+ *
+ *  -HWID: wapg-sc
+ */
+
+#define RBWAPG_LED1        1
+#define RBWAPG_LED2        8
+#define RBWAPG_LED3        9
+#define RBWAPG_POWERLED        16
+
+#define RBWAPG_GPIO_MDIO_MDC       12
+#define RBWAPG_GPIO_MDIO_DATA      11
+
+#define RBWAPG_MDIO_PHYMASK        0
+
+static struct mdio_gpio_platform_data rbwap_mdio_data = {
+   .mdc        = RBWAPG_GPIO_MDIO_MDC,
+   .mdio       = RBWAPG_GPIO_MDIO_DATA,
+// .phy_mask   = ~BIT(RBWAPG_MDIO_PHYMASK),
+   .phy_mask   = 0,
+};
+
+static struct at803x_platform_data rbwap_ar803x_data = {
+   .disable_smarteee = 0,
+   .enable_rgmii_rx_delay = 0,
+   .enable_rgmii_tx_delay = 0,
+   .fixup_rgmii_tx_delay = 1,
+};
+
+static struct platform_device rbwap_phy_device = {
+   .name   = "mdio-gpio",
+   .id = 1,
+   .dev    = {
+       .platform_data = &rbwap_mdio_data,
+                &rbwap_ar803x_data
+   },
+};
+
+static void __init rbwapg_setup(void)
+{
+   u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI
+       | RBSPI_HAS_TS;
+
+   if (rbspi_platform_setup())
+       return;
+
+   /* Sets SPI and USB */
+   rbspi_peripherals_setup(flags);
+
+   /* SoC setup: MDIO Interface  */
+   ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
+   platform_device_register(&rbwap_phy_device);
+
+   /* Eth setup */
+   ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
+
+   ath79_eth0_data.mii_bus_dev = &rbwap_phy_device.dev;
+   ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+   ath79_eth0_data.phy_mask = BIT(RBWAPG_MDIO_PHYMASK);
+
+// ath79_eth0_pll_data.pll_1000 = 0x;
+// ath79_eth0_pll_data.pll_100 = 0x;
+// ath79_eth0_pll_data.pll_10 = 0x;
+
+   ath79_eth0_data.speed = SPEED_1000;
+   ath79_eth0_data.duplex = DUPLEX_FULL;
+
+   ath79_register_eth(0);
+
+   /*GPIO*/
+   ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
+       ARRAY_SIZE(rbspi_gpio_keys_reset1),
+       rbspi_gpio_keys_reset1);
+}

+MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAPG, "wapg-sc", rbwapg_setup)
 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);