// latency accumulator -- a chain of ops with data dependency between each two ops
// to break the dependency set COISSUE

#if __aarch64__ == 0
    #error wrong target arch
#endif

#include <stddef.h>

int main(int, char**) {
    size_t const rep = size_t(5e8);

    for (size_t i = 0; i < rep; ++i) {

#if COISSUE
        asm volatile (
            "tbl v17.16b, {v1.16b},  v0.16b\n\t"
            "tbl v18.16b, {v2.16b},  v0.16b\n\t"
            "tbl v19.16b, {v3.16b},  v0.16b\n\t"
            "tbl v20.16b, {v4.16b},  v0.16b\n\t"
            "tbl v21.16b, {v5.16b},  v0.16b\n\t"
            "tbl v22.16b, {v6.16b},  v0.16b\n\t"
            "tbl v23.16b, {v7.16b},  v0.16b\n\t"
            "tbl v24.16b, {v8.16b},  v0.16b\n\t"
            "tbl v25.16b, {v9.16b},  v0.16b\n\t"
            "tbl v26.16b, {v10.16b}, v0.16b\n\t"
            "tbl v27.16b, {v11.16b}, v0.16b\n\t"
            "tbl v28.16b, {v12.16b}, v0.16b\n\t"
            "tbl v29.16b, {v13.16b}, v0.16b\n\t"
            "tbl v30.16b, {v14.16b}, v0.16b\n\t"
            "tbl v31.16b, {v15.16b}, v0.16b\n\t"
            "tbl v0.16b,  {v16.16b}, v0.16b"
            : : : "memory");

#else
        asm volatile (
            "tbl v2.16b,  {v1.16b},  v0.16b\n\t"
            "tbl v3.16b,  {v2.16b},  v0.16b\n\t"
            "tbl v4.16b,  {v3.16b},  v0.16b\n\t"
            "tbl v5.16b,  {v4.16b},  v0.16b\n\t"
            "tbl v6.16b,  {v5.16b},  v0.16b\n\t"
            "tbl v7.16b,  {v6.16b},  v0.16b\n\t"
            "tbl v8.16b,  {v7.16b},  v0.16b\n\t"
            "tbl v9.16b,  {v8.16b},  v0.16b\n\t"
            "tbl v10.16b, {v9.16b},  v0.16b\n\t"
            "tbl v11.16b, {v10.16b}, v0.16b\n\t"
            "tbl v12.16b, {v11.16b}, v0.16b\n\t"
            "tbl v13.16b, {v12.16b}, v0.16b\n\t"
            "tbl v14.16b, {v13.16b}, v0.16b\n\t"
            "tbl v15.16b, {v14.16b}, v0.16b\n\t"
            "tbl v16.16b, {v15.16b}, v0.16b\n\t"
            "tbl v17.16b, {v16.16b}, v0.16b"
            : : : "memory");

#endif
    }

    return 0;
}