ENTITY AULA4 IS
	PORT (  CLOCK, INICIA : IN BIT;
			QOUT : BUFFER BIT_VECTOR(2 DOWNTO 0) );
END AULA4;
ARCHITECTURE CANARINHOPISTOLA OF AULA4 IS
	COMPONENT FFJK
		PORT (  J, K, CLK, PRS, RST : IN BIT;
			    Q, QN : OUT BIT );
	END COMPONENT;
	SIGNAL AUX, A1, A2 : BIT;
BEGIN
	FF1 : FFJK PORT MAP (J=>'1',K=>'1',CLK=>CLOCK,PRS=>AUX,
						 RST=>'1', Q=>QOUT(0), QN=>A1);
	FF2 : FFJK PORT MAP (J=>'1',K=>'1',CLK=>A1,PRS=>'1',
						 RST=>AUX, Q=>QOUT(1), QN=>A2);
	FF3 : FFJK PORT MAP (J=>'1',K=>'1',CLK=>A2,PRS=>AUX,
						 RST=>'1', Q=>QOUT(2));
	AUX <= INICIA AND (NOT ((NOT QOUT(2)) AND (NOT QOUT(1)) AND (NOT QOUT(0))));
END CANARINHOPISTOLA;

ENTITY FFJK IS -- FLIP FLOP JK COM PRESET E RESET
	PORT (  J, K, CLK, PRS, RST : IN BIT;
			Q, QN : OUT BIT );
END FFJK;
ARCHITECTURE OSCARNIEMEYER OF FFJK IS
	SIGNAL STATE : BIT; -- ESTADO INTERNO (PARA EVITAR LEITURA DO Q)
BEGIN
	PROCESS (CLK, PRS, RST)
	BEGIN
		IF PRS='0' THEN STATE <= '1'; -- PRESET ASSÍNCRONO
		ELSIF RST='0' THEN STATE <= '0'; -- RESET ASSÍNCRONO
		ELSIF CLK='0' AND CLK'EVENT THEN -- CHECAR DESCIDA DE CLOCK
			IF J='1' AND K='1' THEN STATE <= NOT STATE; -- TOGGLE
			ELSIF J='0' AND K='1' THEN STATE <= '0';
			ELSIF J='1' AND K='0' THEN STATE <= '1';
			END IF;
		END IF;
	END PROCESS;
	Q <= STATE;
	QN <= NOT STATE;
END OSCARNIEMEYER;