module i2s_gray_counter
(
    input clk,
    input clear,
    input direct_access,
    input en,
    output reg [COUNTER_WIDTH-1:0] gray_count_out
);

parameter COUNTER_WIDTH = 5;

// internal signals
reg [COUNTER_WIDTH-1:0] binary_count;

always @(posedge clk or posedge direct_access or negedge rst_n) begin
    if (clear) begin
        binary_count <= {COUNTER_WIDTH{1'b0}} + 1;
        gray_count_out <= {COUNTER_WIDTH{1'b0}};
    end
    else begin
        if (direct_access | (clk & en)) begin
            binary_count <= binary_count + 1;
            gray_count_out <= {binary_count[COUNTER_WIDTH-1], binary_count[COUNTER_WIDTH-2:0] ^ binary_count[COUNTER_WIDTH-1:1]};
        end
    end
end

endmodule