LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY reklama IS
PORT
(
    SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
    HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 : OUT STD_LOGIC_VECTOR(0 TO 6)
);
END reklama;

ARCHITECTURE strukturalna OF reklama IS

CONSTANT SPACJA : STD_LOGIC_VECTOR(2 DOWNTO 0):="000";

-- DEKLARACJA KOMPONENTÓW

COMPONENT mux3bit8to1 -- MULTIPLEKSER
PORT
(
    -- WEKTOR STERUJĄCY I 8 wektorów INFORMACYJNYCH
    S, U0, U1, U2, U3, U4, U5,U6,U7: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END COMPONENT;

COMPONENT char7seg -- TRANSKODER
PORT
(
    C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    Display : OUT STD_LOGIC_VECTOR(0 TO 6)
);
END COMPONENT;

SIGNAL M0, M1, M2, M3, M4, M5, M6, M7 : STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN
-- KONKRETYZACJA UŻYCIA KOMPONENTÓW

-- KONKRETYZACJE KOLEJNYCH MULTIPLEKSERÓW UKŁADU
MUX0 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    SPACJA,
    M0
);

MUX1 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    M1
);

MUX2 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    M2
);

MUX3 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    M3
);

MUX4 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    M4
);

MUX5 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SPACJA,
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    M5
);

MUX6 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SPACJA,
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    M6
);

MUX7 : mux3bit8to1 PORT MAP
(
    SW(17 DOWNTO 15),
    SPACJA,
    SW(14 DOWNTO 12),
    SW(11 DOWNTO 9),
    SW(8 DOWNTO 6),
    SW(5 DOWNTO 3),
    SW(2 DOWNTO 0),
    SPACJA,
    SPACJA,
    M7
);

-- KONKRETYZACJE KOLEJNYCH TRANSKODERÓW
H0: char7seg PORT MAP (M0, HEX0);
H1: char7seg PORT MAP (M1, HEX1);
H2: char7seg PORT MAP (M2, HEX2);
H3: char7seg PORT MAP (M3, HEX3);
H4: char7seg PORT MAP (M4, HEX4);
H5: char7seg PORT MAP (M5, HEX5);
H6: char7seg PORT MAP (M6, HEX6);
H7: char7seg PORT MAP (M7, HEX7);

END strukturalna;


-- IMPLEMENTACJA MULTIPLEKSERA 8 do 1 (WEKTOR 3 BITOWY)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mux3bit8to1 IS
 PORT ( S, U0, U1, U2, U3, U4, U5,U6,U7: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 M : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END mux3bit8to1;
ARCHITECTURE strukturalna OF mux3bit8to1 IS
BEGIN
        M <= (
        ((not S(2) and not S(1) and not S(0) and U0(2)) or (not S(2) and not S(1) and S(0) and U1(2))
        or (not S(2) and S(1) and S(0) and U2(2)) or (not S(2) and S(1) and not S(0) and U3(2))
        or (S(2) and S(1) and not S(0) and U4(2)) or (S(2) and S(1) and S(0) and U5(2))
        or (S(2) and not S(1) and S(0) and U6(2)) or (S(2) and not S(1) and not S(0) and U7(2)))
        &
        ((not S(2) and not S(1) and not S(0) and U0(1)) or (not S(2) and not S(1) and S(0) and U1(1))
        or (not S(2) and S(1) and S(0) and U2(1)) or (not S(2) and S(1) and not S(0) and U3(1))
        or (S(2) and S(1) and not S(0) and U4(1)) or (S(2) and S(1) and S(0) and U5(1))
        or (S(2) and not S(1) and S(0) and U6(1)) or (S(2) and not S(1) and not S(0) and U7(1)))
        &
        ((not S(2) and not S(1) and not S(0) and U0(0)) or (not S(2) and not S(1) and S(0) and U1(0))
        or (not S(2) and S(1) and S(0) and U2(0)) or (not S(2) and S(1) and not S(0) and U3(0))
        or (S(2) and S(1) and not S(0) and U4(0)) or (S(2) and S(1) and S(0) and U5(0))
        or (S(2) and not S(1) and S(0) and U6(0)) or (S(2) and not S(1) and not S(0) and U7(0)))
        );

END strukturalna;

    -- IMPLEMENTACJA TRANSKODERA
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY char7seg IS
 PORT ( C : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
 Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END char7seg;
ARCHITECTURE strukturalna OF char7seg IS
BEGIN
    --with C select
    --Display <=    "1111111" when "000", -- spacja
    --              "0111000" when "001", -- F
    --              "0100001" when "010", -- G
    --              "1001000" when "011", -- H
    --              "1001111" when "100", -- I
    --              "1000011" when "101", -- J
    --              "-------" when others;

    Display <= ((not C(2) and not C(1) and not C(0)) or
                    (not C(2) and C(1) and C(0)) or
                    (C(2) and not C(1) and not C(0)) or
                    (C(2) and not C(1) and C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                     (not C(2) and not C(1) and C(0)) or
                    (not C(2) and C(1) and not C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                    (not C(2) and not C(1) and C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                     (not C(2) and not C(1) and C(0)) or
                    (not C(2) and C(1) and C(0)) or
                    (C(2) and not C(1) and not C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                    (C(2) and not C(1) and not C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                     (C(2) and not C(1) and not C(0)) or
                    (C(2) and not C(1) and C(0)))
                    &
                    ((not C(2) and not C(1) and not C(0)) or
                    (not C(2) and C(1) and not C(0)) or
                    (C(2) and not C(1) and not C(0)) or
                    (C(2) and not C(1) and C(0))
                    );
END strukturalna;