`default_nettype none

module mini_dut
(
    input  wire pcpi_wr,
    input  wire pcpi_ready,
    output reg  pcpi_int_wr
);

    wire pcpi_mul_ready;
    wire pcpi_mul_wr;

    assign pcpi_mul_ready = 0;
    assign pcpi_mul_wr = 0;

    always @* begin
        pcpi_int_wr = 0;

        (* parallel_case *)
        case (1'b1)
            pcpi_ready: begin
                pcpi_int_wr = pcpi_wr;
            end

            pcpi_mul_ready: begin
                pcpi_int_wr = pcpi_mul_wr;
            end
        endcase
    end

endmodule


module mini_dut_wrap_good
(
    input  wire pcpi_wr,
    input  wire pcpi_ready,
    output wire pcpi_int_wr
);

    mini_dut dut_I (
        .pcpi_wr(pcpi_wr),
        .pcpi_ready(pcpi_ready),
        .pcpi_int_wr(pcpi_int_wr)
    );

endmodule


module mini_dut_wrap_bad
(
    input  wire pcpi_wr,
    output wire pcpi_int_wr
);

    mini_dut dut_I (
        .pcpi_wr(pcpi_wr),
        .pcpi_ready(pcpi_wr),
        .pcpi_int_wr(pcpi_int_wr)
    );

endmodule