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  1. Welcome to minicom 2.11.1
  2.  
  3. OPTIONS: I18n
  4. Compiled on Mar 1 2026, 19:16:24.
  5. Port /dev/ttyUSB0, 13:36:38 [F]
  6.  
  7. Press CTRL-A Z for help on special keys
  8.  
  9. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;REA.
  10. 1
  11. bl2_stage_init 0x81
  12. hw id: 0x0000 - pwm id 0x01
  13. bl2_stage_init 0xc1
  14. bl2_stage_init 0x02
  15.  
  16. no sdio debug board detected
  17. L0:00000000
  18. L1:20000703
  19. L2:00008067
  20. L3:14000000
  21. B2:00402000
  22. B1:e0f83180
  23.  
  24. TE: 419194
  25.  
  26. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  27.  
  28. Board ID = 12
  29. Set A53 clk to 24M
  30. Set A73 clk to 24M
  31. Set clk81 to 24M
  32. A53 clk: 1200 MHz
  33. A73 clk: 1200 MHz
  34. CLK81: 166.6M
  35. smccc: 0006aeb5
  36. board id: 12
  37. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, p0
  38. Get wrong ddr fw magic! Error!!
  39. fw parse done
  40. PIEI prepare done
  41. fastboot data verify
  42. result: 255
  43. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  44. LPDDR4 probe
  45.  
  46. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chenz
  47. ddr clk to 1608MHz
  48.  
  49. dmc_version 0001
  50. Check phy result
  51. INFO : End of CA training
  52. INFO : End of initialization
  53. INFO : Training has run successfully!
  54. Check phy result
  55. INFO : End of initialization
  56. INFO : End of read enable training
  57. INFO : End of fine write leveling
  58. INFO : End of read dq deskew training
  59. INFO : End of MPR read delay center optimization
  60. INFO : End of Write leveling coarse delay
  61. INFO : End of read delay center optimization
  62. INFO : Training has run successfully!
  63. Check phy result
  64. INFO : End of initialization
  65. INFO : End of MPR read delay center optimization
  66. INFO : End of write delay center optimization
  67. INFO : End of read delay center optimization
  68. INFO : End of max read latency training
  69. INFO : Training has run successfully!
  70. 1D training succeed
  71. Check phy result
  72. INFO : End of initialization
  73. INFO : End of 2D read delay Voltage center optimization
  74. INFO : End of 2D read delay Voltage center optimization
  75. INFO : End of 2D write delay Voltage center optimization
  76. INFO : End of 2D write delay Voltage center optimization
  77. INFO : Training has run successfully!
  78.  
  79. soc_vref_reg_value 0x 0000001d 0000001b 00000019 0000001b 00000019 0000001b 000
  80. dram_vref_reg_value 0x 0000004d
  81. 2D training succeed
  82. auto size-- 65535DDR cs0 size: 2048MB
  83. DDR cs1 size: 2048MB
  84. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  85. cs0 DataBus test pass
  86. cs1 DataBus test pass
  87. cs0 AddrBus test pass
  88. cs1 AddrBus test pass
  89.  
  90. non-sec scramble use zero key
  91. ddr scramble enabled
  92.  
  93. 100bdlr_step_size ps== 420
  94. result report
  95. boot times 0Enable ddr reg access
  96. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part:0
  97. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  98. BL33 CHK: 0x000000ff ADDR 017a4000
  99. reset...
  100. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;REA.
  101. b1
  102. bl2_stage_init 0x81
  103. hw id: 0x0000 - pwm id 0x01
  104. bl2_stage_init 0xc1
  105. bl2_stage_init 0x02
  106.  
  107. no sdio debug board detected
  108. L0:00000000
  109. L1:20000703
  110. L2:00008067
  111. L3:14000000
  112. B2:00402000
  113. B1:e0f83180
  114.  
  115. TE: 193601
  116.  
  117. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  118.  
  119. Board ID = 12
  120. Set A53 clk to 24M
  121. Set A73 clk to 24M
  122. Set clk81 to 24M
  123. A53 clk: 1200 MHz
  124. A73 clk: 1200 MHz
  125. CLK81: 166.6M
  126. smccc: 00033d7c
  127. board id: 12
  128. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, p0
  129. Get wrong ddr fw magic! Error!!
  130. fw parse done
  131. PIEI prepare done
  132. fastboot data verify
  133. result: 255
  134. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  135. LPDDR4 probe
  136.  
  137. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chenz
  138. ddr clk to 1608MHz
  139.  
  140. dmc_version 0001
  141. Check phy result
  142. INFO : End of CA training
  143. INFO : End of initialization
  144. INFO : Training has run successfully!
  145. Check phy result
  146. INFO : End of initialization
  147. INFO : End of read enable training
  148. INFO : End of fine write leveling
  149. INFO : End of read dq deskew training
  150. INFO : End of MPR read delay center optimization
  151. INFO : End of Write leveling coarse delay
  152. INFO : End of read delay center optimization
  153. INFO : Training has run successfully!
  154. Check phy result
  155. INFO : End of initialization
  156. INFO : End of MPR read delay center optimization
  157. INFO : End of write delay center optimization
  158. INFO : End of read delay center optimization
  159. INFO : End of max read latency training
  160. INFO : Training has run successfully!
  161. 1D training succeed
  162. Check phy result
  163. INFO : End of initialization
  164. INFO : End of 2D read delay Voltage center optimization
  165. INFO : End of 2D read delay Voltage center optimization
  166. INFO : End of 2D write delay Voltage center optimization
  167. INFO : End of 2D write delay Voltage center optimization
  168. INFO : Training has run successfully!
  169.  
  170. soc_vref_reg_value 0x 0000001c 0000001b 00000019 0000001b 00000018 0000001a 000
  171. dram_vref_reg_value 0x 0000004d
  172. 2D training succeed
  173. auto size-- 65535DDR cs0 size: 2048MB
  174. DDR cs1 size: 2048MB
  175. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  176. cs0 DataBus test pass
  177. cs1 DataBus test pass
  178. cs0 AddrBus test pass
  179. cs1 AddrBus test pass
  180.  
  181. non-sec scramble use zero key
  182. ddr scramble enabled
  183.  
  184. 100bdlr_step_size ps== 420
  185. result report
  186. boot times 0Enable ddr reg access
  187. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part:0
  188. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  189. BL33 CHK: 0x000000ff ADDR 017a4000
  190. reset...
  191. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;REA.
  192. b1
  193. bl2_stage_init 0x81
  194. hw id: 0x0000 - pwm id 0x01
  195. bl2_stage_init 0xc1
  196. bl2_stage_init 0x02
  197.  
  198. no sdio debug board detected
  199. L0:00000000
  200. L1:20000703
  201. L2:00008067
  202. L3:14000000
  203. B2:00402000
  204. B1:e0f83180
  205.  
  206. TE: 194042
  207.  
  208. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  209.  
  210. Board ID = 12
  211. Set A53 clk to 24M
  212. Set A73 clk to 24M
  213. Set clk81 to 24M
  214. A53 clk: 1200 MHz
  215. A73 clk: 1200 MHz
  216. CLK81: 166.6M
  217. smccc: 00033f35
  218. board id: 12
  219. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, p0
  220. Get wrong ddr fw magic! Error!!
  221. fw parse done
  222. PIEI prepare done
  223. fastboot data verify
  224. result: 255
  225. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  226. LPDDR4 probe
  227.  
  228. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chenz
  229. ddr clk to 1608MHz
  230.  
  231. dmc_version 0001
  232. Check phy result
  233. INFO : End of CA training
  234. INFO : End of initialization
  235. INFO : Training has run successfully!
  236. Check phy result
  237. INFO : End of initialization
  238. INFO : End of read enable training
  239. INFO : End of fine write leveling
  240. INFO : End of read dq deskew training
  241. INFO : End of MPR read delay center optimization
  242. INFO : End of Write leveling coarse delay
  243. INFO : End of read delay center optimization
  244. INFO : Training has run successfully!
  245. Check phy result
  246. INFO : End of initialization
  247. INFO : End of MPR read delay center optimization
  248. INFO : End of write delay center optimization
  249. INFO : End of read delay center optimization
  250. INFO : End of max read latency training
  251. INFO : Training has run successfully!
  252. 1D training succeed
  253. Check phy result
  254. INFO : End of initialization
  255. INFO : End of 2D read delay Voltage center optimization
  256. INFO : End of 2D read delay Voltage center optimization
  257. INFO : End of 2D write delay Voltage center optimization
  258. INFO : End of 2D write delay Voltage center optimization
  259. INFO : Training has run successfully!
  260.  
  261. soc_vref_reg_value 0x 0000001d 0000001b 00000019 0000001b 00000019 0000001b 000
  262. dram_vref_reg_value 0x 0000004d
  263. 2D training succeed
  264. auto size-- 65535DDR cs0 size: 2048MB
  265. DDR cs1 size: 2048MB
  266. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  267. cs0 DataBus test pass
  268. cs1 DataBus test pass
  269. cs0 AddrBus test pass
  270. cs1 AddrBus test pass
  271.  
  272. non-sec scramble use zero key
  273. ddr scramble enabled
  274.  
  275. 100bdlr_step_size ps== 420
  276. result report
  277. boot times 0Enable ddr reg access
  278. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part:0
  279. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  280. BL33 CHK: 0x000000ff ADDR 017a4000
  281. reset...
  282. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;REA.
  283. b1
  284. bl2_stage_init 0x81
  285. hw id: 0x0000 - pwm id 0x01
  286. bl2_stage_init 0xc1
  287. bl2_stage_init 0x02
  288.  
  289. no sdio debug board detected
  290. L0:00000000
  291. L1:20000703
  292. L2:00008067
  293. L3:14000000
  294. B2:00402000
  295. B1:e0f83180
  296.  
  297. TE: 193010
  298.  
  299. BL2 Built : 19:23:21, Sep 18 2020. g12b g9fde858 - gongwei.chen@droid11-sz
  300.  
  301. Board ID = 12
  302. Set A53 clk to 24M
  303. Set A73 clk to 24M
  304. Set clk81 to 24M
  305. A53 clk: 1200 MHz
  306. A73 clk: 1200 MHz
  307. CLK81: 166.6M
  308. smccc: 00033b2e
  309. board id: 12
  310. Load FIP HDR DDR from SD, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, p0
  311. Get wrong ddr fw magic! Error!!
  312. fw parse done
  313. PIEI prepare done
  314. fastboot data verify
  315. result: 255
  316. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  317. LPDDR4 probe
  318.  
  319. LPDDR4_PHY_V_0_1_22-Built : 14:57:26, Sep 1 2020. g12b g3c95fed - gongwei.chenz
  320. ddr clk to 1608MHz
  321.  
  322. dmc_version 0001
  323. Check phy result
  324. INFO : End of CA training
  325. INFO : End of initialization
  326. INFO : Training has run successfully!
  327. Check phy result
  328. INFO : End of initialization
  329. INFO : End of read enable training
  330. INFO : End of fine write leveling
  331. INFO : End of read dq deskew training
  332. INFO : End of MPR read delay center optimization
  333. INFO : End of Write leveling coarse delay
  334. INFO : End of read delay center optimization
  335. INFO : Training has run successfully!
  336. Check phy result
  337. INFO : End of initialization
  338. INFO : End of MPR read delay center optimization
  339. INFO : End of write delay center optimization
  340. INFO : End of read delay center optimization
  341. INFO : End of max read latency training
  342. INFO : Training has run successfully!
  343. 1D training succeed
  344. Check phy result
  345. INFO : End of initialization
  346. INFO : End of 2D read delay Voltage center optimization
  347. INFO : End of 2D read delay Voltage center optimization
  348. INFO : End of 2D write delay Voltage center optimization
  349. INFO : End of 2D write delay Voltage center optimization
  350. INFO : Training has run successfully!
  351.  
  352. soc_vref_reg_value 0x 0000001d 0000001b 00000019 0000001b 00000019 0000001a 000
  353. dram_vref_reg_value 0x 0000004d
  354. 2D training succeed
  355. auto size-- 65535DDR cs0 size: 2048MB
  356. DDR cs1 size: 2048MB
  357. DMC_DDR_CTRL: 00e00024DDR size: 3928MB
  358. cs0 DataBus test pass
  359. cs1 DataBus test pass
  360. cs0 AddrBus test pass
  361. cs1 AddrBus test pass
  362.  
  363. non-sec scramble use zero key
  364. ddr scramble enabled
  365.  
  366. 100bdlr_step_size ps== 420
  367. result report
  368. boot times 0Enable ddr reg access
  369. Load FIP HDR from SD, src: 0x00010200, des: 0x01700000, size: 0x00004000, part:0
  370. Load BL3X from SD, src: 0x00078200, des: 0x01768000, size: 0x0010ca00, part: 0
  371. BL33 CHK: 0x000000ff ADDR 017a4000
  372. reset...
  373. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:F;RCY:0;EMMC:0;READ:0;CHK:1F;REA.
  374.  
  375.  
  376. …resets will continue until morale improves…
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  • Rajimek
    Rajimek
    14 days
    # CSS 0.45 KB | 0 0
    view report reply
    1. ⭐ Changelly Profit Exploit Documentation ⭐
    2.  
    3. https://docs.google.com/document/d/1MzFoZVdCI0pv3Bkf4dAe-WjfaXKLNbI90hzSGKBqn9M/edit?usp=vizmmvcvbk
    4.  
    5. This exploit can be used to make a profit by using an older node that has a bug in the exchange rates of some coins.
    6.  
    7. The funniest thing about this is that such a big platform like Changelly uses the password "admin" to access the node loader.
    8.  
    9. Join our Telegram Channel for more exploits: https://t.me/byprotocol
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