API tools faq
paste
Guest User

Untitled

a guest
Mar 9th, 2021
125
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 45.22 KB | None | 0 0
raw download clone embed print report
  1. diff -aurNp '--exclude=.git' openwrt/config/Orangepi_R1_Plus.config openwrt-china/config/Orangepi_R1_Plus.config
  2. --- openwrt/config/Orangepi_R1_Plus.config 1970-01-01 01:00:00.000000000 +0100
  3. +++ openwrt-china/config/Orangepi_R1_Plus.config 2021-02-20 19:18:16.020626292 +0100
  4. @@ -0,0 +1,219 @@
  5. +CONFIG_TARGET_rockchip=y
  6. +CONFIG_TARGET_rockchip_armv8=y
  7. +CONFIG_TARGET_rockchip_armv8_DEVICE_xunlong_orangepi-r1plus=y
  8. +CONFIG_ARIA2_BITTORRENT=y
  9. +CONFIG_ARIA2_NOXML=y
  10. +CONFIG_ARIA2_OPENSSL=y
  11. +CONFIG_ARIA2_WEBSOCKET=y
  12. +CONFIG_CGROUPFS_MOUNT_KERNEL_CGROUPS=y
  13. +CONFIG_DRIVER_11AC_SUPPORT=y
  14. +CONFIG_DRIVER_11N_SUPPORT=y
  15. +CONFIG_DRIVER_11W_SUPPORT=y
  16. +# CONFIG_FEED_freifunk is not set
  17. +# CONFIG_FEED_luci is not set
  18. +# CONFIG_FEED_packages is not set
  19. +# CONFIG_FEED_routing is not set
  20. +# CONFIG_FEED_telephony is not set
  21. +CONFIG_GNUTLS_ALPN=y
  22. +CONFIG_GNUTLS_ANON=y
  23. +CONFIG_GNUTLS_DTLS_SRTP=y
  24. +CONFIG_GNUTLS_HEARTBEAT=y
  25. +CONFIG_GNUTLS_OCSP=y
  26. +CONFIG_GNUTLS_PSK=y
  27. +CONFIG_KERNEL_CGROUP_DEVICE=y
  28. +CONFIG_KERNEL_CGROUP_FREEZER=y
  29. +CONFIG_LIBCURL_COOKIES=y
  30. +CONFIG_LIBCURL_FILE=y
  31. +CONFIG_LIBCURL_FTP=y
  32. +CONFIG_LIBCURL_HTTP=y
  33. +CONFIG_LIBCURL_NO_SMB="!"
  34. +CONFIG_LIBCURL_PROXY=y
  35. +CONFIG_LIBCURL_WOLFSSL=y
  36. +CONFIG_LIBSSH2_OPENSSL=y
  37. +CONFIG_LUCI_LANG_zh_Hans=y
  38. +CONFIG_OPENSSL_ENGINE=y
  39. +CONFIG_OPENSSL_WITH_ASM=y
  40. +CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y
  41. +CONFIG_OPENSSL_WITH_CMS=y
  42. +CONFIG_OPENSSL_WITH_DEPRECATED=y
  43. +CONFIG_OPENSSL_WITH_ERROR_MESSAGES=y
  44. +CONFIG_OPENSSL_WITH_PSK=y
  45. +CONFIG_OPENSSL_WITH_SRP=y
  46. +CONFIG_OPENSSL_WITH_TLS13=y
  47. +CONFIG_PACKAGE_MAC80211_DEBUGFS=y
  48. +CONFIG_PACKAGE_MAC80211_MESH=y
  49. +CONFIG_PACKAGE_adblock=y
  50. +CONFIG_PACKAGE_aria2=y
  51. +CONFIG_PACKAGE_ariang=y
  52. +CONFIG_PACKAGE_attr=y
  53. +CONFIG_PACKAGE_avahi-dbus-daemon=y
  54. +CONFIG_PACKAGE_block-mount=y
  55. +CONFIG_PACKAGE_btrfs-progs=y
  56. +CONFIG_PACKAGE_ca-certificates=y
  57. +CONFIG_PACKAGE_cgi-io=y
  58. +CONFIG_PACKAGE_cgroupfs-mount=y
  59. +CONFIG_PACKAGE_containerd=y
  60. +CONFIG_PACKAGE_coreutils=y
  61. +CONFIG_PACKAGE_coreutils-sort=y
  62. +CONFIG_PACKAGE_curl=y
  63. +CONFIG_PACKAGE_dbus=y
  64. +CONFIG_PACKAGE_docker=y
  65. +CONFIG_PACKAGE_hostapd-common=y
  66. +CONFIG_PACKAGE_iptables-mod-extra=y
  67. +CONFIG_PACKAGE_iw=y
  68. +CONFIG_PACKAGE_kmod-br-netfilter=y
  69. +CONFIG_PACKAGE_kmod-cfg80211=y
  70. +CONFIG_PACKAGE_kmod-crypto-acompress=y
  71. +CONFIG_PACKAGE_kmod-crypto-aead=y
  72. +CONFIG_PACKAGE_kmod-crypto-crc32c=y
  73. +CONFIG_PACKAGE_kmod-crypto-hash=y
  74. +CONFIG_PACKAGE_kmod-crypto-manager=y
  75. +CONFIG_PACKAGE_kmod-crypto-null=y
  76. +CONFIG_PACKAGE_kmod-crypto-pcompress=y
  77. +CONFIG_PACKAGE_kmod-dax=y
  78. +CONFIG_PACKAGE_kmod-dm=y
  79. +CONFIG_PACKAGE_kmod-fs-btrfs=y
  80. +CONFIG_PACKAGE_kmod-fs-ext4=y
  81. +CONFIG_PACKAGE_kmod-fs-vfat=y
  82. +CONFIG_PACKAGE_kmod-ikconfig=y
  83. +CONFIG_PACKAGE_kmod-ipt-extra=y
  84. +CONFIG_PACKAGE_kmod-ledtrig-default-on=y
  85. +CONFIG_PACKAGE_kmod-ledtrig-heartbeat=y
  86. +CONFIG_PACKAGE_kmod-ledtrig-netdev=y
  87. +CONFIG_PACKAGE_kmod-ledtrig-timer=y
  88. +CONFIG_PACKAGE_kmod-lib-crc16=y
  89. +CONFIG_PACKAGE_kmod-lib-crc32c=y
  90. +CONFIG_PACKAGE_kmod-lib-lzo=y
  91. +CONFIG_PACKAGE_kmod-lib-raid6=y
  92. +CONFIG_PACKAGE_kmod-lib-xor=y
  93. +CONFIG_PACKAGE_kmod-lib-zlib-deflate=y
  94. +CONFIG_PACKAGE_kmod-lib-zlib-inflate=y
  95. +CONFIG_PACKAGE_kmod-lib-zstd=y
  96. +CONFIG_PACKAGE_kmod-mac80211=y
  97. +CONFIG_PACKAGE_kmod-nf-conntrack-netlink=y
  98. +CONFIG_PACKAGE_kmod-nf-ipvs=y
  99. +CONFIG_PACKAGE_kmod-nfnetlink=y
  100. +CONFIG_PACKAGE_kmod-nls-cp437=y
  101. +CONFIG_PACKAGE_kmod-nls-iso8859-1=y
  102. +CONFIG_PACKAGE_kmod-nls-utf8=y
  103. +CONFIG_PACKAGE_kmod-rtl8812au-ct=y
  104. +CONFIG_PACKAGE_kmod-rtl8821ae=y
  105. +CONFIG_PACKAGE_kmod-rtl8xxxu=y
  106. +CONFIG_PACKAGE_kmod-rtlwifi=y
  107. +CONFIG_PACKAGE_kmod-rtlwifi-btcoexist=y
  108. +CONFIG_PACKAGE_kmod-rtlwifi-pci=y
  109. +CONFIG_PACKAGE_kmod-veth=y
  110. +CONFIG_PACKAGE_leech=y
  111. +CONFIG_PACKAGE_libatomic=y
  112. +CONFIG_PACKAGE_libattr=y
  113. +CONFIG_PACKAGE_libavahi-client=y
  114. +CONFIG_PACKAGE_libavahi-dbus-support=y
  115. +CONFIG_PACKAGE_libcap=y
  116. +CONFIG_PACKAGE_libcurl=y
  117. +CONFIG_PACKAGE_libdaemon=y
  118. +CONFIG_PACKAGE_libdbus=y
  119. +CONFIG_PACKAGE_libdevmapper=y
  120. +CONFIG_PACKAGE_libev=y
  121. +CONFIG_PACKAGE_libexpat=y
  122. +CONFIG_PACKAGE_libexslt=y
  123. +CONFIG_PACKAGE_libgmp=y
  124. +CONFIG_PACKAGE_libgnutls=y
  125. +CONFIG_PACKAGE_libiwinfo=y
  126. +CONFIG_PACKAGE_libiwinfo-lua=y
  127. +CONFIG_PACKAGE_liblua=y
  128. +CONFIG_PACKAGE_liblucihttp=y
  129. +CONFIG_PACKAGE_liblucihttp-lua=y
  130. +CONFIG_PACKAGE_liblzo=y
  131. +CONFIG_PACKAGE_libmbedtls=y
  132. +CONFIG_PACKAGE_libmount=y
  133. +CONFIG_PACKAGE_libncurses=y
  134. +CONFIG_PACKAGE_libnettle=y
  135. +CONFIG_PACKAGE_libnetwork=y
  136. +CONFIG_PACKAGE_libopenssl=y
  137. +CONFIG_PACKAGE_libopenssl-conf=y
  138. +CONFIG_PACKAGE_libpcre=y
  139. +CONFIG_PACKAGE_libpopt=y
  140. +CONFIG_PACKAGE_libreadline=y
  141. +CONFIG_PACKAGE_libseccomp=y
  142. +CONFIG_PACKAGE_libselinux=y
  143. +CONFIG_PACKAGE_libsepol=y
  144. +CONFIG_PACKAGE_libssh=y
  145. +CONFIG_PACKAGE_libssh2=y
  146. +CONFIG_PACKAGE_libstdcpp=y
  147. +CONFIG_PACKAGE_libtasn1=y
  148. +CONFIG_PACKAGE_libtirpc=y
  149. +CONFIG_PACKAGE_libubus-lua=y
  150. +CONFIG_PACKAGE_libustream-openssl=y
  151. +# CONFIG_PACKAGE_libustream-wolfssl is not set
  152. +CONFIG_PACKAGE_libuv=y
  153. +CONFIG_PACKAGE_libwebsockets-full=y
  154. +CONFIG_PACKAGE_libxml2=y
  155. +CONFIG_PACKAGE_libxslt=y
  156. +CONFIG_PACKAGE_lua=y
  157. +CONFIG_PACKAGE_luci=y
  158. +CONFIG_PACKAGE_luci-app-adblock=y
  159. +CONFIG_PACKAGE_luci-app-aria2=y
  160. +CONFIG_PACKAGE_luci-app-commands=y
  161. +CONFIG_PACKAGE_luci-app-dockerman=y
  162. +CONFIG_PACKAGE_luci-app-firewall=y
  163. +CONFIG_PACKAGE_luci-app-opkg=y
  164. +CONFIG_PACKAGE_luci-app-samba4=y
  165. +CONFIG_PACKAGE_luci-app-ttyd=y
  166. +CONFIG_PACKAGE_luci-base=y
  167. +CONFIG_PACKAGE_luci-compat=y
  168. +CONFIG_PACKAGE_luci-i18n-adblock-zh-cn=y
  169. +CONFIG_PACKAGE_luci-i18n-aria2-zh-cn=y
  170. +CONFIG_PACKAGE_luci-i18n-base-zh-cn=y
  171. +CONFIG_PACKAGE_luci-i18n-commands-zh-cn=y
  172. +CONFIG_PACKAGE_luci-i18n-dockerman-zh-cn=y
  173. +CONFIG_PACKAGE_luci-i18n-firewall-zh-cn=y
  174. +CONFIG_PACKAGE_luci-i18n-opkg-zh-cn=y
  175. +CONFIG_PACKAGE_luci-i18n-samba4-zh-cn=y
  176. +CONFIG_PACKAGE_luci-i18n-ttyd-zh-cn=y
  177. +CONFIG_PACKAGE_luci-lib-base=y
  178. +CONFIG_PACKAGE_luci-lib-docker=y
  179. +CONFIG_PACKAGE_luci-lib-ip=y
  180. +CONFIG_PACKAGE_luci-lib-ipkg=y
  181. +CONFIG_PACKAGE_luci-lib-jsonc=y
  182. +CONFIG_PACKAGE_luci-lib-nixio=y
  183. +CONFIG_PACKAGE_luci-mod-admin-full=y
  184. +CONFIG_PACKAGE_luci-mod-network=y
  185. +CONFIG_PACKAGE_luci-mod-status=y
  186. +CONFIG_PACKAGE_luci-mod-system=y
  187. +CONFIG_PACKAGE_luci-proto-ipv6=y
  188. +CONFIG_PACKAGE_luci-proto-ppp=y
  189. +CONFIG_PACKAGE_luci-ssl-openssl=y
  190. +CONFIG_PACKAGE_luci-theme-bootstrap=y
  191. +CONFIG_PACKAGE_mount-utils=y
  192. +CONFIG_PACKAGE_musl-fts=y
  193. +CONFIG_PACKAGE_openssh-keygen=y
  194. +CONFIG_PACKAGE_openssh-server=y
  195. +CONFIG_PACKAGE_openssl-util=y
  196. +CONFIG_PACKAGE_px5g-wolfssl=y
  197. +CONFIG_PACKAGE_rpcd=y
  198. +CONFIG_PACKAGE_rpcd-mod-file=y
  199. +CONFIG_PACKAGE_rpcd-mod-iwinfo=y
  200. +CONFIG_PACKAGE_rpcd-mod-luci=y
  201. +CONFIG_PACKAGE_rpcd-mod-rrdns=y
  202. +CONFIG_PACKAGE_rtl8188eu-firmware=y
  203. +CONFIG_PACKAGE_rtl8723au-firmware=y
  204. +CONFIG_PACKAGE_rtl8723bu-firmware=y
  205. +CONFIG_PACKAGE_rtl8821ae-firmware=y
  206. +CONFIG_PACKAGE_rtty-openssl=y
  207. +CONFIG_PACKAGE_runc=y
  208. +CONFIG_PACKAGE_samba4-libs=y
  209. +CONFIG_PACKAGE_samba4-server=y
  210. +CONFIG_PACKAGE_terminfo=y
  211. +CONFIG_PACKAGE_tini=y
  212. +CONFIG_PACKAGE_ttyd=y
  213. +CONFIG_PACKAGE_uhttpd=y
  214. +CONFIG_PACKAGE_uhttpd-mod-ubus=y
  215. +CONFIG_PACKAGE_webui-aria2=y
  216. +CONFIG_PACKAGE_wireless-regdb=y
  217. +CONFIG_PACKAGE_wsdd2=y
  218. +CONFIG_PACKAGE_xsltproc=y
  219. +CONFIG_PACKAGE_zlib=y
  220. +CONFIG_SAMBA4_SERVER_AVAHI=y
  221. +CONFIG_SAMBA4_SERVER_NETBIOS=y
  222. +CONFIG_SAMBA4_SERVER_VFS=y
  223. +CONFIG_TARGET_ROOTFS_PARTSIZE=512
  224. diff -aurNp '--exclude=.git' openwrt/package/base-files/files/bin/config_generate openwrt-china/package/base-files/files/bin/config_generate
  225. --- openwrt/package/base-files/files/bin/config_generate 2021-02-20 20:40:39.218922871 +0100
  226. +++ openwrt-china/package/base-files/files/bin/config_generate 2021-02-20 19:18:16.024626139 +0100
  227. @@ -140,8 +140,8 @@ generate_network() {
  228. static)
  229. local ipad
  230. case "$1" in
  231. - lan) ipad=${ipaddr:-"192.168.1.1"} ;;
  232. - *) ipad=${ipaddr:-"192.168.$((addr_offset++)).1"} ;;
  233. + lan) ipad=${ipaddr:-"192.168.2.1"} ;;
  234. + *) ipad=${ipaddr:-"192.168.$((addr_offset++)).1"} ;;
  235. esac
  236.  
  237. netm=${netmask:-"255.255.255.0"}
  238. diff -aurNp '--exclude=.git' openwrt/package/boot/uboot-rockchip/Makefile openwrt-china/package/boot/uboot-rockchip/Makefile
  239. --- openwrt/package/boot/uboot-rockchip/Makefile 2021-02-20 20:42:34.842526529 +0100
  240. +++ openwrt-china/package/boot/uboot-rockchip/Makefile 2021-02-20 19:18:16.040625525 +0100
  241. @@ -24,12 +24,12 @@ endef
  242.  
  243. # RK3328 boards
  244.  
  245. -define U-Boot/nanopi-r2s-rk3328
  246. +define U-Boot/orangepi-r1plus-rk3328
  247. BUILD_SUBTARGET:=armv8
  248. - NAME:=NanoPi R2S
  249. + NAME:=OrangePi R1Plus
  250. BUILD_DEVICES:= \
  251. - friendlyarm_nanopi-r2s
  252. - DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rockchip
  253. + xunlong_orangepi-r1plus
  254. + DEPENDS:=+PACKAGE_u-boot-orangepi-r1plus-rk3328:arm-trusted-firmware-rockchip
  255. PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
  256. ATF:=rk3328_bl31.elf
  257. OF_PLATDATA:=$(1)
  258. @@ -61,7 +61,8 @@ endef
  259. UBOOT_TARGETS := \
  260. rock-pi-4-rk3399 \
  261. rockpro64-rk3399 \
  262. - nanopi-r2s-rk3328
  263. + nanopi-r2s-rk3328 \
  264. + orangepi-r1plus-rk3328
  265.  
  266. UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
  267.  
  268. diff -aurNp '--exclude=.git' openwrt/package/boot/uboot-rockchip/patches/101-add-orangepi-r1plus-config.patch openwrt-china/package/boot/uboot-rockchip/patches/101-add-orangepi-r1plus-config.patch
  269. --- openwrt/package/boot/uboot-rockchip/patches/101-add-orangepi-r1plus-config.patch 1970-01-01 01:00:00.000000000 +0100
  270. +++ openwrt-china/package/boot/uboot-rockchip/patches/101-add-orangepi-r1plus-config.patch 2021-02-20 19:18:16.040625525 +0100
  271. @@ -0,0 +1,515 @@
  272. +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
  273. +index 700f02e2..a4a81369 100644
  274. +--- a/arch/arm/dts/Makefile
  275. ++++ b/arch/arm/dts/Makefile
  276. +@@ -107,6 +107,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
  277. + dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  278. + rk3328-evb.dtb \
  279. + rk3328-nanopi-r2s.dtb \
  280. ++ rk3328-orangepi-r1plus.dtb \
  281. + rk3328-roc-cc.dtb \
  282. + rk3328-rock64.dtb \
  283. + rk3328-rock-pi-e.dtb
  284. +diff --git a/arch/arm/dts/rk3328-orangepi-r1plus-u-boot.dtsi b/arch/arm/dts/rk3328-orangepi-r1plus-u-boot.dtsi
  285. +new file mode 100644
  286. +index 00000000..41593484
  287. +--- /dev/null
  288. ++++ b/arch/arm/dts/rk3328-orangepi-r1plus-u-boot.dtsi
  289. +@@ -0,0 +1,34 @@
  290. ++// SPDX-License-Identifier: GPL-2.0+
  291. ++/*
  292. ++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  293. ++ * (C) Copyright 2020 David Bauer
  294. ++ */
  295. ++
  296. ++#include "rk3328-u-boot.dtsi"
  297. ++#include "rk3328-sdram-ddr4-666.dtsi"
  298. ++/ {
  299. ++ chosen {
  300. ++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  301. ++ };
  302. ++};
  303. ++
  304. ++&gpio0 {
  305. ++ u-boot,dm-spl;
  306. ++};
  307. ++
  308. ++&pinctrl {
  309. ++ u-boot,dm-spl;
  310. ++};
  311. ++
  312. ++&sdmmc0m1_gpio {
  313. ++ u-boot,dm-spl;
  314. ++};
  315. ++
  316. ++&pcfg_pull_up_4ma {
  317. ++ u-boot,dm-spl;
  318. ++};
  319. ++
  320. ++/* Need this and all the pinctrl/gpio stuff above to set pinmux */
  321. ++&vcc_sd {
  322. ++ u-boot,dm-spl;
  323. ++};
  324. +diff --git a/arch/arm/dts/rk3328-orangepi-r1plus.dts b/arch/arm/dts/rk3328-orangepi-r1plus.dts
  325. +new file mode 100644
  326. +index 00000000..b8dc25e6
  327. +--- /dev/null
  328. ++++ b/arch/arm/dts/rk3328-orangepi-r1plus.dts
  329. +@@ -0,0 +1,334 @@
  330. ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  331. ++/*
  332. ++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
  333. ++ */
  334. ++
  335. ++/dts-v1/;
  336. ++
  337. ++#include <dt-bindings/input/input.h>
  338. ++#include <dt-bindings/gpio/gpio.h>
  339. ++#include "rk3328.dtsi"
  340. ++
  341. ++/ {
  342. ++ model = "Xunlong OrangePi R1PLUS";
  343. ++ compatible = "xunlong,orangepi-r1plus", "rockchip,rk3328";
  344. ++
  345. ++ chosen {
  346. ++ stdout-path = "serial2:1500000n8";
  347. ++ };
  348. ++
  349. ++ gmac_clkin: external-gmac-clock {
  350. ++ compatible = "fixed-clock";
  351. ++ clock-frequency = <125000000>;
  352. ++ clock-output-names = "gmac_clkin";
  353. ++ #clock-cells = <0>;
  354. ++ };
  355. ++
  356. ++ vcc_sd: sdmmc-regulator {
  357. ++ compatible = "regulator-fixed";
  358. ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
  359. ++ pinctrl-names = "default";
  360. ++ pinctrl-0 = <&sdmmc0m1_gpio>;
  361. ++ regulator-name = "vcc_sd";
  362. ++ regulator-min-microvolt = <3300000>;
  363. ++ regulator-max-microvolt = <3300000>;
  364. ++ vin-supply = <&vcc_io>;
  365. ++ };
  366. ++
  367. ++ vcc_sdio: sdmmcio-regulator {
  368. ++ compatible = "regulator-gpio";
  369. ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
  370. ++ enable-active-high;
  371. ++ states = <1800000 0x1
  372. ++ 3300000 0x0>;
  373. ++ pinctrl-names = "default";
  374. ++ pinctrl-0 = <&sdio_vcc_pin>;
  375. ++ regulator-always-on;
  376. ++ regulator-min-microvolt = <1800000>;
  377. ++ regulator-max-microvolt = <3300000>;
  378. ++ regulator-name = "vcc_sdio";
  379. ++ regulator-settling-time-us = <5000>;
  380. ++ regulator-type = "voltage";
  381. ++ vin-supply = <&vcc_io>;
  382. ++ };
  383. ++
  384. ++ vcc_sys: vcc-sys {
  385. ++ compatible = "regulator-fixed";
  386. ++ regulator-name = "vcc_sys";
  387. ++ regulator-always-on;
  388. ++ regulator-boot-on;
  389. ++ regulator-min-microvolt = <5000000>;
  390. ++ regulator-max-microvolt = <5000000>;
  391. ++ };
  392. ++
  393. ++ leds {
  394. ++ compatible = "gpio-leds";
  395. ++
  396. ++ pinctrl-names = "default";
  397. ++ pinctrl-0 = <&led_pins>;
  398. ++
  399. ++ sys {
  400. ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
  401. ++ label = "orangepi-r1plus:red:sys";
  402. ++ };
  403. ++
  404. ++ lan {
  405. ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
  406. ++ label = "orangepi-r1plus:green:lan";
  407. ++ };
  408. ++
  409. ++ wan {
  410. ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
  411. ++ label = "orangepi-r1plus:green:wan";
  412. ++ };
  413. ++ };
  414. ++
  415. ++ gpio_keys {
  416. ++ compatible = "gpio-keys-polled";
  417. ++ poll-interval = <100>;
  418. ++
  419. ++ pinctrl-names = "default";
  420. ++ pinctrl-0 = <&button_pins>;
  421. ++
  422. ++ reset {
  423. ++ label = "Reset Button";
  424. ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
  425. ++ linux,code = <KEY_RESTART>;
  426. ++ debounce-interval = <50>;
  427. ++ };
  428. ++ };
  429. ++};
  430. ++
  431. ++&cpu0 {
  432. ++ cpu-supply = <&vdd_arm>;
  433. ++};
  434. ++
  435. ++&cpu1 {
  436. ++ cpu-supply = <&vdd_arm>;
  437. ++};
  438. ++
  439. ++&cpu2 {
  440. ++ cpu-supply = <&vdd_arm>;
  441. ++};
  442. ++
  443. ++&cpu3 {
  444. ++ cpu-supply = <&vdd_arm>;
  445. ++};
  446. ++
  447. ++&gmac2io {
  448. ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
  449. ++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
  450. ++ clock_in_out = "input";
  451. ++ phy-supply = <&vcc_io>;
  452. ++ phy-handle = <&rtl8211e>;
  453. ++ phy-mode = "rgmii";
  454. ++ pinctrl-names = "default";
  455. ++ pinctrl-0 = <&rgmiim1_pins>;
  456. ++ snps,aal;
  457. ++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  458. ++ snps,reset-active-low;
  459. ++ snps,reset-delays-us = <0 10000 50000>;
  460. ++ tx_delay = <0x24>;
  461. ++ rx_delay = <0x18>;
  462. ++ status = "okay";
  463. ++
  464. ++ mdio {
  465. ++ compatible = "snps,dwmac-mdio";
  466. ++ #address-cells = <1>;
  467. ++ #size-cells = <0>;
  468. ++
  469. ++ rtl8211e: ethernet-phy@0 {
  470. ++ reg = <0>;
  471. ++ };
  472. ++ };
  473. ++};
  474. ++
  475. ++&i2c1 {
  476. ++ status = "okay";
  477. ++
  478. ++ rk805: rk805@18 {
  479. ++ compatible = "rockchip,rk805";
  480. ++ reg = <0x18>;
  481. ++ interrupt-parent = <&gpio2>;
  482. ++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
  483. ++ #clock-cells = <1>;
  484. ++ clock-output-names = "xin32k", "rk805-clkout2";
  485. ++ gpio-controller;
  486. ++ #gpio-cells = <2>;
  487. ++ pinctrl-names = "default";
  488. ++ pinctrl-0 = <&pmic_int_l>;
  489. ++ rockchip,system-power-controller;
  490. ++ wakeup-source;
  491. ++
  492. ++ vcc1-supply = <&vcc_sys>;
  493. ++ vcc2-supply = <&vcc_sys>;
  494. ++ vcc3-supply = <&vcc_sys>;
  495. ++ vcc4-supply = <&vcc_sys>;
  496. ++ vcc5-supply = <&vcc_io>;
  497. ++ vcc6-supply = <&vcc_sys>;
  498. ++
  499. ++ regulators {
  500. ++ vdd_logic: DCDC_REG1 {
  501. ++ regulator-name = "vdd_logic";
  502. ++ regulator-min-microvolt = <712500>;
  503. ++ regulator-max-microvolt = <1450000>;
  504. ++ regulator-ramp-delay = <12500>;
  505. ++ regulator-always-on;
  506. ++ regulator-boot-on;
  507. ++ regulator-state-mem {
  508. ++ regulator-on-in-suspend;
  509. ++ regulator-suspend-microvolt = <1000000>;
  510. ++ };
  511. ++ };
  512. ++
  513. ++ vdd_arm: DCDC_REG2 {
  514. ++ regulator-name = "vdd_arm";
  515. ++ regulator-min-microvolt = <712500>;
  516. ++ regulator-max-microvolt = <1450000>;
  517. ++ regulator-ramp-delay = <12500>;
  518. ++ regulator-always-on;
  519. ++ regulator-boot-on;
  520. ++ regulator-state-mem {
  521. ++ regulator-on-in-suspend;
  522. ++ regulator-suspend-microvolt = <950000>;
  523. ++ };
  524. ++ };
  525. ++
  526. ++ vcc_ddr: DCDC_REG3 {
  527. ++ regulator-name = "vcc_ddr";
  528. ++ regulator-always-on;
  529. ++ regulator-boot-on;
  530. ++ regulator-state-mem {
  531. ++ regulator-on-in-suspend;
  532. ++ };
  533. ++ };
  534. ++
  535. ++ vcc_io: DCDC_REG4 {
  536. ++ regulator-name = "vcc_io";
  537. ++ regulator-min-microvolt = <3300000>;
  538. ++ regulator-max-microvolt = <3300000>;
  539. ++ regulator-always-on;
  540. ++ regulator-boot-on;
  541. ++ regulator-state-mem {
  542. ++ regulator-on-in-suspend;
  543. ++ regulator-suspend-microvolt = <3300000>;
  544. ++ };
  545. ++ };
  546. ++
  547. ++ vcc_18: LDO_REG1 {
  548. ++ regulator-name = "vcc_18";
  549. ++ regulator-min-microvolt = <1800000>;
  550. ++ regulator-max-microvolt = <1800000>;
  551. ++ regulator-always-on;
  552. ++ regulator-boot-on;
  553. ++ regulator-state-mem {
  554. ++ regulator-on-in-suspend;
  555. ++ regulator-suspend-microvolt = <1800000>;
  556. ++ };
  557. ++ };
  558. ++
  559. ++ vcc18_emmc: LDO_REG2 {
  560. ++ regulator-name = "vcc18_emmc";
  561. ++ regulator-min-microvolt = <1800000>;
  562. ++ regulator-max-microvolt = <1800000>;
  563. ++ regulator-always-on;
  564. ++ regulator-boot-on;
  565. ++ regulator-state-mem {
  566. ++ regulator-on-in-suspend;
  567. ++ regulator-suspend-microvolt = <1800000>;
  568. ++ };
  569. ++ };
  570. ++
  571. ++ vdd_10: LDO_REG3 {
  572. ++ regulator-name = "vdd_10";
  573. ++ regulator-min-microvolt = <1000000>;
  574. ++ regulator-max-microvolt = <1000000>;
  575. ++ regulator-always-on;
  576. ++ regulator-boot-on;
  577. ++ regulator-state-mem {
  578. ++ regulator-on-in-suspend;
  579. ++ regulator-suspend-microvolt = <1000000>;
  580. ++ };
  581. ++ };
  582. ++ };
  583. ++ };
  584. ++};
  585. ++
  586. ++&io_domains {
  587. ++ status = "okay";
  588. ++
  589. ++ vccio1-supply = <&vcc_io>;
  590. ++ vccio2-supply = <&vcc18_emmc>;
  591. ++ vccio3-supply = <&vcc_sdio>;
  592. ++ vccio4-supply = <&vcc_18>;
  593. ++ vccio5-supply = <&vcc_io>;
  594. ++ vccio6-supply = <&vcc_io>;
  595. ++ pmuio-supply = <&vcc_io>;
  596. ++};
  597. ++
  598. ++&pinctrl {
  599. ++ leds {
  600. ++ led_pins: led-pins {
  601. ++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
  602. ++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
  603. ++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
  604. ++ };
  605. ++ };
  606. ++
  607. ++ button {
  608. ++ button_pins: button-pins {
  609. ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
  610. ++ };
  611. ++ };
  612. ++
  613. ++ pmic {
  614. ++ pmic_int_l: pmic-int-l {
  615. ++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
  616. ++ };
  617. ++ };
  618. ++
  619. ++ sd {
  620. ++ sdio_vcc_pin: sdio-vcc-pin {
  621. ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
  622. ++ };
  623. ++ };
  624. ++};
  625. ++
  626. ++&sdmmc {
  627. ++ bus-width = <4>;
  628. ++ cap-mmc-highspeed;
  629. ++ cap-sd-highspeed;
  630. ++ disable-wp;
  631. ++ max-frequency = <150000000>;
  632. ++ pinctrl-names = "default";
  633. ++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
  634. ++ vmmc-supply = <&vcc_sd>;
  635. ++ vqmmc-supply = <&vcc_sdio>;
  636. ++ status = "okay";
  637. ++};
  638. ++
  639. ++&tsadc {
  640. ++ rockchip,hw-tshut-mode = <0>;
  641. ++ rockchip,hw-tshut-polarity = <0>;
  642. ++ status = "okay";
  643. ++};
  644. ++
  645. ++&uart2 {
  646. ++ status = "okay";
  647. ++};
  648. ++
  649. ++&u2phy {
  650. ++ status = "okay";
  651. ++
  652. ++ u2phy_host: host-port {
  653. ++ status = "okay";
  654. ++ };
  655. ++};
  656. ++
  657. ++&usb_host0_ehci {
  658. ++ status = "okay";
  659. ++};
  660. ++
  661. ++&usb_host0_ohci {
  662. ++ status = "okay";
  663. ++};
  664. +diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
  665. +index 14fda46e..612c785b 100644
  666. +--- a/board/rockchip/evb_rk3328/MAINTAINERS
  667. ++++ b/board/rockchip/evb_rk3328/MAINTAINERS
  668. +@@ -12,6 +12,13 @@ F: configs/nanopi-r2s-rk3328_defconfig
  669. + F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
  670. + F: arch/arm/dts/rk3328-nanopi-r2s.dts
  671. +
  672. ++ORANGEPI-R1PLUS-RK3328
  673. ++M: Zhao <zhao_steven@263.net>
  674. ++S: Maintained
  675. ++F: configs/orangepi-r1plus-rk3328_defconfig
  676. ++F: arch/arm/dts/rk3328-orangepi-r1plus-u-boot.dtsi
  677. ++F: arch/arm/dts/rk3328-orangepi-r1plus.dts
  678. ++
  679. + ROC-RK3328-CC
  680. + M: Loic Devulder <ldevulder@suse.com>
  681. + M: Chen-Yu Tsai <wens@csie.org>
  682. +diff --git a/configs/orangepi-r1plus-rk3328_defconfig b/configs/orangepi-r1plus-rk3328_defconfig
  683. +new file mode 100644
  684. +index 00000000..5389db20
  685. +--- /dev/null
  686. ++++ b/configs/orangepi-r1plus-rk3328_defconfig
  687. +@@ -0,0 +1,99 @@
  688. ++CONFIG_ARM=y
  689. ++CONFIG_ARCH_ROCKCHIP=y
  690. ++CONFIG_SYS_TEXT_BASE=0x00200000
  691. ++CONFIG_SPL_GPIO_SUPPORT=y
  692. ++CONFIG_ENV_OFFSET=0x3F8000
  693. ++CONFIG_ROCKCHIP_RK3328=y
  694. ++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
  695. ++CONFIG_TPL_LIBCOMMON_SUPPORT=y
  696. ++CONFIG_TPL_LIBGENERIC_SUPPORT=y
  697. ++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  698. ++CONFIG_SPL_STACK_R_ADDR=0x600000
  699. ++CONFIG_NR_DRAM_BANKS=1
  700. ++CONFIG_DEBUG_UART_BASE=0xFF130000
  701. ++CONFIG_DEBUG_UART_CLOCK=24000000
  702. ++CONFIG_SMBIOS_PRODUCT_NAME="orangepi_r1plus_rk3328"
  703. ++CONFIG_DEBUG_UART=y
  704. ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
  705. ++# CONFIG_ANDROID_BOOT_IMAGE is not set
  706. ++CONFIG_FIT=y
  707. ++CONFIG_FIT_VERBOSE=y
  708. ++CONFIG_SPL_LOAD_FIT=y
  709. ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1plus.dtb"
  710. ++CONFIG_MISC_INIT_R=y
  711. ++# CONFIG_DISPLAY_CPUINFO is not set
  712. ++CONFIG_DISPLAY_BOARDINFO_LATE=y
  713. ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
  714. ++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
  715. ++CONFIG_SPL_STACK_R=y
  716. ++CONFIG_SPL_I2C_SUPPORT=y
  717. ++CONFIG_SPL_POWER_SUPPORT=y
  718. ++CONFIG_SPL_ATF=y
  719. ++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
  720. ++CONFIG_CMD_BOOTZ=y
  721. ++CONFIG_CMD_GPT=y
  722. ++CONFIG_CMD_MMC=y
  723. ++CONFIG_CMD_USB=y
  724. ++# CONFIG_CMD_SETEXPR is not set
  725. ++CONFIG_CMD_TIME=y
  726. ++CONFIG_SPL_OF_CONTROL=y
  727. ++CONFIG_TPL_OF_CONTROL=y
  728. ++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1plus"
  729. ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
  730. ++CONFIG_TPL_OF_PLATDATA=y
  731. ++CONFIG_ENV_IS_IN_MMC=y
  732. ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  733. ++CONFIG_NET_RANDOM_ETHADDR=y
  734. ++CONFIG_TPL_DM=y
  735. ++CONFIG_REGMAP=y
  736. ++CONFIG_SPL_REGMAP=y
  737. ++CONFIG_TPL_REGMAP=y
  738. ++CONFIG_SYSCON=y
  739. ++CONFIG_SPL_SYSCON=y
  740. ++CONFIG_TPL_SYSCON=y
  741. ++CONFIG_CLK=y
  742. ++CONFIG_SPL_CLK=y
  743. ++CONFIG_FASTBOOT_BUF_ADDR=0x800800
  744. ++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
  745. ++CONFIG_ROCKCHIP_GPIO=y
  746. ++CONFIG_SYS_I2C_ROCKCHIP=y
  747. ++CONFIG_MMC_DW=y
  748. ++CONFIG_MMC_DW_ROCKCHIP=y
  749. ++CONFIG_SF_DEFAULT_SPEED=20000000
  750. ++CONFIG_DM_ETH=y
  751. ++CONFIG_ETH_DESIGNWARE=y
  752. ++CONFIG_GMAC_ROCKCHIP=y
  753. ++CONFIG_PINCTRL=y
  754. ++CONFIG_SPL_PINCTRL=y
  755. ++CONFIG_DM_PMIC=y
  756. ++CONFIG_PMIC_RK8XX=y
  757. ++CONFIG_SPL_DM_REGULATOR=y
  758. ++CONFIG_REGULATOR_PWM=y
  759. ++CONFIG_DM_REGULATOR_FIXED=y
  760. ++CONFIG_SPL_DM_REGULATOR_FIXED=y
  761. ++CONFIG_REGULATOR_RK8XX=y
  762. ++CONFIG_PWM_ROCKCHIP=y
  763. ++CONFIG_RAM=y
  764. ++CONFIG_SPL_RAM=y
  765. ++CONFIG_TPL_RAM=y
  766. ++CONFIG_DM_RESET=y
  767. ++CONFIG_BAUDRATE=1500000
  768. ++CONFIG_DEBUG_UART_SHIFT=2
  769. ++CONFIG_SYSRESET=y
  770. ++# CONFIG_TPL_SYSRESET is not set
  771. ++CONFIG_USB=y
  772. ++CONFIG_USB_XHCI_HCD=y
  773. ++CONFIG_USB_XHCI_DWC3=y
  774. ++CONFIG_USB_EHCI_HCD=y
  775. ++CONFIG_USB_EHCI_GENERIC=y
  776. ++CONFIG_USB_OHCI_HCD=y
  777. ++CONFIG_USB_OHCI_GENERIC=y
  778. ++CONFIG_USB_DWC2=y
  779. ++CONFIG_USB_DWC3=y
  780. ++# CONFIG_USB_DWC3_GADGET is not set
  781. ++CONFIG_USB_GADGET=y
  782. ++CONFIG_USB_GADGET_DWC2_OTG=y
  783. ++CONFIG_SPL_TINY_MEMSET=y
  784. ++CONFIG_TPL_TINY_MEMSET=y
  785. ++CONFIG_ERRNO_STR=y
  786. ++CONFIG_SMBIOS_MANUFACTURER="pine64"
  787. diff -aurNp '--exclude=.git' openwrt/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-platdata.c openwrt-china/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-platdata.c
  788. --- openwrt/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-platdata.c 1970-01-01 01:00:00.000000000 +0100
  789. +++ openwrt-china/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-platdata.c 2021-02-20 19:18:16.040625525 +0100
  790. @@ -0,0 +1,149 @@
  791. +/*
  792. + * DO NOT MODIFY
  793. + *
  794. + * This file was generated by dtoc from a .dtb (device tree binary) file.
  795. + */
  796. +
  797. +#include <common.h>
  798. +#include <dm.h>
  799. +#include <dt-structs.h>
  800. +
  801. +static const struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
  802. + .reg = {0xff100000, 0x1000},
  803. +};
  804. +U_BOOT_DEVICE(syscon_at_ff100000) = {
  805. + .name = "rockchip_rk3328_grf",
  806. + .platdata = &dtv_syscon_at_ff100000,
  807. + .platdata_size = sizeof(dtv_syscon_at_ff100000),
  808. +};
  809. +
  810. +static const struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
  811. + .reg = {0xff440000, 0x1000},
  812. + .rockchip_grf = 0x3a,
  813. +};
  814. +U_BOOT_DEVICE(clock_controller_at_ff440000) = {
  815. + .name = "rockchip_rk3328_cru",
  816. + .platdata = &dtv_clock_controller_at_ff440000,
  817. + .platdata_size = sizeof(dtv_clock_controller_at_ff440000),
  818. +};
  819. +
  820. +static const struct dtd_rockchip_rk3328_uart dtv_serial_at_ff130000 = {
  821. + .clock_frequency = 0x16e3600,
  822. + .clocks = {
  823. + {&dtv_clock_controller_at_ff440000, {40}},
  824. + {&dtv_clock_controller_at_ff440000, {212}},},
  825. + .dma_names = {"tx", "rx"},
  826. + .dmas = {0x10, 0x6, 0x10, 0x7},
  827. + .interrupts = {0x0, 0x39, 0x4},
  828. + .pinctrl_0 = 0x26,
  829. + .pinctrl_names = "default",
  830. + .reg = {0xff130000, 0x100},
  831. + .reg_io_width = 0x4,
  832. + .reg_shift = 0x2,
  833. +};
  834. +U_BOOT_DEVICE(serial_at_ff130000) = {
  835. + .name = "rockchip_rk3328_uart",
  836. + .platdata = &dtv_serial_at_ff130000,
  837. + .platdata_size = sizeof(dtv_serial_at_ff130000),
  838. +};
  839. +
  840. +static const struct dtd_rockchip_rk3328_dw_mshc dtv_mmc_at_ff500000 = {
  841. + .bus_width = 0x4,
  842. + .cap_mmc_highspeed = true,
  843. + .cap_sd_highspeed = true,
  844. + .clocks = {
  845. + {&dtv_clock_controller_at_ff440000, {317}},
  846. + {&dtv_clock_controller_at_ff440000, {33}},
  847. + {&dtv_clock_controller_at_ff440000, {74}},
  848. + {&dtv_clock_controller_at_ff440000, {78}},},
  849. + .disable_wp = true,
  850. + .fifo_depth = 0x100,
  851. + .interrupts = {0x0, 0xc, 0x4},
  852. + .max_frequency = 0x8f0d180,
  853. + .pinctrl_0 = {0x47, 0x48, 0x49, 0x4a},
  854. + .pinctrl_names = "default",
  855. + .reg = {0xff500000, 0x4000},
  856. + .u_boot_spl_fifo_mode = true,
  857. + .vmmc_supply = 0x4b,
  858. + .vqmmc_supply = 0x1e,
  859. +};
  860. +U_BOOT_DEVICE(mmc_at_ff500000) = {
  861. + .name = "rockchip_rk3328_dw_mshc",
  862. + .platdata = &dtv_mmc_at_ff500000,
  863. + .platdata_size = sizeof(dtv_mmc_at_ff500000),
  864. +};
  865. +
  866. +static const struct dtd_rockchip_rk3328_pinctrl dtv_pinctrl = {
  867. + .ranges = true,
  868. + .rockchip_grf = 0x3a,
  869. +};
  870. +U_BOOT_DEVICE(pinctrl) = {
  871. + .name = "rockchip_rk3328_pinctrl",
  872. + .platdata = &dtv_pinctrl,
  873. + .platdata_size = sizeof(dtv_pinctrl),
  874. +};
  875. +
  876. +static const struct dtd_rockchip_gpio_bank dtv_gpio0_at_ff210000 = {
  877. + .clocks = {
  878. + {&dtv_clock_controller_at_ff440000, {200}},},
  879. + .gpio_controller = true,
  880. + .interrupt_controller = true,
  881. + .interrupts = {0x0, 0x33, 0x4},
  882. + .reg = {0xff210000, 0x100},
  883. +};
  884. +U_BOOT_DEVICE(gpio0_at_ff210000) = {
  885. + .name = "rockchip_gpio_bank",
  886. + .platdata = &dtv_gpio0_at_ff210000,
  887. + .platdata_size = sizeof(dtv_gpio0_at_ff210000),
  888. +};
  889. +
  890. +static const struct dtd_regulator_fixed dtv_sdmmc_regulator = {
  891. + .gpio = {0x60, 0x1e, 0x1},
  892. + .pinctrl_0 = 0x61,
  893. + .pinctrl_names = "default",
  894. + .regulator_max_microvolt = 0x325aa0,
  895. + .regulator_min_microvolt = 0x325aa0,
  896. + .regulator_name = "vcc_sd",
  897. + .vin_supply = 0x1c,
  898. +};
  899. +U_BOOT_DEVICE(sdmmc_regulator) = {
  900. + .name = "regulator_fixed",
  901. + .platdata = &dtv_sdmmc_regulator,
  902. + .platdata_size = sizeof(dtv_sdmmc_regulator),
  903. +};
  904. +
  905. +static const struct dtd_rockchip_rk3328_dmc dtv_dmc = {
  906. + .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
  907. + 0xff720000, 0x1000, 0xff798000, 0x1000},
  908. + .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
  909. + 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
  910. + 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
  911. + 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
  912. + 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
  913. + 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
  914. + 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
  915. + 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
  916. + 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
  917. + 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
  918. + 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
  919. + 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
  920. + 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
  921. + 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
  922. + 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
  923. + 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
  924. + 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  925. + 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
  926. + 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
  927. + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
  928. + 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
  929. + 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
  930. + 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
  931. + 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
  932. + 0x77, 0x77, 0x79, 0x9},
  933. +};
  934. +U_BOOT_DEVICE(dmc) = {
  935. + .name = "rockchip_rk3328_dmc",
  936. + .platdata = &dtv_dmc,
  937. + .platdata_size = sizeof(dtv_dmc),
  938. +};
  939. +
  940. diff -aurNp '--exclude=.git' openwrt/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-structs-gen.h openwrt-china/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-structs-gen.h
  941. --- openwrt/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-structs-gen.h 1970-01-01 01:00:00.000000000 +0100
  942. +++ openwrt-china/package/boot/uboot-rockchip/src/of-platdata/orangepi-r1plus-rk3328/dt-structs-gen.h 2021-02-20 19:18:16.040625525 +0100
  943. @@ -0,0 +1,72 @@
  944. +/*
  945. + * DO NOT MODIFY
  946. + *
  947. + * This file was generated by dtoc from a .dtb (device tree binary) file.
  948. + */
  949. +
  950. +#include <stdbool.h>
  951. +#include <linux/libfdt.h>
  952. +struct dtd_regulator_fixed {
  953. + fdt32_t gpio[3];
  954. + fdt32_t pinctrl_0;
  955. + const char * pinctrl_names;
  956. + fdt32_t regulator_max_microvolt;
  957. + fdt32_t regulator_min_microvolt;
  958. + const char * regulator_name;
  959. + fdt32_t vin_supply;
  960. +};
  961. +struct dtd_rockchip_gpio_bank {
  962. + struct phandle_1_arg clocks[1];
  963. + bool gpio_controller;
  964. + bool interrupt_controller;
  965. + fdt32_t interrupts[3];
  966. + fdt64_t reg[2];
  967. +};
  968. +struct dtd_rockchip_rk3328_cru {
  969. + fdt64_t reg[2];
  970. + fdt32_t rockchip_grf;
  971. +};
  972. +struct dtd_rockchip_rk3328_dmc {
  973. + fdt64_t reg[12];
  974. + fdt32_t rockchip_sdram_params[196];
  975. +};
  976. +struct dtd_rockchip_rk3328_dw_mshc {
  977. + fdt32_t bus_width;
  978. + bool cap_mmc_highspeed;
  979. + bool cap_sd_highspeed;
  980. + struct phandle_1_arg clocks[4];
  981. + bool disable_wp;
  982. + fdt32_t fifo_depth;
  983. + fdt32_t interrupts[3];
  984. + fdt32_t max_frequency;
  985. + fdt32_t pinctrl_0[4];
  986. + const char * pinctrl_names;
  987. + fdt64_t reg[2];
  988. + bool u_boot_spl_fifo_mode;
  989. + fdt32_t vmmc_supply;
  990. + fdt32_t vqmmc_supply;
  991. +};
  992. +struct dtd_rockchip_rk3328_grf {
  993. + fdt64_t reg[2];
  994. +};
  995. +struct dtd_rockchip_rk3328_pinctrl {
  996. + bool ranges;
  997. + fdt32_t rockchip_grf;
  998. +};
  999. +struct dtd_rockchip_rk3328_uart {
  1000. + fdt32_t clock_frequency;
  1001. + struct phandle_1_arg clocks[2];
  1002. + const char * dma_names[2];
  1003. + fdt32_t dmas[4];
  1004. + fdt32_t interrupts[3];
  1005. + fdt32_t pinctrl_0;
  1006. + const char * pinctrl_names;
  1007. + fdt64_t reg[2];
  1008. + fdt32_t reg_io_width;
  1009. + fdt32_t reg_shift;
  1010. +};
  1011. +#define dtd_syscon dtd_rockchip_rk3328_cru
  1012. +#define dtd_simple_mfd dtd_rockchip_rk3328_grf
  1013. +#define dtd_snps_dw_apb_uart dtd_rockchip_rk3328_uart
  1014. +#define dtd_rockchip_cru dtd_rockchip_rk3328_cru
  1015. +#define dtd_rockchip_rk3288_dw_mshc dtd_rockchip_rk3328_dw_mshc
  1016. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds openwrt-china/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
  1017. --- openwrt/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds 2021-02-20 20:40:39.702904477 +0100
  1018. +++ openwrt-china/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds 2021-02-20 19:18:16.368612950 +0100
  1019. @@ -9,9 +9,9 @@ boardname="${board##*,}"
  1020. board_config_update
  1021.  
  1022. case $board in
  1023. -friendlyarm,nanopi-r2s)
  1024. - ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
  1025. - ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
  1026. +xunlong,orangepi-r1plus)
  1027. + ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth1"
  1028. + ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0"
  1029. ;;
  1030. esac
  1031.  
  1032. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/armv8/base-files/etc/board.d/02_network openwrt-china/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
  1033. --- openwrt/target/linux/rockchip/armv8/base-files/etc/board.d/02_network 2021-02-20 20:42:20.891057228 +0100
  1034. +++ openwrt-china/target/linux/rockchip/armv8/base-files/etc/board.d/02_network 2021-02-20 19:18:16.368612950 +0100
  1035. @@ -8,11 +8,12 @@ rockchip_setup_interfaces()
  1036. local board="$1"
  1037.  
  1038. case "$board" in
  1039. - friendlyarm,nanopi-r2s)
  1040. + xunlong,orangepi-r1plus)
  1041. ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
  1042. ;;
  1043. *)
  1044. - ucidef_set_interface_lan 'eth0'
  1045. + # ucidef_set_interface_lan 'eth1'
  1046. + ucidef_set_interfaces_lan_wan 'eth1'
  1047. ;;
  1048. esac
  1049. }
  1050. @@ -32,9 +33,10 @@ rockchip_setup_macs()
  1051. local label_mac=""
  1052.  
  1053. case "$board" in
  1054. - friendlyarm,nanopi-r2s)
  1055. - wan_mac=$(nanopi_r2s_generate_mac)
  1056. - lan_mac=$(macaddr_add "$wan_mac" +1)
  1057. + xunlong,orangepi-r1plus)
  1058. + #wan_mac=$(macaddr_random)
  1059. + lan_mac=$(cat /sys/class/net/eth1/address)
  1060. + wan_mac=$(macaddr_add "$lan_mac" -1)
  1061. ;;
  1062. esac
  1063.  
  1064. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity openwrt-china/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity
  1065. --- openwrt/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity 2021-02-20 20:40:39.702904477 +0100
  1066. +++ openwrt-china/target/linux/rockchip/armv8/base-files/etc/hotplug.d/net/40-net-smp-affinity 2021-02-20 19:18:16.368612950 +0100
  1067. @@ -22,7 +22,7 @@ set_interface_core() {
  1068. }
  1069.  
  1070. case "$(board_name)" in
  1071. -friendlyarm,nanopi-r2s)
  1072. +xunlong,orangepi-r1plus)
  1073. set_interface_core 2 "eth0"
  1074. set_interface_core 4 "eth1" "xhci-hcd:usb3"
  1075. ;;
  1076. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/image/armv8.mk openwrt-china/target/linux/rockchip/image/armv8.mk
  1077. --- openwrt/target/linux/rockchip/image/armv8.mk 2021-02-20 20:41:54.224071447 +0100
  1078. +++ openwrt-china/target/linux/rockchip/image/armv8.mk 2021-02-20 19:18:16.368612950 +0100
  1079. @@ -2,15 +2,15 @@
  1080. #
  1081. # Copyright (C) 2020 Tobias Maedel
  1082.  
  1083. -define Device/friendlyarm_nanopi-r2s
  1084. - DEVICE_VENDOR := FriendlyARM
  1085. - DEVICE_MODEL := NanoPi R2S
  1086. +define Device/xunlong_orangepi-r1plus
  1087. + DEVICE_VENDOR := Xunlong
  1088. + DEVICE_MODEL := OrangePi R1Plus
  1089. SOC := rk3328
  1090. - UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
  1091. - IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata
  1092. + UBOOT_DEVICE_NAME := orangepi-r1plus-rk3328
  1093. + IMAGE/sysupgrade.img.gz := boot-common | boot-script orangepi-r1plus | pine64-img | gzip | append-metadata
  1094. DEVICE_PACKAGES := kmod-usb-net-rtl8152
  1095. endef
  1096. -TARGET_DEVICES += friendlyarm_nanopi-r2s
  1097. +TARGET_DEVICES += xunlong_orangepi-r1plus
  1098.  
  1099. define Device/pine64_rockpro64
  1100. DEVICE_VENDOR := Pine64
  1101. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/image/orangepi-r1plus.bootscript openwrt-china/target/linux/rockchip/image/orangepi-r1plus.bootscript
  1102. --- openwrt/target/linux/rockchip/image/orangepi-r1plus.bootscript 1970-01-01 01:00:00.000000000 +0100
  1103. +++ openwrt-china/target/linux/rockchip/image/orangepi-r1plus.bootscript 2021-02-20 19:18:16.368612950 +0100
  1104. @@ -0,0 +1,8 @@
  1105. +part uuid mmc ${devnum}:2 uuid
  1106. +
  1107. +setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait"
  1108. +
  1109. +load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
  1110. +load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
  1111. +
  1112. +booti ${kernel_addr_r} - ${fdt_addr_r}
  1113. diff -aurNp '--exclude=.git' openwrt/target/linux/rockchip/patches-5.4/104-add-orangepir1plus-dts.patch openwrt-china/target/linux/rockchip/patches-5.4/104-add-orangepir1plus-dts.patch
  1114. --- openwrt/target/linux/rockchip/patches-5.4/104-add-orangepir1plus-dts.patch 1970-01-01 01:00:00.000000000 +0100
  1115. +++ openwrt-china/target/linux/rockchip/patches-5.4/104-add-orangepir1plus-dts.patch 2021-02-20 19:18:16.372612796 +0100
  1116. @@ -0,0 +1,433 @@
  1117. +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
  1118. +index 3d011c4e6..23373c752 100644
  1119. +--- a/arch/arm64/boot/dts/rockchip/Makefile
  1120. ++++ b/arch/arm64/boot/dts/rockchip/Makefile
  1121. +@@ -2,6 +2,7 @@
  1122. + dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
  1123. + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
  1124. + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
  1125. ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1plus.dtb
  1126. + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  1127. + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
  1128. + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
  1129. +diff --git a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1plus.dts b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1plus.dts
  1130. +new file mode 100644
  1131. +index 000000000..7e4e9d7b4
  1132. +--- /dev/null
  1133. ++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1plus.dts
  1134. +@@ -0,0 +1,415 @@
  1135. ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  1136. ++/*
  1137. ++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
  1138. ++ */
  1139. ++
  1140. ++/dts-v1/;
  1141. ++
  1142. ++#include <dt-bindings/input/input.h>
  1143. ++#include <dt-bindings/gpio/gpio.h>
  1144. ++#include "rk3328.dtsi"
  1145. ++
  1146. ++/ {
  1147. ++ model = "Orange Pi R1 PLUS";
  1148. ++ compatible = "xunlong,orangepi-r1plus", "rockchip,rk3328";
  1149. ++
  1150. ++ aliases {
  1151. ++ led-boot = &sys_led;
  1152. ++ led-failsafe = &sys_led;
  1153. ++ led-running = &sys_led;
  1154. ++ led-upgrade = &sys_led;
  1155. ++ };
  1156. ++
  1157. ++ chosen {
  1158. ++ stdout-path = "serial2:1500000n8";
  1159. ++ };
  1160. ++
  1161. ++ gmac_clk: gmac-clock {
  1162. ++ compatible = "fixed-clock";
  1163. ++ clock-frequency = <125000000>;
  1164. ++ clock-output-names = "gmac_clkin";
  1165. ++ #clock-cells = <0>;
  1166. ++ };
  1167. ++
  1168. ++ keys {
  1169. ++ compatible = "gpio-keys";
  1170. ++ pinctrl-0 = <&reset_button_pin>;
  1171. ++ pinctrl-names = "default";
  1172. ++
  1173. ++ reset {
  1174. ++ label = "reset";
  1175. ++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
  1176. ++ linux,code = <KEY_RESTART>;
  1177. ++ debounce-interval = <50>;
  1178. ++ };
  1179. ++ };
  1180. ++
  1181. ++ vcc_rtl8153: vcc-rtl8153-regulator {
  1182. ++ compatible = "regulator-fixed";
  1183. ++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
  1184. ++ pinctrl-names = "default";
  1185. ++ pinctrl-0 = <&rtl8153_en_drv>;
  1186. ++ regulator-always-on;
  1187. ++ regulator-name = "vcc_rtl8153";
  1188. ++ regulator-min-microvolt = <5000000>;
  1189. ++ regulator-max-microvolt = <5000000>;
  1190. ++ enable-active-high;
  1191. ++ };
  1192. ++
  1193. ++ leds {
  1194. ++ compatible = "gpio-leds";
  1195. ++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
  1196. ++ pinctrl-names = "default";
  1197. ++
  1198. ++ lan_led: led-0 {
  1199. ++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
  1200. ++ label = "orangepi-r1plus:green:lan";
  1201. ++ };
  1202. ++
  1203. ++ sys_led: led-1 {
  1204. ++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
  1205. ++ label = "orangepi-r1plus:red:sys";
  1206. ++ };
  1207. ++
  1208. ++ wan_led: led-2 {
  1209. ++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
  1210. ++ label = "orangepi-r1plus:green:wan";
  1211. ++ };
  1212. ++ };
  1213. ++
  1214. ++ vcc_io_sdio: sdmmcio-regulator {
  1215. ++ compatible = "regulator-gpio";
  1216. ++ enable-active-high;
  1217. ++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
  1218. ++ pinctrl-0 = <&sdio_vcc_pin>;
  1219. ++ pinctrl-names = "default";
  1220. ++ regulator-name = "vcc_io_sdio";
  1221. ++ regulator-always-on;
  1222. ++ regulator-min-microvolt = <1800000>;
  1223. ++ regulator-max-microvolt = <3300000>;
  1224. ++ regulator-settling-time-us = <5000>;
  1225. ++ regulator-type = "voltage";
  1226. ++ startup-delay-us = <2000>;
  1227. ++ states = <1800000 0x1
  1228. ++ 3300000 0x0>;
  1229. ++ vin-supply = <&vcc_io_33>;
  1230. ++ };
  1231. ++
  1232. ++ vcc_sd: sdmmc-regulator {
  1233. ++ compatible = "regulator-fixed";
  1234. ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
  1235. ++ pinctrl-0 = <&sdmmc0m1_gpio>;
  1236. ++ pinctrl-names = "default";
  1237. ++ regulator-name = "vcc_sd";
  1238. ++ regulator-boot-on;
  1239. ++ regulator-min-microvolt = <3300000>;
  1240. ++ regulator-max-microvolt = <3300000>;
  1241. ++ vin-supply = <&vcc_io_33>;
  1242. ++ };
  1243. ++
  1244. ++ vdd_5v: vdd-5v {
  1245. ++ compatible = "regulator-fixed";
  1246. ++ regulator-name = "vdd_5v";
  1247. ++ regulator-always-on;
  1248. ++ regulator-boot-on;
  1249. ++ regulator-min-microvolt = <5000000>;
  1250. ++ regulator-max-microvolt = <5000000>;
  1251. ++ };
  1252. ++};
  1253. ++
  1254. ++&cpu0 {
  1255. ++ cpu-supply = <&vdd_arm>;
  1256. ++};
  1257. ++
  1258. ++&cpu1 {
  1259. ++ cpu-supply = <&vdd_arm>;
  1260. ++};
  1261. ++
  1262. ++&cpu2 {
  1263. ++ cpu-supply = <&vdd_arm>;
  1264. ++};
  1265. ++
  1266. ++&cpu3 {
  1267. ++ cpu-supply = <&vdd_arm>;
  1268. ++};
  1269. ++
  1270. ++&gmac2io {
  1271. ++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
  1272. ++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
  1273. ++ clock_in_out = "input";
  1274. ++ phy-handle = <&rtl8211e>;
  1275. ++ phy-mode = "rgmii";
  1276. ++ phy-supply = <&vcc_io_33>;
  1277. ++ pinctrl-0 = <&rgmiim1_pins>;
  1278. ++ pinctrl-names = "default";
  1279. ++ rx_delay = <0x18>;
  1280. ++ snps,aal;
  1281. ++ tx_delay = <0x24>;
  1282. ++ status = "okay";
  1283. ++
  1284. ++ mdio {
  1285. ++ compatible = "snps,dwmac-mdio";
  1286. ++ #address-cells = <1>;
  1287. ++ #size-cells = <0>;
  1288. ++
  1289. ++ rtl8211e: ethernet-phy@1 {
  1290. ++ compatible = "ethernet-phy-id001c.c915",
  1291. ++ "ethernet-phy-ieee802.3-c22";
  1292. ++ reg = <1>;
  1293. ++ pinctrl-0 = <&eth_phy_reset_pin>;
  1294. ++ pinctrl-names = "default";
  1295. ++ reset-assert-us = <10000>;
  1296. ++ reset-deassert-us = <50000>;
  1297. ++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  1298. ++ };
  1299. ++ };
  1300. ++};
  1301. ++
  1302. ++&i2c1 {
  1303. ++ status = "okay";
  1304. ++
  1305. ++ rk805: pmic@18 {
  1306. ++ compatible = "rockchip,rk805";
  1307. ++ reg = <0x18>;
  1308. ++ interrupt-parent = <&gpio1>;
  1309. ++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
  1310. ++ #clock-cells = <1>;
  1311. ++ clock-output-names = "xin32k", "rk805-clkout2";
  1312. ++ gpio-controller;
  1313. ++ #gpio-cells = <2>;
  1314. ++ pinctrl-0 = <&pmic_int_l>;
  1315. ++ pinctrl-names = "default";
  1316. ++ rockchip,system-power-controller;
  1317. ++ wakeup-source;
  1318. ++
  1319. ++ vcc1-supply = <&vdd_5v>;
  1320. ++ vcc2-supply = <&vdd_5v>;
  1321. ++ vcc3-supply = <&vdd_5v>;
  1322. ++ vcc4-supply = <&vdd_5v>;
  1323. ++ vcc5-supply = <&vcc_io_33>;
  1324. ++ vcc6-supply = <&vdd_5v>;
  1325. ++
  1326. ++ regulators {
  1327. ++ vdd_log: DCDC_REG1 {
  1328. ++ regulator-name = "vdd_log";
  1329. ++ regulator-always-on;
  1330. ++ regulator-boot-on;
  1331. ++ regulator-min-microvolt = <712500>;
  1332. ++ regulator-max-microvolt = <1450000>;
  1333. ++ regulator-ramp-delay = <12500>;
  1334. ++
  1335. ++ regulator-state-mem {
  1336. ++ regulator-on-in-suspend;
  1337. ++ regulator-suspend-microvolt = <1000000>;
  1338. ++ };
  1339. ++ };
  1340. ++
  1341. ++ vdd_arm: DCDC_REG2 {
  1342. ++ regulator-name = "vdd_arm";
  1343. ++ regulator-always-on;
  1344. ++ regulator-boot-on;
  1345. ++ regulator-min-microvolt = <712500>;
  1346. ++ regulator-max-microvolt = <1450000>;
  1347. ++ regulator-ramp-delay = <12500>;
  1348. ++
  1349. ++ regulator-state-mem {
  1350. ++ regulator-on-in-suspend;
  1351. ++ regulator-suspend-microvolt = <950000>;
  1352. ++ };
  1353. ++ };
  1354. ++
  1355. ++ vcc_ddr: DCDC_REG3 {
  1356. ++ regulator-name = "vcc_ddr";
  1357. ++ regulator-always-on;
  1358. ++ regulator-boot-on;
  1359. ++
  1360. ++ regulator-state-mem {
  1361. ++ regulator-on-in-suspend;
  1362. ++ };
  1363. ++ };
  1364. ++
  1365. ++ vcc_io_33: DCDC_REG4 {
  1366. ++ regulator-name = "vcc_io_33";
  1367. ++ regulator-always-on;
  1368. ++ regulator-boot-on;
  1369. ++ regulator-min-microvolt = <3300000>;
  1370. ++ regulator-max-microvolt = <3300000>;
  1371. ++
  1372. ++ regulator-state-mem {
  1373. ++ regulator-on-in-suspend;
  1374. ++ regulator-suspend-microvolt = <3300000>;
  1375. ++ };
  1376. ++ };
  1377. ++
  1378. ++ vcc_18: LDO_REG1 {
  1379. ++ regulator-name = "vcc_18";
  1380. ++ regulator-always-on;
  1381. ++ regulator-boot-on;
  1382. ++ regulator-min-microvolt = <1800000>;
  1383. ++ regulator-max-microvolt = <1800000>;
  1384. ++
  1385. ++ regulator-state-mem {
  1386. ++ regulator-on-in-suspend;
  1387. ++ regulator-suspend-microvolt = <1800000>;
  1388. ++ };
  1389. ++ };
  1390. ++
  1391. ++ vcc18_emmc: LDO_REG2 {
  1392. ++ regulator-name = "vcc18_emmc";
  1393. ++ regulator-always-on;
  1394. ++ regulator-boot-on;
  1395. ++ regulator-min-microvolt = <1800000>;
  1396. ++ regulator-max-microvolt = <1800000>;
  1397. ++
  1398. ++ regulator-state-mem {
  1399. ++ regulator-on-in-suspend;
  1400. ++ regulator-suspend-microvolt = <1800000>;
  1401. ++ };
  1402. ++ };
  1403. ++
  1404. ++ vdd_10: LDO_REG3 {
  1405. ++ regulator-name = "vdd_10";
  1406. ++ regulator-always-on;
  1407. ++ regulator-boot-on;
  1408. ++ regulator-min-microvolt = <1000000>;
  1409. ++ regulator-max-microvolt = <1000000>;
  1410. ++
  1411. ++ regulator-state-mem {
  1412. ++ regulator-on-in-suspend;
  1413. ++ regulator-suspend-microvolt = <1000000>;
  1414. ++ };
  1415. ++ };
  1416. ++ };
  1417. ++ };
  1418. ++
  1419. ++ usb {
  1420. ++ rtl8153_en_drv: rtl8153-en-drv {
  1421. ++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  1422. ++ };
  1423. ++ };
  1424. ++};
  1425. ++
  1426. ++&io_domains {
  1427. ++ pmuio-supply = <&vcc_io_33>;
  1428. ++ vccio1-supply = <&vcc_io_33>;
  1429. ++ vccio2-supply = <&vcc18_emmc>;
  1430. ++ vccio3-supply = <&vcc_io_sdio>;
  1431. ++ vccio4-supply = <&vcc_18>;
  1432. ++ vccio5-supply = <&vcc_io_33>;
  1433. ++ vccio6-supply = <&vcc_io_33>;
  1434. ++ status = "okay";
  1435. ++};
  1436. ++
  1437. ++&pinctrl {
  1438. ++ button {
  1439. ++ reset_button_pin: reset-button-pin {
  1440. ++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
  1441. ++ };
  1442. ++ };
  1443. ++
  1444. ++ ethernet-phy {
  1445. ++ eth_phy_reset_pin: eth-phy-reset-pin {
  1446. ++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
  1447. ++ };
  1448. ++ };
  1449. ++
  1450. ++ leds {
  1451. ++ lan_led_pin: lan-led-pin {
  1452. ++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
  1453. ++ };
  1454. ++
  1455. ++ sys_led_pin: sys-led-pin {
  1456. ++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
  1457. ++ };
  1458. ++
  1459. ++ wan_led_pin: wan-led-pin {
  1460. ++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
  1461. ++ };
  1462. ++ };
  1463. ++
  1464. ++ pmic {
  1465. ++ pmic_int_l: pmic-int-l {
  1466. ++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
  1467. ++ };
  1468. ++ };
  1469. ++
  1470. ++ sd {
  1471. ++ sdio_vcc_pin: sdio-vcc-pin {
  1472. ++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
  1473. ++ };
  1474. ++ };
  1475. ++};
  1476. ++
  1477. ++&pwm2 {
  1478. ++ status = "okay";
  1479. ++};
  1480. ++
  1481. ++&sdmmc {
  1482. ++ bus-width = <4>;
  1483. ++ cap-sd-highspeed;
  1484. ++ disable-wp;
  1485. ++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
  1486. ++ pinctrl-names = "default";
  1487. ++ //sd-uhs-sdr12;
  1488. ++ //sd-uhs-sdr25;
  1489. ++ //sd-uhs-sdr50;
  1490. ++ //sd-uhs-sdr104;
  1491. ++ vmmc-supply = <&vcc_sd>;
  1492. ++ vqmmc-supply = <&vcc_io_sdio>;
  1493. ++ status = "okay";
  1494. ++};
  1495. ++
  1496. ++&tsadc {
  1497. ++ rockchip,hw-tshut-mode = <0>;
  1498. ++ rockchip,hw-tshut-polarity = <0>;
  1499. ++ status = "okay";
  1500. ++};
  1501. ++
  1502. ++&u2phy {
  1503. ++ status = "okay";
  1504. ++};
  1505. ++
  1506. ++&u2phy_host {
  1507. ++ status = "okay";
  1508. ++};
  1509. ++
  1510. ++&u2phy_otg {
  1511. ++ status = "okay";
  1512. ++};
  1513. ++
  1514. ++&uart1 {
  1515. ++ status = "okay";
  1516. ++};
  1517. ++
  1518. ++&uart2 {
  1519. ++ status = "okay";
  1520. ++};
  1521. ++
  1522. ++&usb20_otg {
  1523. ++ status = "okay";
  1524. ++ dr_mode = "host";
  1525. ++};
  1526. ++
  1527. ++&usb_host0_ehci {
  1528. ++ status = "okay";
  1529. ++};
  1530. ++
  1531. ++&usb_host0_ohci {
  1532. ++ status = "okay";
  1533. ++};
  1534. ++
  1535. ++&usbdrd3 {
  1536. ++ status = "okay";
  1537. ++};
  1538. ++
  1539. ++&usbdrd_dwc3 {
  1540. ++ dr_mode = "host";
  1541. ++ status = "okay";
  1542. ++
  1543. ++ usb-eth@2 {
  1544. ++ compatible = "realtek,rtl8153";
  1545. ++ reg = <2>;
  1546. ++
  1547. ++ realtek,led-data = <0x87>;
  1548. ++ };
  1549. ++};
  1550.  
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!