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- cmsis_blinky.elf: file format elf32-littlearm
- Disassembly of section .text:
- 080000c4 <__udivsi3-0x14>:
- 80000c4: 080005e8 .word 0x080005e8
- 80000c8: 20000000 .word 0x20000000
- 80000cc: 20000014 .word 0x20000014
- 80000d0: 20000014 .word 0x20000014
- 80000d4: 20000014 .word 0x20000014
- 080000d8 <__udivsi3>:
- 80000d8: e2512001 subs r2, r1, #1
- 80000dc: 012fff1e bxeq lr
- 80000e0: 3a000036 bcc 80001c0 <__udivsi3+0xe8>
- 80000e4: e1500001 cmp r0, r1
- 80000e8: 9a000022 bls 8000178 <__udivsi3+0xa0>
- 80000ec: e1110002 tst r1, r2
- 80000f0: 0a000023 beq 8000184 <__udivsi3+0xac>
- 80000f4: e311020e tst r1, #-536870912 ; 0xe0000000
- 80000f8: 01a01181 lsleq r1, r1, #3
- 80000fc: 03a03008 moveq r3, #8
- 8000100: 13a03001 movne r3, #1
- 8000104: e3510201 cmp r1, #268435456 ; 0x10000000
- 8000108: 31510000 cmpcc r1, r0
- 800010c: 31a01201 lslcc r1, r1, #4
- 8000110: 31a03203 lslcc r3, r3, #4
- 8000114: 3afffffa bcc 8000104 <__udivsi3+0x2c>
- 8000118: e3510102 cmp r1, #-2147483648 ; 0x80000000
- 800011c: 31510000 cmpcc r1, r0
- 8000120: 31a01081 lslcc r1, r1, #1
- 8000124: 31a03083 lslcc r3, r3, #1
- 8000128: 3afffffa bcc 8000118 <__udivsi3+0x40>
- 800012c: e3a02000 mov r2, #0
- 8000130: e1500001 cmp r0, r1
- 8000134: 20400001 subcs r0, r0, r1
- 8000138: 21822003 orrcs r2, r2, r3
- 800013c: e15000a1 cmp r0, r1, lsr #1
- 8000140: 204000a1 subcs r0, r0, r1, lsr #1
- 8000144: 218220a3 orrcs r2, r2, r3, lsr #1
- 8000148: e1500121 cmp r0, r1, lsr #2
- 800014c: 20400121 subcs r0, r0, r1, lsr #2
- 8000150: 21822123 orrcs r2, r2, r3, lsr #2
- 8000154: e15001a1 cmp r0, r1, lsr #3
- 8000158: 204001a1 subcs r0, r0, r1, lsr #3
- 800015c: 218221a3 orrcs r2, r2, r3, lsr #3
- 8000160: e3500000 cmp r0, #0
- 8000164: 11b03223 lsrsne r3, r3, #4
- 8000168: 11a01221 lsrne r1, r1, #4
- 800016c: 1affffef bne 8000130 <__udivsi3+0x58>
- 8000170: e1a00002 mov r0, r2
- 8000174: e12fff1e bx lr
- 8000178: 03a00001 moveq r0, #1
- 800017c: 13a00000 movne r0, #0
- 8000180: e12fff1e bx lr
- 8000184: e3510801 cmp r1, #65536 ; 0x10000
- 8000188: 21a01821 lsrcs r1, r1, #16
- 800018c: 23a02010 movcs r2, #16
- 8000190: 33a02000 movcc r2, #0
- 8000194: e3510c01 cmp r1, #256 ; 0x100
- 8000198: 21a01421 lsrcs r1, r1, #8
- 800019c: 22822008 addcs r2, r2, #8
- 80001a0: e3510010 cmp r1, #16
- 80001a4: 21a01221 lsrcs r1, r1, #4
- 80001a8: 22822004 addcs r2, r2, #4
- 80001ac: e3510004 cmp r1, #4
- 80001b0: 82822003 addhi r2, r2, #3
- 80001b4: 908220a1 addls r2, r2, r1, lsr #1
- 80001b8: e1a00230 lsr r0, r0, r2
- 80001bc: e12fff1e bx lr
- 80001c0: e3500000 cmp r0, #0
- 80001c4: 13e00000 mvnne r0, #0
- 80001c8: ea000059 b 8000334 <__aeabi_idiv0>
- 080001cc <__aeabi_uidivmod>:
- 80001cc: e3510000 cmp r1, #0
- 80001d0: 0afffffa beq 80001c0 <__udivsi3+0xe8>
- 80001d4: e92d4003 push {r0, r1, lr}
- 80001d8: ebffffbe bl 80000d8 <__udivsi3>
- 80001dc: e8bd4006 pop {r1, r2, lr}
- 80001e0: e0030092 mul r3, r2, r0
- 80001e4: e0411003 sub r1, r1, r3
- 80001e8: e12fff1e bx lr
- 080001ec <__divsi3>:
- 80001ec: e3510000 cmp r1, #0
- 80001f0: 0a000043 beq 8000304 <.divsi3_skip_div0_test+0x110>
- 080001f4 <.divsi3_skip_div0_test>:
- 80001f4: e020c001 eor ip, r0, r1
- 80001f8: 42611000 rsbmi r1, r1, #0
- 80001fc: e2512001 subs r2, r1, #1
- 8000200: 0a000027 beq 80002a4 <.divsi3_skip_div0_test+0xb0>
- 8000204: e1b03000 movs r3, r0
- 8000208: 42603000 rsbmi r3, r0, #0
- 800020c: e1530001 cmp r3, r1
- 8000210: 9a000026 bls 80002b0 <.divsi3_skip_div0_test+0xbc>
- 8000214: e1110002 tst r1, r2
- 8000218: 0a000028 beq 80002c0 <.divsi3_skip_div0_test+0xcc>
- 800021c: e311020e tst r1, #-536870912 ; 0xe0000000
- 8000220: 01a01181 lsleq r1, r1, #3
- 8000224: 03a02008 moveq r2, #8
- 8000228: 13a02001 movne r2, #1
- 800022c: e3510201 cmp r1, #268435456 ; 0x10000000
- 8000230: 31510003 cmpcc r1, r3
- 8000234: 31a01201 lslcc r1, r1, #4
- 8000238: 31a02202 lslcc r2, r2, #4
- 800023c: 3afffffa bcc 800022c <.divsi3_skip_div0_test+0x38>
- 8000240: e3510102 cmp r1, #-2147483648 ; 0x80000000
- 8000244: 31510003 cmpcc r1, r3
- 8000248: 31a01081 lslcc r1, r1, #1
- 800024c: 31a02082 lslcc r2, r2, #1
- 8000250: 3afffffa bcc 8000240 <.divsi3_skip_div0_test+0x4c>
- 8000254: e3a00000 mov r0, #0
- 8000258: e1530001 cmp r3, r1
- 800025c: 20433001 subcs r3, r3, r1
- 8000260: 21800002 orrcs r0, r0, r2
- 8000264: e15300a1 cmp r3, r1, lsr #1
- 8000268: 204330a1 subcs r3, r3, r1, lsr #1
- 800026c: 218000a2 orrcs r0, r0, r2, lsr #1
- 8000270: e1530121 cmp r3, r1, lsr #2
- 8000274: 20433121 subcs r3, r3, r1, lsr #2
- 8000278: 21800122 orrcs r0, r0, r2, lsr #2
- 800027c: e15301a1 cmp r3, r1, lsr #3
- 8000280: 204331a1 subcs r3, r3, r1, lsr #3
- 8000284: 218001a2 orrcs r0, r0, r2, lsr #3
- 8000288: e3530000 cmp r3, #0
- 800028c: 11b02222 lsrsne r2, r2, #4
- 8000290: 11a01221 lsrne r1, r1, #4
- 8000294: 1affffef bne 8000258 <.divsi3_skip_div0_test+0x64>
- 8000298: e35c0000 cmp ip, #0
- 800029c: 42600000 rsbmi r0, r0, #0
- 80002a0: e12fff1e bx lr
- 80002a4: e13c0000 teq ip, r0
- 80002a8: 42600000 rsbmi r0, r0, #0
- 80002ac: e12fff1e bx lr
- 80002b0: 33a00000 movcc r0, #0
- 80002b4: 01a00fcc asreq r0, ip, #31
- 80002b8: 03800001 orreq r0, r0, #1
- 80002bc: e12fff1e bx lr
- 80002c0: e3510801 cmp r1, #65536 ; 0x10000
- 80002c4: 21a01821 lsrcs r1, r1, #16
- 80002c8: 23a02010 movcs r2, #16
- 80002cc: 33a02000 movcc r2, #0
- 80002d0: e3510c01 cmp r1, #256 ; 0x100
- 80002d4: 21a01421 lsrcs r1, r1, #8
- 80002d8: 22822008 addcs r2, r2, #8
- 80002dc: e3510010 cmp r1, #16
- 80002e0: 21a01221 lsrcs r1, r1, #4
- 80002e4: 22822004 addcs r2, r2, #4
- 80002e8: e3510004 cmp r1, #4
- 80002ec: 82822003 addhi r2, r2, #3
- 80002f0: 908220a1 addls r2, r2, r1, lsr #1
- 80002f4: e35c0000 cmp ip, #0
- 80002f8: e1a00233 lsr r0, r3, r2
- 80002fc: 42600000 rsbmi r0, r0, #0
- 8000300: e12fff1e bx lr
- 8000304: e3500000 cmp r0, #0
- 8000308: c3e00102 mvngt r0, #-2147483648 ; 0x80000000
- 800030c: b3a00102 movlt r0, #-2147483648 ; 0x80000000
- 8000310: ea000007 b 8000334 <__aeabi_idiv0>
- 08000314 <__aeabi_idivmod>:
- 8000314: e3510000 cmp r1, #0
- 8000318: 0afffff9 beq 8000304 <.divsi3_skip_div0_test+0x110>
- 800031c: e92d4003 push {r0, r1, lr}
- 8000320: ebffffb3 bl 80001f4 <.divsi3_skip_div0_test>
- 8000324: e8bd4006 pop {r1, r2, lr}
- 8000328: e0030092 mul r3, r2, r0
- 800032c: e0411003 sub r1, r1, r3
- 8000330: e12fff1e bx lr
- 08000334 <__aeabi_idiv0>:
- 8000334: e12fff1e bx lr
- 08000338 <main>:
- // return 1;
- // }
- // return ticks;
- //}
- int main(void) {
- 8000338: b580 push {r7, lr}
- 800033a: b082 sub sp, #8
- 800033c: af00 add r7, sp, #0
- int x = 100;
- 800033e: 2364 movs r3, #100 ; 0x64
- 8000340: 607b str r3, [r7, #4]
- int y = x / 10;
- 8000342: 687b ldr r3, [r7, #4]
- 8000344: 210a movs r1, #10
- 8000346: 0018 movs r0, r3
- 8000348: f7ff ff50 bl 80001ec <__divsi3>
- 800034c: 0003 movs r3, r0
- 800034e: 603b str r3, [r7, #0]
- //int x = SystemCoreClock / 10;
- //int x = 8000000 / 10;
- //setup_gpio();
- //setup_systick(x);
- while (1) {
- 8000350: e7fe b.n 8000350 <main+0x18>
- ...
- 08000354 <SystemInit>:
- * SystemCoreClock variable.
- * @param None
- * @retval None
- */
- void SystemInit (void)
- {
- 8000354: b580 push {r7, lr}
- 8000356: af00 add r7, sp, #0
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
- 8000358: 4b1b ldr r3, [pc, #108] ; (80003c8 <SystemInit+0x74>)
- 800035a: 681a ldr r2, [r3, #0]
- 800035c: 4b1a ldr r3, [pc, #104] ; (80003c8 <SystemInit+0x74>)
- 800035e: 2101 movs r1, #1
- 8000360: 430a orrs r2, r1
- 8000362: 601a str r2, [r3, #0]
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
- 8000364: 4b18 ldr r3, [pc, #96] ; (80003c8 <SystemInit+0x74>)
- 8000366: 685a ldr r2, [r3, #4]
- 8000368: 4b17 ldr r3, [pc, #92] ; (80003c8 <SystemInit+0x74>)
- 800036a: 4918 ldr r1, [pc, #96] ; (80003cc <SystemInit+0x78>)
- 800036c: 400a ands r2, r1
- 800036e: 605a str r2, [r3, #4]
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
- 8000370: 4b15 ldr r3, [pc, #84] ; (80003c8 <SystemInit+0x74>)
- 8000372: 681a ldr r2, [r3, #0]
- 8000374: 4b14 ldr r3, [pc, #80] ; (80003c8 <SystemInit+0x74>)
- 8000376: 4916 ldr r1, [pc, #88] ; (80003d0 <SystemInit+0x7c>)
- 8000378: 400a ands r2, r1
- 800037a: 601a str r2, [r3, #0]
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
- 800037c: 4b12 ldr r3, [pc, #72] ; (80003c8 <SystemInit+0x74>)
- 800037e: 681a ldr r2, [r3, #0]
- 8000380: 4b11 ldr r3, [pc, #68] ; (80003c8 <SystemInit+0x74>)
- 8000382: 4914 ldr r1, [pc, #80] ; (80003d4 <SystemInit+0x80>)
- 8000384: 400a ands r2, r1
- 8000386: 601a str r2, [r3, #0]
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
- 8000388: 4b0f ldr r3, [pc, #60] ; (80003c8 <SystemInit+0x74>)
- 800038a: 685a ldr r2, [r3, #4]
- 800038c: 4b0e ldr r3, [pc, #56] ; (80003c8 <SystemInit+0x74>)
- 800038e: 4912 ldr r1, [pc, #72] ; (80003d8 <SystemInit+0x84>)
- 8000390: 400a ands r2, r1
- 8000392: 605a str r2, [r3, #4]
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
- 8000394: 4b0c ldr r3, [pc, #48] ; (80003c8 <SystemInit+0x74>)
- 8000396: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000398: 4b0b ldr r3, [pc, #44] ; (80003c8 <SystemInit+0x74>)
- 800039a: 210f movs r1, #15
- 800039c: 438a bics r2, r1
- 800039e: 62da str r2, [r3, #44] ; 0x2c
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
- 80003a0: 4b09 ldr r3, [pc, #36] ; (80003c8 <SystemInit+0x74>)
- 80003a2: 6b1a ldr r2, [r3, #48] ; 0x30
- 80003a4: 4b08 ldr r3, [pc, #32] ; (80003c8 <SystemInit+0x74>)
- 80003a6: 490d ldr r1, [pc, #52] ; (80003dc <SystemInit+0x88>)
- 80003a8: 400a ands r2, r1
- 80003aa: 631a str r2, [r3, #48] ; 0x30
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
- 80003ac: 4b06 ldr r3, [pc, #24] ; (80003c8 <SystemInit+0x74>)
- 80003ae: 6b5a ldr r2, [r3, #52] ; 0x34
- 80003b0: 4b05 ldr r3, [pc, #20] ; (80003c8 <SystemInit+0x74>)
- 80003b2: 2101 movs r1, #1
- 80003b4: 438a bics r2, r1
- 80003b6: 635a str r2, [r3, #52] ; 0x34
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
- 80003b8: 4b03 ldr r3, [pc, #12] ; (80003c8 <SystemInit+0x74>)
- 80003ba: 2200 movs r2, #0
- 80003bc: 609a str r2, [r3, #8]
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
- SetSysClock();
- 80003be: f000 f87f bl 80004c0 <SetSysClock>
- }
- 80003c2: 46c0 nop ; (mov r8, r8)
- 80003c4: 46bd mov sp, r7
- 80003c6: bd80 pop {r7, pc}
- 80003c8: 40021000 .word 0x40021000
- 80003cc: f8ffb80c .word 0xf8ffb80c
- 80003d0: fef6ffff .word 0xfef6ffff
- 80003d4: fffbffff .word 0xfffbffff
- 80003d8: ffc0ffff .word 0xffc0ffff
- 80003dc: fffffeac .word 0xfffffeac
- 080003e0 <SystemCoreClockUpdate>:
- * value for HSE crystal.
- * @param None
- * @retval None
- */
- void SystemCoreClockUpdate (void)
- {
- 80003e0: b580 push {r7, lr}
- 80003e2: b084 sub sp, #16
- 80003e4: af00 add r7, sp, #0
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
- 80003e6: 2300 movs r3, #0
- 80003e8: 60fb str r3, [r7, #12]
- 80003ea: 2300 movs r3, #0
- 80003ec: 60bb str r3, [r7, #8]
- 80003ee: 2300 movs r3, #0
- 80003f0: 607b str r3, [r7, #4]
- 80003f2: 2300 movs r3, #0
- 80003f4: 603b str r3, [r7, #0]
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
- 80003f6: 4b2e ldr r3, [pc, #184] ; (80004b0 <SystemCoreClockUpdate+0xd0>)
- 80003f8: 685b ldr r3, [r3, #4]
- 80003fa: 220c movs r2, #12
- 80003fc: 4013 ands r3, r2
- 80003fe: 60fb str r3, [r7, #12]
- switch (tmp)
- 8000400: 68fb ldr r3, [r7, #12]
- 8000402: 2b04 cmp r3, #4
- 8000404: d007 beq.n 8000416 <SystemCoreClockUpdate+0x36>
- 8000406: 2b08 cmp r3, #8
- 8000408: d009 beq.n 800041e <SystemCoreClockUpdate+0x3e>
- 800040a: 2b00 cmp r3, #0
- 800040c: d138 bne.n 8000480 <SystemCoreClockUpdate+0xa0>
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- 800040e: 4b29 ldr r3, [pc, #164] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 8000410: 4a29 ldr r2, [pc, #164] ; (80004b8 <SystemCoreClockUpdate+0xd8>)
- 8000412: 601a str r2, [r3, #0]
- break;
- 8000414: e038 b.n 8000488 <SystemCoreClockUpdate+0xa8>
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- 8000416: 4b27 ldr r3, [pc, #156] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 8000418: 4a27 ldr r2, [pc, #156] ; (80004b8 <SystemCoreClockUpdate+0xd8>)
- 800041a: 601a str r2, [r3, #0]
- break;
- 800041c: e034 b.n 8000488 <SystemCoreClockUpdate+0xa8>
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- 800041e: 4b24 ldr r3, [pc, #144] ; (80004b0 <SystemCoreClockUpdate+0xd0>)
- 8000420: 685a ldr r2, [r3, #4]
- 8000422: 23f0 movs r3, #240 ; 0xf0
- 8000424: 039b lsls r3, r3, #14
- 8000426: 4013 ands r3, r2
- 8000428: 60bb str r3, [r7, #8]
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- 800042a: 4b21 ldr r3, [pc, #132] ; (80004b0 <SystemCoreClockUpdate+0xd0>)
- 800042c: 685a ldr r2, [r3, #4]
- 800042e: 23c0 movs r3, #192 ; 0xc0
- 8000430: 025b lsls r3, r3, #9
- 8000432: 4013 ands r3, r2
- 8000434: 607b str r3, [r7, #4]
- pllmull = ( pllmull >> 18) + 2;
- 8000436: 68bb ldr r3, [r7, #8]
- 8000438: 0c9b lsrs r3, r3, #18
- 800043a: 3302 adds r3, #2
- 800043c: 60bb str r3, [r7, #8]
- if (pllsource == 0x00)
- 800043e: 687b ldr r3, [r7, #4]
- 8000440: 2b00 cmp r3, #0
- 8000442: d10c bne.n 800045e <SystemCoreClockUpdate+0x7e>
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- 8000444: 68b9 ldr r1, [r7, #8]
- 8000446: 000a movs r2, r1
- 8000448: 0152 lsls r2, r2, #5
- 800044a: 1a52 subs r2, r2, r1
- 800044c: 0193 lsls r3, r2, #6
- 800044e: 1a9b subs r3, r3, r2
- 8000450: 00db lsls r3, r3, #3
- 8000452: 185b adds r3, r3, r1
- 8000454: 021b lsls r3, r3, #8
- 8000456: 001a movs r2, r3
- 8000458: 4b16 ldr r3, [pc, #88] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 800045a: 601a str r2, [r3, #0]
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- break;
- 800045c: e014 b.n 8000488 <SystemCoreClockUpdate+0xa8>
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- 800045e: 4b14 ldr r3, [pc, #80] ; (80004b0 <SystemCoreClockUpdate+0xd0>)
- 8000460: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000462: 220f movs r2, #15
- 8000464: 4013 ands r3, r2
- 8000466: 3301 adds r3, #1
- 8000468: 603b str r3, [r7, #0]
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- 800046a: 6839 ldr r1, [r7, #0]
- 800046c: 4812 ldr r0, [pc, #72] ; (80004b8 <SystemCoreClockUpdate+0xd8>)
- 800046e: f7ff fe33 bl 80000d8 <__udivsi3>
- 8000472: 0003 movs r3, r0
- 8000474: 001a movs r2, r3
- 8000476: 68bb ldr r3, [r7, #8]
- 8000478: 435a muls r2, r3
- 800047a: 4b0e ldr r3, [pc, #56] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 800047c: 601a str r2, [r3, #0]
- break;
- 800047e: e003 b.n 8000488 <SystemCoreClockUpdate+0xa8>
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- 8000480: 4b0c ldr r3, [pc, #48] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 8000482: 4a0d ldr r2, [pc, #52] ; (80004b8 <SystemCoreClockUpdate+0xd8>)
- 8000484: 601a str r2, [r3, #0]
- break;
- 8000486: 46c0 nop ; (mov r8, r8)
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- 8000488: 4b09 ldr r3, [pc, #36] ; (80004b0 <SystemCoreClockUpdate+0xd0>)
- 800048a: 685b ldr r3, [r3, #4]
- 800048c: 091b lsrs r3, r3, #4
- 800048e: 220f movs r2, #15
- 8000490: 4013 ands r3, r2
- 8000492: 4a0a ldr r2, [pc, #40] ; (80004bc <SystemCoreClockUpdate+0xdc>)
- 8000494: 5cd3 ldrb r3, [r2, r3]
- 8000496: b2db uxtb r3, r3
- 8000498: 60fb str r3, [r7, #12]
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
- 800049a: 4b06 ldr r3, [pc, #24] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 800049c: 681a ldr r2, [r3, #0]
- 800049e: 68fb ldr r3, [r7, #12]
- 80004a0: 40da lsrs r2, r3
- 80004a2: 4b04 ldr r3, [pc, #16] ; (80004b4 <SystemCoreClockUpdate+0xd4>)
- 80004a4: 601a str r2, [r3, #0]
- }
- 80004a6: 46c0 nop ; (mov r8, r8)
- 80004a8: 46bd mov sp, r7
- 80004aa: b004 add sp, #16
- 80004ac: bd80 pop {r7, pc}
- 80004ae: 46c0 nop ; (mov r8, r8)
- 80004b0: 40021000 .word 0x40021000
- 80004b4: 20000000 .word 0x20000000
- 80004b8: 007a1200 .word 0x007a1200
- 80004bc: 20000004 .word 0x20000004
- 080004c0 <SetSysClock>:
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
- static void SetSysClock(void)
- {
- 80004c0: b580 push {r7, lr}
- 80004c2: b082 sub sp, #8
- 80004c4: af00 add r7, sp, #0
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
- 80004c6: 2300 movs r3, #0
- 80004c8: 607b str r3, [r7, #4]
- 80004ca: 2300 movs r3, #0
- 80004cc: 603b str r3, [r7, #0]
- /* HSE used as System clock source */
- /******************************************************************************/
- /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
- 80004ce: 4b24 ldr r3, [pc, #144] ; (8000560 <SetSysClock+0xa0>)
- 80004d0: 681a ldr r2, [r3, #0]
- 80004d2: 4b23 ldr r3, [pc, #140] ; (8000560 <SetSysClock+0xa0>)
- 80004d4: 2180 movs r1, #128 ; 0x80
- 80004d6: 0249 lsls r1, r1, #9
- 80004d8: 430a orrs r2, r1
- 80004da: 601a str r2, [r3, #0]
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- 80004dc: 4b20 ldr r3, [pc, #128] ; (8000560 <SetSysClock+0xa0>)
- 80004de: 681a ldr r2, [r3, #0]
- 80004e0: 2380 movs r3, #128 ; 0x80
- 80004e2: 029b lsls r3, r3, #10
- 80004e4: 4013 ands r3, r2
- 80004e6: 603b str r3, [r7, #0]
- StartUpCounter++;
- 80004e8: 687b ldr r3, [r7, #4]
- 80004ea: 3301 adds r3, #1
- 80004ec: 607b str r3, [r7, #4]
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
- 80004ee: 683b ldr r3, [r7, #0]
- 80004f0: 2b00 cmp r3, #0
- 80004f2: d104 bne.n 80004fe <SetSysClock+0x3e>
- 80004f4: 687a ldr r2, [r7, #4]
- 80004f6: 23a0 movs r3, #160 ; 0xa0
- 80004f8: 01db lsls r3, r3, #7
- 80004fa: 429a cmp r2, r3
- 80004fc: d1ee bne.n 80004dc <SetSysClock+0x1c>
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- 80004fe: 4b18 ldr r3, [pc, #96] ; (8000560 <SetSysClock+0xa0>)
- 8000500: 681a ldr r2, [r3, #0]
- 8000502: 2380 movs r3, #128 ; 0x80
- 8000504: 029b lsls r3, r3, #10
- 8000506: 4013 ands r3, r2
- 8000508: d002 beq.n 8000510 <SetSysClock+0x50>
- {
- HSEStatus = (uint32_t)0x01;
- 800050a: 2301 movs r3, #1
- 800050c: 603b str r3, [r7, #0]
- 800050e: e001 b.n 8000514 <SetSysClock+0x54>
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- 8000510: 2300 movs r3, #0
- 8000512: 603b str r3, [r7, #0]
- }
- if (HSEStatus == (uint32_t)0x01)
- 8000514: 683b ldr r3, [r7, #0]
- 8000516: 2b01 cmp r3, #1
- 8000518: d11d bne.n 8000556 <SetSysClock+0x96>
- {
- /* Enable Prefetch Buffer and Flash 0 wait state */
- FLASH->ACR = FLASH_ACR_PRFTBE;
- 800051a: 4b12 ldr r3, [pc, #72] ; (8000564 <SetSysClock+0xa4>)
- 800051c: 2210 movs r2, #16
- 800051e: 601a str r2, [r3, #0]
- /* HCLK = SYSCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
- 8000520: 4a0f ldr r2, [pc, #60] ; (8000560 <SetSysClock+0xa0>)
- 8000522: 4b0f ldr r3, [pc, #60] ; (8000560 <SetSysClock+0xa0>)
- 8000524: 6852 ldr r2, [r2, #4]
- 8000526: 605a str r2, [r3, #4]
- /* PCLK = HCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
- 8000528: 4a0d ldr r2, [pc, #52] ; (8000560 <SetSysClock+0xa0>)
- 800052a: 4b0d ldr r3, [pc, #52] ; (8000560 <SetSysClock+0xa0>)
- 800052c: 6852 ldr r2, [r2, #4]
- 800052e: 605a str r2, [r3, #4]
- /* Select HSE as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- 8000530: 4b0b ldr r3, [pc, #44] ; (8000560 <SetSysClock+0xa0>)
- 8000532: 685a ldr r2, [r3, #4]
- 8000534: 4b0a ldr r3, [pc, #40] ; (8000560 <SetSysClock+0xa0>)
- 8000536: 2103 movs r1, #3
- 8000538: 438a bics r2, r1
- 800053a: 605a str r2, [r3, #4]
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
- 800053c: 4b08 ldr r3, [pc, #32] ; (8000560 <SetSysClock+0xa0>)
- 800053e: 685a ldr r2, [r3, #4]
- 8000540: 4b07 ldr r3, [pc, #28] ; (8000560 <SetSysClock+0xa0>)
- 8000542: 2101 movs r1, #1
- 8000544: 430a orrs r2, r1
- 8000546: 605a str r2, [r3, #4]
- /* Wait till HSE is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSE)
- 8000548: 46c0 nop ; (mov r8, r8)
- 800054a: 4b05 ldr r3, [pc, #20] ; (8000560 <SetSysClock+0xa0>)
- 800054c: 685b ldr r3, [r3, #4]
- 800054e: 220c movs r2, #12
- 8000550: 4013 ands r3, r2
- 8000552: 2b04 cmp r3, #4
- 8000554: d1f9 bne.n 800054a <SetSysClock+0x8a>
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
- }
- 8000556: 46c0 nop ; (mov r8, r8)
- 8000558: 46bd mov sp, r7
- 800055a: b002 add sp, #8
- 800055c: bd80 pop {r7, pc}
- 800055e: 46c0 nop ; (mov r8, r8)
- 8000560: 40021000 .word 0x40021000
- 8000564: 40022000 .word 0x40022000
- 08000568 <Reset_Handler>:
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
- Reset_Handler:
- ldr r0, =_estack
- 8000568: 4812 ldr r0, [pc, #72] ; (80005b4 <LoopForever+0x2>)
- mov sp, r0 /* set stack pointer */
- 800056a: 4685 mov sp, r0
- /*Check if boot space corresponds to test memory*/
- LDR R0,=0x00000004
- 800056c: 4812 ldr r0, [pc, #72] ; (80005b8 <LoopForever+0x6>)
- LDR R1, [R0]
- 800056e: 6801 ldr r1, [r0, #0]
- LSRS R1, R1, #24
- 8000570: 0e09 lsrs r1, r1, #24
- LDR R2,=0x1F
- 8000572: 4a12 ldr r2, [pc, #72] ; (80005bc <LoopForever+0xa>)
- CMP R1, R2
- 8000574: 4291 cmp r1, r2
- BNE ApplicationStart
- 8000576: d105 bne.n 8000584 <ApplicationStart>
- /*SYSCFG clock enable*/
- LDR R0,=0x40021018
- 8000578: 4811 ldr r0, [pc, #68] ; (80005c0 <LoopForever+0xe>)
- LDR R1,=0x00000001
- 800057a: 4912 ldr r1, [pc, #72] ; (80005c4 <LoopForever+0x12>)
- STR R1, [R0]
- 800057c: 6001 str r1, [r0, #0]
- /*Set CFGR1 register with flash memory remap at address 0*/
- LDR R0,=0x40010000
- 800057e: 4812 ldr r0, [pc, #72] ; (80005c8 <LoopForever+0x16>)
- LDR R1,=0x00000000
- 8000580: 4912 ldr r1, [pc, #72] ; (80005cc <LoopForever+0x1a>)
- STR R1, [R0]
- 8000582: 6001 str r1, [r0, #0]
- 08000584 <ApplicationStart>:
- ApplicationStart:
- /* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- 8000584: 2100 movs r1, #0
- b LoopCopyDataInit
- 8000586: e003 b.n 8000590 <LoopCopyDataInit>
- 08000588 <CopyDataInit>:
- CopyDataInit:
- ldr r3, =_sidata
- 8000588: 4b11 ldr r3, [pc, #68] ; (80005d0 <LoopForever+0x1e>)
- ldr r3, [r3, r1]
- 800058a: 585b ldr r3, [r3, r1]
- str r3, [r0, r1]
- 800058c: 5043 str r3, [r0, r1]
- adds r1, r1, #4
- 800058e: 3104 adds r1, #4
- 08000590 <LoopCopyDataInit>:
- LoopCopyDataInit:
- ldr r0, =_sdata
- 8000590: 4810 ldr r0, [pc, #64] ; (80005d4 <LoopForever+0x22>)
- ldr r3, =_edata
- 8000592: 4b11 ldr r3, [pc, #68] ; (80005d8 <LoopForever+0x26>)
- adds r2, r0, r1
- 8000594: 1842 adds r2, r0, r1
- cmp r2, r3
- 8000596: 429a cmp r2, r3
- bcc CopyDataInit
- 8000598: d3f6 bcc.n 8000588 <CopyDataInit>
- ldr r2, =_sbss
- 800059a: 4a10 ldr r2, [pc, #64] ; (80005dc <LoopForever+0x2a>)
- b LoopFillZerobss
- 800059c: e002 b.n 80005a4 <LoopFillZerobss>
- 0800059e <FillZerobss>:
- /* Zero fill the bss segment. */
- FillZerobss:
- movs r3, #0
- 800059e: 2300 movs r3, #0
- str r3, [r2]
- 80005a0: 6013 str r3, [r2, #0]
- adds r2, r2, #4
- 80005a2: 3204 adds r2, #4
- 080005a4 <LoopFillZerobss>:
- LoopFillZerobss:
- ldr r3, = _ebss
- 80005a4: 4b0e ldr r3, [pc, #56] ; (80005e0 <LoopForever+0x2e>)
- cmp r2, r3
- 80005a6: 429a cmp r2, r3
- bcc FillZerobss
- 80005a8: d3f9 bcc.n 800059e <FillZerobss>
- /* Call the clock system intitialization function.*/
- bl SystemInit
- 80005aa: f7ff fed3 bl 8000354 <SystemInit>
- /* Call the application's entry point.*/
- bl main
- 80005ae: f7ff fec3 bl 8000338 <main>
- 080005b2 <LoopForever>:
- LoopForever:
- b LoopForever
- 80005b2: e7fe b.n 80005b2 <LoopForever>
- ldr r0, =_estack
- 80005b4: 20001000 .word 0x20001000
- LDR R0,=0x00000004
- 80005b8: 00000004 .word 0x00000004
- LDR R2,=0x1F
- 80005bc: 0000001f .word 0x0000001f
- LDR R0,=0x40021018
- 80005c0: 40021018 .word 0x40021018
- LDR R1,=0x00000001
- 80005c4: 00000001 .word 0x00000001
- LDR R0,=0x40010000
- 80005c8: 40010000 .word 0x40010000
- LDR R1,=0x00000000
- 80005cc: 00000000 .word 0x00000000
- ldr r3, =_sidata
- 80005d0: 080005e8 .word 0x080005e8
- ldr r0, =_sdata
- 80005d4: 20000000 .word 0x20000000
- ldr r3, =_edata
- 80005d8: 20000014 .word 0x20000014
- ldr r2, =_sbss
- 80005dc: 20000014 .word 0x20000014
- ldr r3, = _ebss
- 80005e0: 20000014 .word 0x20000014
- 080005e4 <ADC1_IRQHandler>:
- * @retval : None
- */
- .section .text.Default_Handler,"ax",%progbits
- Default_Handler:
- Infinite_Loop:
- b Infinite_Loop
- 80005e4: e7fe b.n 80005e4 <ADC1_IRQHandler>
- Disassembly of section .data:
- 20000000 <SystemCoreClock>:
- 20000000: 1200 007a ..z.
- 20000004 <AHBPrescTable>:
- ...
- 2000000c: 0201 0403 0706 0908 ........
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