`timescale 1ns/100ps

module ads1018 (
                input  reset,
                input  clk_i,
                output reg sclk_adc,
                output reg cs,
                input  din, //принимаем результат
                output reg dout, //отправляем вопрос к каналам
                output reg [11:0]o_ch1,
                output reg [11:0]o_ch2,
                output reg [11:0]o_ch3,
                output reg [11:0]o_ch4,
                input ena_i
               );
parameter SYSCLK_PERIOD = 40.690104; // 24,576MHz
//defparam    sclk_sours1.freq_const = sclk_presc;  // 24,576/4/2 = 3,072 MHz
parameter   sclk_presc = 10;

reg [8:0] counter; // reg to enter 32- or 16-bit transmission cycle
// operating way
// cs high 5*40.69 ns
parameter csHigh = 5;
//sclk low 3*40.69 ns
parameter sclkLow = 3;
//sclk high 4*40.69 ns
parameter sclkPer = 8*16-4; // 16 периодов по восемь тактов/ не учитывается последний низкий sclk
//sclk low 4*40.69 ns
//sclk low 3*40.69 ns
//repeat
reg [2:0] dur_sclk;

reg [15:0] transdata = 0;
wire [15:0] transtmp  = {transdata[14:0], din};

//wires for cofig regs
//////////////////////////////////////////////////////////////////

reg [15:0]dataInCh[3:0];
reg  [1:0]ch_cnt;

parameter dataOutCh =
{
// ss mux pga m dr ts p op r
16'b1_100_010_0_100_0_0_01_1,
16'b1_101_010_0_100_0_0_01_1,
16'b1_110_010_0_100_0_0_01_1,
16'b1_111_010_0_100_0_0_01_1

};
reg start = 0;
reg [15:0] shiftOut [3:0];


    reg    main_reg;
    wire    pos_sclk, neg_sclk;
    assign  pos_sclk = sclk_adc & ~main_reg;
    assign  neg_sclk = ~sclk_adc & main_reg;
    integer i;

initial begin
    cs = 1'b1;
    for (i = 0; i < 4; i=i+1) shiftOut[i] = dataOutCh[((3-i)*16)+:16];
    counter <= 0;
    ch_cnt = 0;
    sclk_adc = 0;
    dur_sclk = 0;
    dout = 0;
    o_ch1 = 0; o_ch2 = 0; o_ch3 = 0; o_ch4 = 0;
    dataInCh[0][15:0] = 0;
    dataInCh[1][15:0] = 0;
    dataInCh[2][15:0] = 0;
    dataInCh[3][15:0] = 0;
end


//switch control
always @(posedge clk_i or posedge reset)
begin
if (reset)
    begin
        main_reg <= sclk_adc;
        cs <= 1;
        dout <= 0;
        counter <= 0;
        o_ch1 <= 0; o_ch2 <= 0; o_ch3 <= 0; o_ch4 <= 0;
    end
else if (ena_i) start <= 1'b1;

if (start)

    begin
        counter <= counter + 1'b1;
        if (counter == csHigh + 1) cs <= 0;
        if ((counter > (csHigh + sclkLow)) && (counter < (csHigh + sclkLow + sclkPer)))
            begin
                dur_sclk <= dur_sclk -1;
                sclk_adc <= dur_sclk[2];
                main_reg <= sclk_adc;

                if (pos_sclk)
                    begin
                        dout <= shiftOut [ch_cnt] [15];
                        shiftOut [ch_cnt][15:0] <= { shiftOut[ch_cnt] [14:0], 1'b0};
                    end
                if (neg_sclk)
                    begin
                        transdata <= transtmp;
                        dataInCh[ch_cnt][15:0] <= transdata;
                    end
            end
        if (counter > csHigh + sclkLow + sclkPer)
        begin
            dur_sclk <= 0;
            sclk_adc <= 0;
            if (ch_cnt == 0) o_ch1 <= dataInCh[3][15:4];
            if (ch_cnt == 1) o_ch2 <= dataInCh[0][15:4];
            if (ch_cnt == 2) o_ch3 <= dataInCh[1][15:4];
            if (ch_cnt == 3) o_ch4 <= dataInCh[2][15:4];
            end
        if (counter > csHigh + sclkLow + sclkPer + sclkLow)
        begin
            cs <= 1;
            counter <= 0;
            start <= 0;
            for (i = 0; i < 4; i=i+1) shiftOut[i] = dataOutCh[((3-i)*16)+:16];
            transdata <= 0;
            ch_cnt <= ch_cnt + 1;
            dout <= 0;
        end
    end

end
/*
//записываем ответ по спаду
always @(negedge sclk_adc)
begin
    transdata = transtmp;
    dataInCh[ch_cnt][15:0] = transdata;
end
//запрос  отсылаем по восходящему
always @(posedge sclk_adc)
begin
    dout = shiftOut [ch_cnt] [15];
    shiftOut [ch_cnt][15:0] = { shiftOut[ch_cnt] [14:0], 1'b0};
end/*/

endmodule