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Odroid N2+ Bootlog 1

Aug 25th, 2023 (edited)
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  1. No Cards Attached boot from UART, Switch SPI
  2.  
  3. G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
  4. bl2_stage_init 0x01
  5. bl2_stage_init 0x81
  6. hw id: 0x0000 - pwm id 0x01
  7. bl2_stage_init 0xc1
  8. bl2_stage_init 0x02
  9.  
  10. L0:00000000
  11. L1:00000703
  12. L2:0000c067
  13. L3:14000020
  14. B2:00402000
  15. B1:e0f83180
  16.  
  17. TE: 58141
  18.  
  19. BL2 Built : 06:17:13, Jun 28 2019. g12b gf0505d7-dirty - qi.duan@droid13
  20.  
  21. Board ID = 5
  22. Set A53 clk to 24M
  23. Set A73 clk to 24M
  24. Set clk81 to 24M
  25. A53 clk: 1200 MHz
  26. A73 clk: 1200 MHz
  27. CLK81: 166.6M
  28. smccc: 00012af9
  29. DDR driver_vesion: LPDDR4_PHY_V_0_1_14 build time: Jun 28 2019 06:17:09
  30. board id: 5
  31. Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
  32. fw parse done
  33. Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
  34. Load ddrfw from SPI, src: 0x0002c000, des: 0xfffd0000, size: 0x00004000, part: 0
  35. PIEI prepare done
  36. fastboot data load
  37. fastboot data verify
  38. verify result: 255
  39. Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
  40. DDR4 probe
  41. ddr clk to 1320MHz
  42. Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x0000c000, part: 0
  43. Check phy result
  44. INFO : End of initialization
  45. INFO : End of read enable training
  46. INFO : End of fine write leveling
  47. INFO : End of read dq deskew training
  48. INFO : End of MPR read delay center optimization
  49. INFO : End of Write leveling coarse delay
  50. INFO : End of write delay center optimization
  51. INFO : End of read delay center optimization
  52. INFO : End of max read latency training
  53. INFO : Training has run successfully!
  54. 1D training succeed
  55. Load ddrfw from SPI, src: 0x00020000, des: 0xfffd0000, size: 0x0000c000, part: 0
  56. Check phy result
  57. INFO : End of initialization
  58. INFO : End of 2D read delay Voltage center optimization
  59. INFO : End of 2D write delay Voltage center optimization
  60. INFO : Training has run successfully!
  61.  
  62. R0_RxClkDly_Margin==82 ps 7
  63. R0_TxDqDly_Margi==82 ps 7
  64.  
  65.  
  66. R1_RxClkDly_Margin==0 ps 0
  67. R1_TxDqDly_Margi==0 ps 0
  68.  
  69. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001
  70. 2D training succeed
  71. auto size-- 65535DDR cs0 size: 2048MB
  72. DDR cs1 size: 2048MB
  73. DMC_DDR_CTRL: 00600024DDR size: 3928MB
  74. cs0 DataBus test pass
  75. cs1 DataBus test pass
  76. cs0 AddrBus test pass
  77. cs1 AddrBus test pass
  78. pre test bdlr_100_average==425 bdlr_100_min==425 bdlr_100_max==425 bdlr_100_cur==425
  79. aft test bdlr_100_average==425 bdlr_100_min==425 bdlr_100_max==425 bdlr_100_cur==425
  80. non-sec scramble use zero key
  81. ddr scramble enabled
  82.  
  83. 100bdlr_step_size ps== 416
  84. result report
  85. boot times 0Enable ddr reg access
  86. Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
  87. Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x00094e00, part: 0
  88. 0.0;M3 CHK:0;cm4_sp_mode 0
  89. E30HDR
  90. MVN_1=0x00000000
  91. MVN_2=0x00000000
  92. [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz]
  93. OPS=0x40
  94. ring efuse init
  95. chipver efuse init
  96. 29 0c 40 00 01 0a 0f 00 00 04 34 38 38 4b 43 50
  97. [0.019858 Inits done]
  98. secure task start!
  99. high task start!
  100. low task start!
  101. run into bl31
  102. NOTICE: BL31: v1.3(release):ab8811b
  103. NOTICE: BL31: Built : 15:03:31, Feb 12 2019
  104. NOTICE: BL31: G12A normal boot!
  105. NOTICE: BL31: BL33 decompress pass
  106. ERROR: Error initializing runtime service opteed_fast
  107.  
  108.  
  109. U-Boot 2015.01 (Mar 17 2022 - 12:57:50)
  110.  
  111. DRAM: 3.5 GiB
  112. Relocation Offset is: d6ef4000
  113. spi_post_bind(spifc): req_seq = 0
  114. register usb cfg[0][1] = 00000000d7f86348
  115. MMC: aml_priv->desc_buf = 0x00000000d3ee47c0
  116. aml_priv->desc_buf = 0x00000000d3ee6b00
  117. SDIO Port C: 0, SDIO Port B: 1
  118. spifc_probe: reg=00000000ffd14000, mem_map=00000000f6000000
  119. SF: Detected XT25Q64 with page size 256 Bytes, erase size 4 KiB, total 8 MiB
  120. In: serial
  121. Out: serial
  122. Err: serial
  123. vpu: error: vpu: check dts: FDT_ERR_BADMAGIC, load default parameters
  124. vpu: driver version: v20190313
  125. vpu: detect chip type: 9
  126. vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
  127. vpu: clk_level = 7
  128. vpu: vpu_power_on
  129. vpu: set_vpu_clk
  130. vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
  131. vpu: set_vpu_clk finish
  132. vpu: vpu_module_init_config
  133. vpp: vpp_init
  134. vpp: g12a/b osd1 matrix rgb2yuv ..............
  135. vpp: g12a/b osd2 matrix rgb2yuv..............
  136. vpp: g12a/b osd3 matrix rgb2yuv..............
  137. cvbs: cpuid:0x29
  138. cvbs_config_hdmipll_g12a
  139. cvbs_set_vid2_clk
  140. aml_i2c_init_port init regs for 2
  141. [aml_i2c_xfer] error ret = -5 i2c master a current slave addr is 0x32
  142. i2c 0xff 0x60 write failed
  143. [aml_i2c_xfer] error ret = -5 i2c master a current slave addr is 0x32
  144. i2c 0x00 read failed
  145. [aml_i2c_xfer] error ret = -5 i2c master a current slave addr is 0x32
  146. i2c 0x01 read failed
  147. [aml_i2c_xfer] error ret = -5 i2c master a current slave addr is 0x32
  148. i2c 0x02 read failed
  149. Read Chip : 0x0, 0x0, 0x0
  150. failed to read LT8619C chip id
  151. lt8619c hdmi_to_lcd device not found.!
  152. co-phase 0x3, tx-dly 0, clock 400000
  153. co-phase 0x3, tx-dly 0, clock 400000
  154. co-phase 0x3, tx-dly 0, clock 400000
  155. emmc/sd response timeout, cmd8, status=0x1bf2800
  156. emmc/sd response timeout, cmd55, status=0x1bf2800
  157. emmc/sd response timeout, cmd1, status=0x1bf2800
  158. Net: dwmac.ff3f0000
  159. Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
  160. SF: Detected XT25Q64 with page size 256 Bytes, erase size 4 KiB, total 8 MiB
  161. SF: 7274496 bytes @ 0x110000 Read: OK
  162. ### CRAMFS load complete: 2156 bytes loaded to 0x10000000
  163. ## Executing script at 10000000
  164. [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
  165. [OSD]set initrd_high: 0x3d800000
  166. [OSD]fb_addr for logo: 0x3d800000
  167. [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
  168. [OSD]fb_addr for logo: 0x3d800000
  169. [OSD]VPP_OFIFO_SIZE:0xfff01fff
  170. [CANVAS]canvas init
  171. [CANVAS]addr=0x3d800000 width=5760, height=2160
  172. cvbs: outputmode[1080p60hz] is invalid
  173. vpp: vpp_matrix_update: 2
  174. set hdmitx VIC = 16
  175. config HPLL = 5940000 frac_rate = 1
  176. HPLL: 0x3b3a04f7
  177. HPLL: 0x1b3a04f7
  178. HPLLv1: 0xdb3a04f7
  179. config HPLL done
  180. j = 6 vid_clk_div = 1
  181. hdmitx phy setting done
  182. hdmitx: set enc for VIC: 16
  183. enc_vpu_bridge_reset[1319]
  184. rx version is 1.4 or below div=10
  185. HDMI cable is NOT connected
  186. card out
  187. ** Bad device mmc 1 **
  188. ### CRAMFS load complete: 41831 bytes loaded to 0x3000000
  189. [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
  190. [OSD]fb_addr for logo: 0x3d800000
  191. [OSD]check dts: FDT_ERR_BADMAGIC, load default fb_addr parameters
  192. [OSD]fb_addr for logo: 0x3d800000
  193. [OSD]VPP_OFIFO_SIZE:0xfff01000
  194. [CANVAS]addr=0x3d800000 width=3840, height=1440
  195. cvbs: outputmode[720p60hz] is invalid
  196. vpp: vpp_matrix_update: 2
  197. set hdmitx VIC = 4
  198. config HPLL = 5940000 frac_rate = 1
  199. HPLL: 0x3b3a04f7
  200. HPLL: 0x1b3a04f7
  201. HPLLv1: 0xdb3a04f7
  202. config HPLL done
  203. j = 3 vid_clk_div = 1
  204. hdmitx phy setting done
  205. hdmitx: set enc for VIC: 4
  206. enc_vpu_bridge_reset[1319]
  207. rx version is 1.4 or below div=10
  208. set hdmitx VIC = 4
  209. config HPLL = 5940000 frac_rate = 1
  210. HPLL: 0x3b3a04f7
  211. HPLL: 0x1b3a04f7
  212. HPLLv1: 0xdb3a04f7
  213. config HPLL done
  214. j = 3 vid_clk_div = 1
  215. hdmitx phy setting done
  216. hdmitx: set enc for VIC: 4
  217. enc_vpu_bridge_reset[1319]
  218. rx version is 1.4 or below div=10
  219. [OSD]osd_hw.free_dst_data: 0,1279,0,719
  220. card out
  221. ** Bad device mmc 1 **
  222. card out
  223. ** Bad device mmc 1 **
  224. ### CRAMFS load complete: 3937382 bytes loaded to 0x2000000
  225. ### CRAMFS load complete: 3011728 bytes loaded to 0x3000000
  226. ### CRAMFS load complete: 71708 bytes loaded to 0x1000000
  227. ee_gate_off ...
  228. ## Booting kernel from Legacy Image at 02000000 ...
  229. Image Name:
  230. Image Type: AArch64 Linux Kernel Image (gzip compressed)
  231. Data Size: 3937318 Bytes = 3.8 MiB
  232. Load Address: 01080000
  233. Entry Point: 01080000
  234. Verifying Checksum ... OK
  235. ## Loading init Ramdisk from Legacy Image at 03000000 ...
  236. Image Name:
  237. Image Type: AArch64 Linux RAMDisk Image (uncompressed)
  238. Data Size: 3011664 Bytes = 2.9 MiB
  239. Load Address: 00000000
  240. Entry Point: 00000000
  241. Verifying Checksum ... OK
  242. active_slot is <NULL>
  243. Unknown command 'store' - try 'help'
  244. No dtbo patitions found
  245. load dtb from 0x1000000 ......
  246. ## Flattened Device Tree blob at 01000000
  247. Booting using the fdt blob at 0x1000000
  248. No valid dtbo image found
  249. Uncompressing Kernel Image ... OK
  250. kernel loaded at 0x01080000, end = 0x019ec808
  251. reserving fdt memory region: addr=1000000 size=12000
  252. Loading Ramdisk to 3d520000, end 3d7ff450 ... OK
  253. Loading Device Tree to 000000001ffeb000, end 000000001ffff81b ... OK
  254.  
  255. Starting kernel ...
  256.  
  257. uboot time: 6046212 us
  258.  
  259.  
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