--tentamenBcodeslot

library ieee;
use ieee.std_logic_1164.all;

entity tentamenBcodeslot is
	port (	SW		: in 	std_logic_vector(17 downto 0);
				KEY 	: in	std_logic_vector(1 downto 0);
				LEDG	: out	std_logic_vector(3 downto 0);
				LEDR	: out	std_LOGIC_VECTOR(17 downto 0);
				HEX0	: out	std_LOGIC_VECTOR(0 to 6)
			);
end tentamenBcodeslot;

architecture arch of tentamenBcodeslot is

	COMPONENT hex7seg IS
		PORT (
					hex		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
					display	: OUT	STD_LOGIC_VECTOR(0 TO 6));
	END COMPONENT hex7seg;

	-- Build an enumerated type for the state machine
	type state_type is (s0, s1, s2, s3);

	-- Register to hold the current state
	signal state   	: state_type;
	signal clk			: std_logic;
	signal reset		: std_logic;
	signal input		: std_logic_vector(3 downto 0);
	signal Q				: std_logic_vector(2 downto 0);
	signal slotopen	: std_logic;

begin

	clk 	<= not(KEY(0));
	reset <= not(key(1));
	input <= SW(3 downto 0);
	LEDG	<= Q & slotopen;
	LEDR 	<= SW;

	h0: hex7seg port map(input, HEX0);

	-- Logic to advance to the next state

	process (clk, reset)
	begin
		if reset = '1' then
			state <= s0;
		elsif (rising_edge(clk)) then
			case state is
				when s0=>
					if input = "0110" then
						state <= s1;
					else
						state <= s0;
					end if;
				when s1=>
					if input = "1010" then
						state <= s2;
					else
						state <= s0;
					end if;
				when s2=>
					if input = "0001" then
						state <= s3;
					else
						state <= s0;
					end if;
				when s3 =>
					state <= s0;
			end case;
		end if;
	end process;

	-- Output depends solely on the current state
	process (state)
	begin
		case state is
			when s0 =>
				Q <= "100";
				slotopen <= '0';
			when s1 =>
				Q <= "110";
				slotopen <= '0';
			when s2 =>
				Q <= "111";
				slotopen <= '0';
			when s3 =>
				Q <= "000";
				slotopen <= '1';
		end case;
	end process;

end arch;

library ieee;
use ieee.std_logic_1164.all;

ENTITY hex7seg IS
	PORT (
				hex		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
				display	: OUT	STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;

ARCHITECTURE Behavior OF hex7seg IS
BEGIN
	--
	--       0
	--      ---
	--     |   |
	--    5|   |1
	--     | 6 |
	--      ---
	--     |   |
	--    4|   |2
	--     |   |
	--      ---
	--       3
	--
	PROCESS ( hex)
	BEGIN
		CASE hex IS
			WHEN "0000" => display <= "0000001";
			WHEN "0001" => display <= "1001111";
			WHEN "0010" => display <= "0010010";
			WHEN "0011" => display <= "0000110";
			WHEN "0100" => display <= "1001100";
			WHEN "0101" => display <= "0100100";
			WHEN "0110" => display <= "0100000";
			WHEN "0111" => display <= "0001111";
			WHEN "1000" => display <= "0000000";
			WHEN "1001" => display <= "0000100";
			WHEN "1010" => display <= "0001000";
			WHEN "1011" => display <= "1100000";
			WHEN "1100" => display <= "0110001";
			WHEN "1101" => display <= "1000010";
			WHEN "1110" => display <= "0110000";
			WHEN "1111" => display <= "0111000";
			WHEN OTHERS => display <= "1111111";		--	empty
		END CASE;
	END PROCESS;

END behavior;