library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xor8 is
port (
	y :out std_logic;
	a :in  std_logic;
	b :in  std_logic;
	c :in  std_logic;
	d :in  std_logic;
	e :in  std_logic;
	f :in  std_logic;
	g :in  std_logic;
	h :in  std_logic
	);
end entity;

architecture rtl of xor8 is
	begin
		process (a, b, c, d, e, f, g, h) begin
			y <= a xor b xor c xor d xor e xor f xor g xor h;
		end process;
end architecture;