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  1.  
  2. `timescale 1 ns / 1 ps
  3.  
  4.     module axis_test_v1_0 #
  5.     (
  6.         // Users to add parameters here
  7.  
  8.         // User parameters ends
  9.         // Do not modify the parameters beyond this line
  10.  
  11.  
  12.         // Parameters of Axi Slave Bus Interface S00_AXIS
  13.         parameter integer C_S00_AXIS_TDATA_WIDTH    = 32,
  14.  
  15.         // Parameters of Axi Master Bus Interface M00_AXIS
  16.         parameter integer C_M00_AXIS_TDATA_WIDTH    = 32,
  17.         parameter integer C_M00_AXIS_START_COUNT    = 32
  18.     )
  19.     (
  20.         // Users to add ports here
  21.  
  22.         // User ports ends
  23.         // Do not modify the ports beyond this line
  24.  
  25.  
  26.         // Ports of Axi Slave Bus Interface S00_AXIS
  27.         input wire  s00_axis_aclk,
  28.         input wire  s00_axis_aresetn,
  29.         output wire  s00_axis_tready,
  30.         input wire [C_S00_AXIS_TDATA_WIDTH-1 : 0] s00_axis_tdata,
  31.         input wire [(C_S00_AXIS_TDATA_WIDTH/8)-1 : 0] s00_axis_tstrb,
  32.         input wire  s00_axis_tlast,
  33.         input wire  s00_axis_tvalid,
  34.  
  35.         // Ports of Axi Master Bus Interface M00_AXIS
  36.         input wire  m00_axis_aclk,
  37.         input wire  m00_axis_aresetn,
  38.         output wire  m00_axis_tvalid,
  39.         output wire [C_M00_AXIS_TDATA_WIDTH-1 : 0] m00_axis_tdata,
  40.         output wire [(C_M00_AXIS_TDATA_WIDTH/8)-1 : 0] m00_axis_tstrb,
  41.         output wire  m00_axis_tlast,
  42.         input wire  m00_axis_tready
  43.     );
  44. // Instantiation of Axi Bus Interface S00_AXIS
  45.     axis_test_v1_0_S00_AXIS # (
  46.         .C_S_AXIS_TDATA_WIDTH(C_S00_AXIS_TDATA_WIDTH)
  47.     ) axis_test_v1_0_S00_AXIS_inst (
  48.         .processedData(),                    //Тут надо как-то хитровыебанно передать m00_axis_tdata, но я не знаю как
  49.         .S_AXIS_ACLK(s00_axis_aclk),
  50.         .S_AXIS_ARESETN(s00_axis_aresetn),
  51.         .S_AXIS_TREADY(s00_axis_tready),
  52.         .S_AXIS_TDATA(s00_axis_tdata),
  53.         .S_AXIS_TSTRB(s00_axis_tstrb),
  54.         .S_AXIS_TLAST(s00_axis_tlast),
  55.         .S_AXIS_TVALID(s00_axis_tvalid)
  56.     );
  57.  
  58. // Instantiation of Axi Bus Interface M00_AXIS
  59.     axis_test_v1_0_M00_AXIS # (
  60.         .C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH),
  61.         .C_M_START_COUNT(C_M00_AXIS_START_COUNT)
  62.     ) axis_test_v1_0_M00_AXIS_inst (
  63.         .M_AXIS_ACLK(m00_axis_aclk),
  64.         .M_AXIS_ARESETN(m00_axis_aresetn),
  65.         .M_AXIS_TVALID(m00_axis_tvalid),
  66.         .M_AXIS_TDATA(m00_axis_tdata),
  67.         .M_AXIS_TSTRB(m00_axis_tstrb),
  68.         .M_AXIS_TLAST(m00_axis_tlast),
  69.         .M_AXIS_TREADY(m00_axis_tready)
  70.     );
  71.  
  72.     // Add user logic here
  73.  
  74.     // User logic ends
  75.  
  76.     endmodule
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