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ardbeg_tn8.dts

Insei
Jul 19th, 2016
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  1. /dts-v1/;
  2.  
  3. / {
  4. compatible = "nvidia,tn8", "nvidia,tegra124";
  5. interrupt-parent = <0x1>;
  6. #address-cells = <0x2>;
  7. #size-cells = <0x2>;
  8. model = "NVIDIA Tegra124 TN8 FFD";
  9. nvidia,dtsfilename = "arch/arm/boot/dts/tegra124-tn8-p1761-1270-a04-e-battery.dts";
  10. nvidia,boardids = "1761:1270:4";
  11.  
  12. aliases {
  13. i2c0 = "/i2c@7000c000";
  14. i2c1 = "/i2c@7000c400";
  15. i2c2 = "/i2c@7000c500";
  16. i2c3 = "/i2c@7000c700";
  17. i2c4 = "/i2c@7000d000";
  18. i2c5 = "/i2c@7000d100";
  19. serial0 = "/serial@70006000";
  20. serial1 = "/serial@70006040";
  21. serial2 = "/serial@70006200";
  22. serial3 = "/serial@70006300";
  23. spi0 = "/spi@7000d400";
  24. spi1 = "/spi@7000d600";
  25. spi2 = "/spi@7000d800";
  26. spi3 = "/spi@7000da00";
  27. spi4 = "/spi@7000dc00";
  28. spi5 = "/spi@7000de00";
  29. };
  30.  
  31. gpio@6000d000 {
  32. compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  33. reg = <0x0 0x6000d000 0x0 0x1000>;
  34. interrupts = <0x0 0x20 0x4 0x0 0x21 0x4 0x0 0x22 0x4 0x0 0x23 0x4 0x0 0x37 0x4 0x0 0x57 0x4 0x0 0x59 0x4 0x0 0x7d 0x4>;
  35. #gpio-cells = <0x2>;
  36. gpio-controller;
  37. #interrupt-cells = <0x2>;
  38. interrupt-controller;
  39. gpio-init-names = "default";
  40. gpio-init-0 = <0x2>;
  41. linux,phandle = <0x7>;
  42. phandle = <0x7>;
  43.  
  44. default {
  45. gpio-input = <0x17 0x3c 0x41 0x46 0x48 0x50 0x52 0x55 0x6f 0x75 0x80 0x85 0x86 0x87 0x8c 0x90 0xa4 0xa5 0xa6 0xa8 0xa9 0xb3 0xbb>;
  46. gpio-output-low = <0x3b 0x3d 0x40 0x51 0x54 0x56 0x6d 0x76 0x88 0x89 0x8a 0x8d 0x93 0x94 0xbf 0xdb 0xdd 0xde 0xdf 0xf1>;
  47. gpio-output-high = <0x3a 0x6c>;
  48. linux,phandle = <0x2>;
  49. phandle = <0x2>;
  50. };
  51. };
  52.  
  53. se@70012000 {
  54. compatible = "nvidia,tegra124-se";
  55. reg = <0x0 0x70012000 0x0 0x2000 0x0 0x7000e400 0x0 0x400>;
  56. interrupts = <0x0 0x3a 0x4>;
  57. };
  58.  
  59. clock {
  60. compatible = "nvidia,tegra124-car";
  61. reg = <0x0 0x60006000 0x0 0x1000>;
  62. #clock-cells = <0x1>;
  63. linux,phandle = <0x10>;
  64. phandle = <0x10>;
  65. };
  66.  
  67. dma@60020000 {
  68. compatible = "nvidia,tegra124-apbdma";
  69. reg = <0x0 0x60020000 0x0 0x1400>;
  70. interrupts = <0x0 0x68 0x4 0x0 0x69 0x4 0x0 0x6a 0x4 0x0 0x6b 0x4 0x0 0x6c 0x4 0x0 0x6d 0x4 0x0 0x6e 0x4 0x0 0x6f 0x4 0x0 0x70 0x4 0x0 0x71 0x4 0x0 0x72 0x4 0x0 0x73 0x4 0x0 0x74 0x4 0x0 0x75 0x4 0x0 0x76 0x4 0x0 0x77 0x4 0x0 0x80 0x4 0x0 0x81 0x4 0x0 0x82 0x4 0x0 0x83 0x4 0x0 0x84 0x4 0x0 0x85 0x4 0x0 0x86 0x4 0x0 0x87 0x4 0x0 0x88 0x4 0x0 0x89 0x4 0x0 0x8a 0x4 0x0 0x8b 0x4 0x0 0x8c 0x4 0x0 0x8d 0x4 0x0 0x8e 0x4 0x0 0x8f 0x4>;
  71. linux,phandle = <0x6>;
  72. phandle = <0x6>;
  73. };
  74.  
  75. pinmux {
  76. compatible = "nvidia,tegra124-pinmux";
  77. reg = <0x0 0x70000868 0x0 0x164 0x0 0x70003000 0x0 0x434>;
  78. pinctrl-names = "default", "drive", "unused";
  79. pinctrl-0 = <0x3>;
  80. pinctrl-1 = <0x4>;
  81. pinctrl-2 = <0x5>;
  82.  
  83. common {
  84. linux,phandle = <0x3>;
  85. phandle = <0x3>;
  86.  
  87. dap_mclk1_pw4 {
  88. nvidia,pins = "dap_mclk1_pw4";
  89. nvidia,function = "extperiph1";
  90. nvidia,enable-input = <0x0>;
  91. nvidia,pull = <0x0>;
  92. nvidia,tristate = <0x0>;
  93. };
  94.  
  95. dap1_din_pn1 {
  96. nvidia,pins = "dap1_din_pn1";
  97. nvidia,function = "i2s0";
  98. nvidia,enable-input = <0x1>;
  99. nvidia,pull = <0x0>;
  100. nvidia,tristate = <0x0>;
  101. };
  102.  
  103. dap1_dout_pn2 {
  104. nvidia,pins = "dap1_dout_pn2";
  105. nvidia,function = "i2s0";
  106. nvidia,enable-input = <0x1>;
  107. nvidia,pull = <0x0>;
  108. nvidia,tristate = <0x0>;
  109. };
  110.  
  111. dap1_fs_pn0 {
  112. nvidia,pins = "dap1_fs_pn0";
  113. nvidia,function = "i2s0";
  114. nvidia,enable-input = <0x1>;
  115. nvidia,pull = <0x0>;
  116. nvidia,tristate = <0x0>;
  117. };
  118.  
  119. dap1_sclk_pn3 {
  120. nvidia,pins = "dap1_sclk_pn3";
  121. nvidia,function = "i2s0";
  122. nvidia,enable-input = <0x1>;
  123. nvidia,pull = <0x0>;
  124. nvidia,tristate = <0x0>;
  125. };
  126.  
  127. dap2_din_pa4 {
  128. nvidia,pins = "dap2_din_pa4";
  129. nvidia,function = "i2s1";
  130. nvidia,enable-input = <0x1>;
  131. nvidia,pull = <0x0>;
  132. nvidia,tristate = <0x0>;
  133. };
  134.  
  135. dap2_dout_pa5 {
  136. nvidia,pins = "dap2_dout_pa5";
  137. nvidia,function = "i2s1";
  138. nvidia,enable-input = <0x1>;
  139. nvidia,pull = <0x0>;
  140. nvidia,tristate = <0x0>;
  141. };
  142.  
  143. dap2_fs_pa2 {
  144. nvidia,pins = "dap2_fs_pa2";
  145. nvidia,function = "i2s1";
  146. nvidia,enable-input = <0x1>;
  147. nvidia,pull = <0x0>;
  148. nvidia,tristate = <0x0>;
  149. };
  150.  
  151. dap2_sclk_pa3 {
  152. nvidia,pins = "dap2_sclk_pa3";
  153. nvidia,function = "i2s1";
  154. nvidia,enable-input = <0x1>;
  155. nvidia,pull = <0x0>;
  156. nvidia,tristate = <0x0>;
  157. };
  158.  
  159. ulpi_clk_py0 {
  160. nvidia,pins = "ulpi_clk_py0";
  161. nvidia,function = "spi1";
  162. nvidia,enable-input = <0x0>;
  163. nvidia,pull = <0x0>;
  164. nvidia,tristate = <0x0>;
  165. };
  166.  
  167. ulpi_dir_py1 {
  168. nvidia,pins = "ulpi_dir_py1";
  169. nvidia,function = "spi1";
  170. nvidia,enable-input = <0x1>;
  171. nvidia,pull = <0x0>;
  172. nvidia,tristate = <0x0>;
  173. };
  174.  
  175. ulpi_nxt_py2 {
  176. nvidia,pins = "ulpi_nxt_py2";
  177. nvidia,function = "spi1";
  178. nvidia,enable-input = <0x0>;
  179. nvidia,pull = <0x0>;
  180. nvidia,tristate = <0x0>;
  181. };
  182.  
  183. ulpi_stp_py3 {
  184. nvidia,pins = "ulpi_stp_py3";
  185. nvidia,function = "spi1";
  186. nvidia,enable-input = <0x0>;
  187. nvidia,pull = <0x0>;
  188. nvidia,tristate = <0x0>;
  189. };
  190.  
  191. cam_i2c_scl_pbb1 {
  192. nvidia,pins = "cam_i2c_scl_pbb1";
  193. nvidia,function = "i2c3";
  194. nvidia,enable-input = <0x1>;
  195. nvidia,pull = <0x0>;
  196. nvidia,tristate = <0x0>;
  197. nvidia,lock = <0x0>;
  198. nvidia,open-drain = <0x1>;
  199. };
  200.  
  201. cam_i2c_sda_pbb2 {
  202. nvidia,pins = "cam_i2c_sda_pbb2";
  203. nvidia,function = "i2c3";
  204. nvidia,enable-input = <0x1>;
  205. nvidia,pull = <0x0>;
  206. nvidia,tristate = <0x0>;
  207. nvidia,lock = <0x0>;
  208. nvidia,open-drain = <0x1>;
  209. };
  210.  
  211. cam_mclk_pcc0 {
  212. nvidia,pins = "cam_mclk_pcc0";
  213. nvidia,function = "vi_alt3";
  214. nvidia,enable-input = <0x0>;
  215. nvidia,pull = <0x0>;
  216. nvidia,tristate = <0x0>;
  217. };
  218.  
  219. pbb0 {
  220. nvidia,pins = "pbb0";
  221. nvidia,function = "vimclk2_alt";
  222. nvidia,enable-input = <0x0>;
  223. nvidia,pull = <0x0>;
  224. nvidia,tristate = <0x0>;
  225. };
  226.  
  227. gen2_i2c_scl_pt5 {
  228. nvidia,pins = "gen2_i2c_scl_pt5";
  229. nvidia,function = "i2c2";
  230. nvidia,enable-input = <0x1>;
  231. nvidia,pull = <0x0>;
  232. nvidia,tristate = <0x0>;
  233. nvidia,lock = <0x0>;
  234. nvidia,open-drain = <0x1>;
  235. };
  236.  
  237. gen2_i2c_sda_pt6 {
  238. nvidia,pins = "gen2_i2c_sda_pt6";
  239. nvidia,function = "i2c2";
  240. nvidia,enable-input = <0x1>;
  241. nvidia,pull = <0x0>;
  242. nvidia,tristate = <0x0>;
  243. nvidia,lock = <0x0>;
  244. nvidia,open-drain = <0x1>;
  245. };
  246.  
  247. pj7 {
  248. nvidia,pins = "pj7";
  249. nvidia,function = "uartd";
  250. nvidia,enable-input = <0x0>;
  251. nvidia,pull = <0x0>;
  252. nvidia,tristate = <0x0>;
  253. };
  254.  
  255. pb0 {
  256. nvidia,pins = "pb0";
  257. nvidia,function = "uartd";
  258. nvidia,enable-input = <0x1>;
  259. nvidia,pull = <0x2>;
  260. nvidia,tristate = <0x0>;
  261. };
  262.  
  263. pb1 {
  264. nvidia,pins = "pb1";
  265. nvidia,function = "uartd";
  266. nvidia,enable-input = <0x1>;
  267. nvidia,pull = <0x2>;
  268. nvidia,tristate = <0x0>;
  269. };
  270.  
  271. pk7 {
  272. nvidia,pins = "pk7";
  273. nvidia,function = "uartd";
  274. nvidia,enable-input = <0x0>;
  275. nvidia,pull = <0x0>;
  276. nvidia,tristate = <0x0>;
  277. };
  278.  
  279. ph1 {
  280. nvidia,pins = "ph1";
  281. nvidia,function = "pwm1";
  282. nvidia,enable-input = <0x0>;
  283. nvidia,pull = <0x0>;
  284. nvidia,tristate = <0x0>;
  285. };
  286.  
  287. pk0 {
  288. nvidia,pins = "pk0";
  289. nvidia,function = "safe";
  290. nvidia,enable-input = <0x1>;
  291. nvidia,pull = <0x1>;
  292. nvidia,tristate = <0x0>;
  293. };
  294.  
  295. pj2 {
  296. nvidia,pins = "pj2";
  297. nvidia,function = "soc";
  298. nvidia,enable-input = <0x1>;
  299. nvidia,pull = <0x2>;
  300. nvidia,tristate = <0x0>;
  301. };
  302.  
  303. clk_32k_out_pa0 {
  304. nvidia,pins = "clk_32k_out_pa0";
  305. nvidia,function = "soc";
  306. nvidia,enable-input = <0x1>;
  307. nvidia,pull = <0x2>;
  308. nvidia,tristate = <0x0>;
  309. };
  310.  
  311. sdmmc1_clk_pz0 {
  312. nvidia,pins = "sdmmc1_clk_pz0";
  313. nvidia,function = "sdmmc1";
  314. nvidia,enable-input = <0x1>;
  315. nvidia,pull = <0x0>;
  316. nvidia,tristate = <0x0>;
  317. };
  318.  
  319. sdmmc1_cmd_pz1 {
  320. nvidia,pins = "sdmmc1_cmd_pz1";
  321. nvidia,function = "sdmmc1";
  322. nvidia,enable-input = <0x1>;
  323. nvidia,pull = <0x2>;
  324. nvidia,tristate = <0x0>;
  325. };
  326.  
  327. sdmmc1_dat0_py7 {
  328. nvidia,pins = "sdmmc1_dat0_py7";
  329. nvidia,function = "sdmmc1";
  330. nvidia,enable-input = <0x1>;
  331. nvidia,pull = <0x2>;
  332. nvidia,tristate = <0x0>;
  333. };
  334.  
  335. sdmmc1_dat1_py6 {
  336. nvidia,pins = "sdmmc1_dat1_py6";
  337. nvidia,function = "sdmmc1";
  338. nvidia,enable-input = <0x1>;
  339. nvidia,pull = <0x2>;
  340. nvidia,tristate = <0x0>;
  341. };
  342.  
  343. sdmmc1_dat2_py5 {
  344. nvidia,pins = "sdmmc1_dat2_py5";
  345. nvidia,function = "sdmmc1";
  346. nvidia,enable-input = <0x1>;
  347. nvidia,pull = <0x2>;
  348. nvidia,tristate = <0x0>;
  349. };
  350.  
  351. sdmmc1_dat3_py4 {
  352. nvidia,pins = "sdmmc1_dat3_py4";
  353. nvidia,function = "sdmmc1";
  354. nvidia,enable-input = <0x1>;
  355. nvidia,pull = <0x2>;
  356. nvidia,tristate = <0x0>;
  357. };
  358.  
  359. sdmmc3_clk_pa6 {
  360. nvidia,pins = "sdmmc3_clk_pa6";
  361. nvidia,function = "sdmmc3";
  362. nvidia,enable-input = <0x1>;
  363. nvidia,pull = <0x0>;
  364. nvidia,tristate = <0x0>;
  365. };
  366.  
  367. sdmmc3_cmd_pa7 {
  368. nvidia,pins = "sdmmc3_cmd_pa7";
  369. nvidia,function = "sdmmc3";
  370. nvidia,enable-input = <0x1>;
  371. nvidia,pull = <0x2>;
  372. nvidia,tristate = <0x0>;
  373. };
  374.  
  375. sdmmc3_dat0_pb7 {
  376. nvidia,pins = "sdmmc3_dat0_pb7";
  377. nvidia,function = "sdmmc3";
  378. nvidia,enable-input = <0x1>;
  379. nvidia,pull = <0x2>;
  380. nvidia,tristate = <0x0>;
  381. };
  382.  
  383. sdmmc3_dat1_pb6 {
  384. nvidia,pins = "sdmmc3_dat1_pb6";
  385. nvidia,function = "sdmmc3";
  386. nvidia,enable-input = <0x1>;
  387. nvidia,pull = <0x2>;
  388. nvidia,tristate = <0x0>;
  389. };
  390.  
  391. sdmmc3_dat2_pb5 {
  392. nvidia,pins = "sdmmc3_dat2_pb5";
  393. nvidia,function = "sdmmc3";
  394. nvidia,enable-input = <0x1>;
  395. nvidia,pull = <0x2>;
  396. nvidia,tristate = <0x0>;
  397. };
  398.  
  399. sdmmc3_dat3_pb4 {
  400. nvidia,pins = "sdmmc3_dat3_pb4";
  401. nvidia,function = "sdmmc3";
  402. nvidia,enable-input = <0x1>;
  403. nvidia,pull = <0x2>;
  404. nvidia,tristate = <0x0>;
  405. };
  406.  
  407. sdmmc3_clk_lb_out_pee4 {
  408. nvidia,pins = "sdmmc3_clk_lb_out_pee4";
  409. nvidia,function = "sdmmc3";
  410. nvidia,enable-input = <0x1>;
  411. nvidia,pull = <0x2>;
  412. nvidia,tristate = <0x0>;
  413. };
  414.  
  415. sdmmc3_clk_lb_in_pee5 {
  416. nvidia,pins = "sdmmc3_clk_lb_in_pee5";
  417. nvidia,function = "sdmmc3";
  418. nvidia,enable-input = <0x1>;
  419. nvidia,pull = <0x2>;
  420. nvidia,tristate = <0x0>;
  421. };
  422.  
  423. sdmmc3_cd_n_pv2 {
  424. nvidia,pins = "sdmmc3_cd_n_pv2";
  425. nvidia,function = "sdmmc3";
  426. nvidia,enable-input = <0x1>;
  427. nvidia,pull = <0x2>;
  428. nvidia,tristate = <0x0>;
  429. };
  430.  
  431. sdmmc4_clk_pcc4 {
  432. nvidia,pins = "sdmmc4_clk_pcc4";
  433. nvidia,function = "sdmmc4";
  434. nvidia,enable-input = <0x1>;
  435. nvidia,pull = <0x0>;
  436. nvidia,tristate = <0x0>;
  437. };
  438.  
  439. sdmmc4_cmd_pt7 {
  440. nvidia,pins = "sdmmc4_cmd_pt7";
  441. nvidia,function = "sdmmc4";
  442. nvidia,enable-input = <0x1>;
  443. nvidia,pull = <0x2>;
  444. nvidia,tristate = <0x0>;
  445. };
  446.  
  447. sdmmc4_dat0_paa0 {
  448. nvidia,pins = "sdmmc4_dat0_paa0";
  449. nvidia,function = "sdmmc4";
  450. nvidia,enable-input = <0x1>;
  451. nvidia,pull = <0x2>;
  452. nvidia,tristate = <0x0>;
  453. };
  454.  
  455. sdmmc4_dat1_paa1 {
  456. nvidia,pins = "sdmmc4_dat1_paa1";
  457. nvidia,function = "sdmmc4";
  458. nvidia,enable-input = <0x1>;
  459. nvidia,pull = <0x2>;
  460. nvidia,tristate = <0x0>;
  461. };
  462.  
  463. sdmmc4_dat2_paa2 {
  464. nvidia,pins = "sdmmc4_dat2_paa2";
  465. nvidia,function = "sdmmc4";
  466. nvidia,enable-input = <0x1>;
  467. nvidia,pull = <0x2>;
  468. nvidia,tristate = <0x0>;
  469. };
  470.  
  471. sdmmc4_dat3_paa3 {
  472. nvidia,pins = "sdmmc4_dat3_paa3";
  473. nvidia,function = "sdmmc4";
  474. nvidia,enable-input = <0x1>;
  475. nvidia,pull = <0x2>;
  476. nvidia,tristate = <0x0>;
  477. };
  478.  
  479. sdmmc4_dat4_paa4 {
  480. nvidia,pins = "sdmmc4_dat4_paa4";
  481. nvidia,function = "sdmmc4";
  482. nvidia,enable-input = <0x1>;
  483. nvidia,pull = <0x2>;
  484. nvidia,tristate = <0x0>;
  485. };
  486.  
  487. sdmmc4_dat5_paa5 {
  488. nvidia,pins = "sdmmc4_dat5_paa5";
  489. nvidia,function = "sdmmc4";
  490. nvidia,enable-input = <0x1>;
  491. nvidia,pull = <0x2>;
  492. nvidia,tristate = <0x0>;
  493. };
  494.  
  495. sdmmc4_dat6_paa6 {
  496. nvidia,pins = "sdmmc4_dat6_paa6";
  497. nvidia,function = "sdmmc4";
  498. nvidia,enable-input = <0x1>;
  499. nvidia,pull = <0x2>;
  500. nvidia,tristate = <0x0>;
  501. };
  502.  
  503. sdmmc4_dat7_paa7 {
  504. nvidia,pins = "sdmmc4_dat7_paa7";
  505. nvidia,function = "sdmmc4";
  506. nvidia,enable-input = <0x1>;
  507. nvidia,pull = <0x2>;
  508. nvidia,tristate = <0x0>;
  509. };
  510.  
  511. pwr_i2c_scl_pz6 {
  512. nvidia,pins = "pwr_i2c_scl_pz6";
  513. nvidia,function = "i2cpwr";
  514. nvidia,enable-input = <0x1>;
  515. nvidia,pull = <0x0>;
  516. nvidia,tristate = <0x0>;
  517. nvidia,open-drain = <0x1>;
  518. };
  519.  
  520. pwr_i2c_sda_pz7 {
  521. nvidia,pins = "pwr_i2c_sda_pz7";
  522. nvidia,function = "i2cpwr";
  523. nvidia,enable-input = <0x1>;
  524. nvidia,pull = <0x0>;
  525. nvidia,tristate = <0x0>;
  526. nvidia,open-drain = <0x1>;
  527. };
  528.  
  529. jtag_rtck {
  530. nvidia,pins = "jtag_rtck";
  531. nvidia,function = "rtck";
  532. nvidia,enable-input = <0x0>;
  533. nvidia,pull = <0x2>;
  534. nvidia,tristate = <0x0>;
  535. };
  536.  
  537. clk_32k_in {
  538. nvidia,pins = "clk_32k_in";
  539. nvidia,function = "clk";
  540. nvidia,enable-input = <0x1>;
  541. nvidia,pull = <0x0>;
  542. nvidia,tristate = <0x0>;
  543. };
  544.  
  545. core_pwr_req {
  546. nvidia,pins = "core_pwr_req";
  547. nvidia,function = "pwron";
  548. nvidia,enable-input = <0x0>;
  549. nvidia,pull = <0x0>;
  550. nvidia,tristate = <0x0>;
  551. };
  552.  
  553. cpu_pwr_req {
  554. nvidia,pins = "cpu_pwr_req";
  555. nvidia,function = "cpu";
  556. nvidia,enable-input = <0x0>;
  557. nvidia,pull = <0x0>;
  558. nvidia,tristate = <0x0>;
  559. };
  560.  
  561. pwr_int_n {
  562. nvidia,pins = "pwr_int_n";
  563. nvidia,function = "pmi";
  564. nvidia,enable-input = <0x1>;
  565. nvidia,pull = <0x2>;
  566. nvidia,tristate = <0x0>;
  567. };
  568.  
  569. reset_out_n {
  570. nvidia,pins = "reset_out_n";
  571. nvidia,function = "reset_out_n";
  572. nvidia,enable-input = <0x0>;
  573. nvidia,pull = <0x0>;
  574. nvidia,tristate = <0x0>;
  575. };
  576.  
  577. dap4_din_pp5 {
  578. nvidia,pins = "dap4_din_pp5";
  579. nvidia,function = "i2s3";
  580. nvidia,enable-input = <0x1>;
  581. nvidia,pull = <0x0>;
  582. nvidia,tristate = <0x0>;
  583. };
  584.  
  585. dap4_dout_pp6 {
  586. nvidia,pins = "dap4_dout_pp6";
  587. nvidia,function = "i2s3";
  588. nvidia,enable-input = <0x1>;
  589. nvidia,pull = <0x0>;
  590. nvidia,tristate = <0x0>;
  591. };
  592.  
  593. dap4_fs_pp4 {
  594. nvidia,pins = "dap4_fs_pp4";
  595. nvidia,function = "i2s3";
  596. nvidia,enable-input = <0x1>;
  597. nvidia,pull = <0x0>;
  598. nvidia,tristate = <0x0>;
  599. };
  600.  
  601. dap4_sclk_pp7 {
  602. nvidia,pins = "dap4_sclk_pp7";
  603. nvidia,function = "i2s3";
  604. nvidia,enable-input = <0x1>;
  605. nvidia,pull = <0x0>;
  606. nvidia,tristate = <0x0>;
  607. };
  608.  
  609. gen1_i2c_sda_pc5 {
  610. nvidia,pins = "gen1_i2c_sda_pc5";
  611. nvidia,function = "i2c1";
  612. nvidia,enable-input = <0x1>;
  613. nvidia,pull = <0x0>;
  614. nvidia,tristate = <0x0>;
  615. nvidia,lock = <0x0>;
  616. nvidia,open-drain = <0x1>;
  617. };
  618.  
  619. gen1_i2c_scl_pc4 {
  620. nvidia,pins = "gen1_i2c_scl_pc4";
  621. nvidia,function = "i2c1";
  622. nvidia,enable-input = <0x1>;
  623. nvidia,pull = <0x0>;
  624. nvidia,tristate = <0x0>;
  625. nvidia,lock = <0x0>;
  626. nvidia,open-drain = <0x1>;
  627. };
  628.  
  629. uart2_cts_n_pj5 {
  630. nvidia,pins = "uart2_cts_n_pj5";
  631. nvidia,function = "uartb";
  632. nvidia,enable-input = <0x1>;
  633. nvidia,pull = <0x2>;
  634. nvidia,tristate = <0x0>;
  635. };
  636.  
  637. uart2_rts_n_pj6 {
  638. nvidia,pins = "uart2_rts_n_pj6";
  639. nvidia,function = "uartb";
  640. nvidia,enable-input = <0x0>;
  641. nvidia,pull = <0x2>;
  642. nvidia,tristate = <0x0>;
  643. };
  644.  
  645. uart2_rxd_pc3 {
  646. nvidia,pins = "uart2_rxd_pc3";
  647. nvidia,function = "irda";
  648. nvidia,enable-input = <0x1>;
  649. nvidia,pull = <0x2>;
  650. nvidia,tristate = <0x0>;
  651. };
  652.  
  653. uart2_txd_pc2 {
  654. nvidia,pins = "uart2_txd_pc2";
  655. nvidia,function = "irda";
  656. nvidia,enable-input = <0x0>;
  657. nvidia,pull = <0x2>;
  658. nvidia,tristate = <0x0>;
  659. };
  660.  
  661. uart3_cts_n_pa1 {
  662. nvidia,pins = "uart3_cts_n_pa1";
  663. nvidia,function = "uartc";
  664. nvidia,enable-input = <0x1>;
  665. nvidia,pull = <0x2>;
  666. nvidia,tristate = <0x0>;
  667. };
  668.  
  669. uart3_rts_n_pc0 {
  670. nvidia,pins = "uart3_rts_n_pc0";
  671. nvidia,function = "uartc";
  672. nvidia,enable-input = <0x0>;
  673. nvidia,pull = <0x2>;
  674. nvidia,tristate = <0x0>;
  675. };
  676.  
  677. uart3_rxd_pw7 {
  678. nvidia,pins = "uart3_rxd_pw7";
  679. nvidia,function = "uartc";
  680. nvidia,enable-input = <0x1>;
  681. nvidia,pull = <0x2>;
  682. nvidia,tristate = <0x0>;
  683. };
  684.  
  685. uart3_txd_pw6 {
  686. nvidia,pins = "uart3_txd_pw6";
  687. nvidia,function = "uartc";
  688. nvidia,enable-input = <0x0>;
  689. nvidia,pull = <0x2>;
  690. nvidia,tristate = <0x0>;
  691. };
  692.  
  693. hdmi_cec_pee3 {
  694. nvidia,pins = "hdmi_cec_pee3";
  695. nvidia,function = "cec";
  696. nvidia,enable-input = <0x1>;
  697. nvidia,pull = <0x0>;
  698. nvidia,tristate = <0x0>;
  699. nvidia,open-drain = <0x1>;
  700. };
  701.  
  702. ddc_scl_pv4 {
  703. nvidia,pins = "ddc_scl_pv4";
  704. nvidia,function = "i2c4";
  705. nvidia,enable-input = <0x1>;
  706. nvidia,pull = <0x0>;
  707. nvidia,tristate = <0x0>;
  708. };
  709.  
  710. ddc_sda_pv5 {
  711. nvidia,pins = "ddc_sda_pv5";
  712. nvidia,function = "i2c4";
  713. nvidia,enable-input = <0x1>;
  714. nvidia,pull = <0x0>;
  715. nvidia,tristate = <0x0>;
  716. };
  717.  
  718. gpio_x7_aud_px7 {
  719. nvidia,pins = "gpio_x7_aud_px7";
  720. nvidia,function = "safe";
  721. nvidia,enable-input = <0x0>;
  722. nvidia,pull = <0x0>;
  723. nvidia,tristate = <0x0>;
  724. };
  725.  
  726. gpio_w3_aud_pw3 {
  727. nvidia,pins = "gpio_w3_aud_pw3";
  728. nvidia,function = "safe";
  729. nvidia,enable-input = <0x1>;
  730. nvidia,pull = <0x2>;
  731. nvidia,tristate = <0x0>;
  732. };
  733.  
  734. gpio_x3_aud_px3 {
  735. nvidia,pins = "gpio_x3_aud_px3";
  736. nvidia,function = "safe";
  737. nvidia,enable-input = <0x1>;
  738. nvidia,pull = <0x2>;
  739. nvidia,tristate = <0x0>;
  740. };
  741.  
  742. pv0 {
  743. nvidia,pins = "pv0";
  744. nvidia,function = "safe";
  745. nvidia,enable-input = <0x1>;
  746. nvidia,pull = <0x2>;
  747. nvidia,tristate = <0x0>;
  748. };
  749.  
  750. pv1 {
  751. nvidia,pins = "pv1";
  752. nvidia,function = "safe";
  753. nvidia,enable-input = <0x1>;
  754. nvidia,pull = <0x2>;
  755. nvidia,tristate = <0x0>;
  756. };
  757.  
  758. ulpi_data4_po5 {
  759. nvidia,pins = "ulpi_data4_po5";
  760. nvidia,function = "safe";
  761. nvidia,enable-input = <0x1>;
  762. nvidia,pull = <0x2>;
  763. nvidia,tristate = <0x0>;
  764. };
  765.  
  766. ulpi_data5_po6 {
  767. nvidia,pins = "ulpi_data5_po6";
  768. nvidia,function = "safe";
  769. nvidia,enable-input = <0x0>;
  770. nvidia,pull = <0x0>;
  771. nvidia,tristate = <0x0>;
  772. };
  773.  
  774. pbb3 {
  775. nvidia,pins = "pbb3";
  776. nvidia,function = "safe";
  777. nvidia,enable-input = <0x0>;
  778. nvidia,pull = <0x0>;
  779. nvidia,tristate = <0x0>;
  780. };
  781.  
  782. pbb5 {
  783. nvidia,pins = "pbb5";
  784. nvidia,function = "safe";
  785. nvidia,enable-input = <0x0>;
  786. nvidia,pull = <0x0>;
  787. nvidia,tristate = <0x0>;
  788. };
  789.  
  790. pbb6 {
  791. nvidia,pins = "pbb6";
  792. nvidia,function = "safe";
  793. nvidia,enable-input = <0x0>;
  794. nvidia,pull = <0x0>;
  795. nvidia,tristate = <0x0>;
  796. };
  797.  
  798. pbb7 {
  799. nvidia,pins = "pbb7";
  800. nvidia,function = "safe";
  801. nvidia,enable-input = <0x0>;
  802. nvidia,pull = <0x0>;
  803. nvidia,tristate = <0x0>;
  804. };
  805.  
  806. ph2 {
  807. nvidia,pins = "ph2";
  808. nvidia,function = "safe";
  809. nvidia,enable-input = <0x0>;
  810. nvidia,pull = <0x0>;
  811. nvidia,tristate = <0x0>;
  812. };
  813.  
  814. ph3 {
  815. nvidia,pins = "ph3";
  816. nvidia,function = "safe";
  817. nvidia,enable-input = <0x0>;
  818. nvidia,pull = <0x0>;
  819. nvidia,tristate = <0x0>;
  820. };
  821.  
  822. ph4 {
  823. nvidia,pins = "ph4";
  824. nvidia,function = "safe";
  825. nvidia,enable-input = <0x1>;
  826. nvidia,pull = <0x2>;
  827. nvidia,tristate = <0x0>;
  828. };
  829.  
  830. ph5 {
  831. nvidia,pins = "ph5";
  832. nvidia,function = "safe";
  833. nvidia,enable-input = <0x0>;
  834. nvidia,pull = <0x0>;
  835. nvidia,tristate = <0x0>;
  836. };
  837.  
  838. pk1 {
  839. nvidia,pins = "pk1";
  840. nvidia,function = "safe";
  841. nvidia,enable-input = <0x0>;
  842. nvidia,pull = <0x0>;
  843. nvidia,tristate = <0x0>;
  844. };
  845.  
  846. pj0 {
  847. nvidia,pins = "pj0";
  848. nvidia,function = "safe";
  849. nvidia,enable-input = <0x1>;
  850. nvidia,pull = <0x2>;
  851. nvidia,tristate = <0x0>;
  852. };
  853.  
  854. pk4 {
  855. nvidia,pins = "pk4";
  856. nvidia,function = "safe";
  857. nvidia,enable-input = <0x0>;
  858. nvidia,pull = <0x0>;
  859. nvidia,tristate = <0x0>;
  860. };
  861.  
  862. pk2 {
  863. nvidia,pins = "pk2";
  864. nvidia,function = "safe";
  865. nvidia,enable-input = <0x1>;
  866. nvidia,pull = <0x0>;
  867. nvidia,tristate = <0x0>;
  868. };
  869.  
  870. pi6 {
  871. nvidia,pins = "pi6";
  872. nvidia,function = "safe";
  873. nvidia,enable-input = <0x1>;
  874. nvidia,pull = <0x2>;
  875. nvidia,tristate = <0x0>;
  876. };
  877.  
  878. pi1 {
  879. nvidia,pins = "pi1";
  880. nvidia,function = "safe";
  881. nvidia,enable-input = <0x1>;
  882. nvidia,pull = <0x0>;
  883. nvidia,tristate = <0x0>;
  884. };
  885.  
  886. pc7 {
  887. nvidia,pins = "pc7";
  888. nvidia,function = "safe";
  889. nvidia,enable-input = <0x1>;
  890. nvidia,pull = <0x2>;
  891. nvidia,tristate = <0x0>;
  892. };
  893.  
  894. pi0 {
  895. nvidia,pins = "pi0";
  896. nvidia,function = "safe";
  897. nvidia,enable-input = <0x0>;
  898. nvidia,pull = <0x0>;
  899. nvidia,tristate = <0x0>;
  900. };
  901.  
  902. kb_col0_pq0 {
  903. nvidia,pins = "kb_col0_pq0";
  904. nvidia,function = "safe";
  905. nvidia,enable-input = <0x1>;
  906. nvidia,pull = <0x2>;
  907. nvidia,tristate = <0x0>;
  908. };
  909.  
  910. kb_col5_pq5 {
  911. nvidia,pins = "kb_col5_pq5";
  912. nvidia,function = "safe";
  913. nvidia,enable-input = <0x1>;
  914. nvidia,pull = <0x2>;
  915. nvidia,tristate = <0x0>;
  916. };
  917.  
  918. kb_col6_pq6 {
  919. nvidia,pins = "kb_col6_pq6";
  920. nvidia,function = "safe";
  921. nvidia,enable-input = <0x1>;
  922. nvidia,pull = <0x2>;
  923. nvidia,tristate = <0x0>;
  924. };
  925.  
  926. kb_col7_pq7 {
  927. nvidia,pins = "kb_col7_pq7";
  928. nvidia,function = "safe";
  929. nvidia,enable-input = <0x1>;
  930. nvidia,pull = <0x2>;
  931. nvidia,tristate = <0x0>;
  932. };
  933.  
  934. kb_row0_pr0 {
  935. nvidia,pins = "kb_row0_pr0";
  936. nvidia,function = "safe";
  937. nvidia,enable-input = <0x0>;
  938. nvidia,pull = <0x0>;
  939. nvidia,tristate = <0x0>;
  940. };
  941.  
  942. kb_row1_pr1 {
  943. nvidia,pins = "kb_row1_pr1";
  944. nvidia,function = "safe";
  945. nvidia,enable-input = <0x0>;
  946. nvidia,pull = <0x0>;
  947. nvidia,tristate = <0x0>;
  948. };
  949.  
  950. kb_row11_ps3 {
  951. nvidia,pins = "kb_row11_ps3";
  952. nvidia,function = "safe";
  953. nvidia,enable-input = <0x0>;
  954. nvidia,pull = <0x0>;
  955. nvidia,tristate = <0x0>;
  956. };
  957.  
  958. kb_row12_ps4 {
  959. nvidia,pins = "kb_row12_ps4";
  960. nvidia,function = "safe";
  961. nvidia,enable-input = <0x0>;
  962. nvidia,pull = <0x0>;
  963. nvidia,tristate = <0x0>;
  964. };
  965.  
  966. kb_row2_pr2 {
  967. nvidia,pins = "kb_row2_pr2";
  968. nvidia,function = "safe";
  969. nvidia,enable-input = <0x0>;
  970. nvidia,pull = <0x0>;
  971. nvidia,tristate = <0x0>;
  972. };
  973.  
  974. kb_row4_pr4 {
  975. nvidia,pins = "kb_row4_pr4";
  976. nvidia,function = "safe";
  977. nvidia,enable-input = <0x1>;
  978. nvidia,pull = <0x2>;
  979. nvidia,tristate = <0x0>;
  980. };
  981.  
  982. kb_row5_pr5 {
  983. nvidia,pins = "kb_row5_pr5";
  984. nvidia,function = "safe";
  985. nvidia,enable-input = <0x0>;
  986. nvidia,pull = <0x0>;
  987. nvidia,tristate = <0x0>;
  988. };
  989.  
  990. kb_row8_ps0 {
  991. nvidia,pins = "kb_row8_ps0";
  992. nvidia,function = "safe";
  993. nvidia,enable-input = <0x1>;
  994. nvidia,pull = <0x2>;
  995. nvidia,tristate = <0x0>;
  996. };
  997.  
  998. clk3_req_pee1 {
  999. nvidia,pins = "clk3_req_pee1";
  1000. nvidia,function = "safe";
  1001. nvidia,enable-input = <0x0>;
  1002. nvidia,pull = <0x0>;
  1003. nvidia,tristate = <0x0>;
  1004. };
  1005.  
  1006. pu5 {
  1007. nvidia,pins = "pu5";
  1008. nvidia,function = "safe";
  1009. nvidia,enable-input = <0x1>;
  1010. nvidia,pull = <0x0>;
  1011. nvidia,tristate = <0x0>;
  1012. };
  1013.  
  1014. pu6 {
  1015. nvidia,pins = "pu6";
  1016. nvidia,function = "safe";
  1017. nvidia,enable-input = <0x1>;
  1018. nvidia,pull = <0x0>;
  1019. nvidia,tristate = <0x0>;
  1020. };
  1021.  
  1022. hdmi_int_pn7 {
  1023. nvidia,pins = "hdmi_int_pn7";
  1024. nvidia,function = "rsvd1";
  1025. nvidia,enable-input = <0x1>;
  1026. nvidia,pull = <0x1>;
  1027. nvidia,tristate = <0x0>;
  1028. };
  1029.  
  1030. spdif_out_pk5 {
  1031. nvidia,pins = "spdif_out_pk5";
  1032. nvidia,function = "safe";
  1033. nvidia,enable-input = <0x1>;
  1034. nvidia,pull = <0x0>;
  1035. nvidia,tristate = <0x0>;
  1036. };
  1037.  
  1038. spdif_in_pk6 {
  1039. nvidia,pins = "spdif_in_pk6";
  1040. nvidia,function = "safe";
  1041. nvidia,enable-input = <0x0>;
  1042. nvidia,pull = <0x0>;
  1043. nvidia,tristate = <0x0>;
  1044. };
  1045.  
  1046. usb_vbus_en0_pn4 {
  1047. nvidia,pins = "usb_vbus_en0_pn4";
  1048. nvidia,function = "safe";
  1049. nvidia,enable-input = <0x0>;
  1050. nvidia,pull = <0x0>;
  1051. nvidia,tristate = <0x0>;
  1052. nvidia,open-drain = <0x0>;
  1053. };
  1054.  
  1055. usb_vbus_en1_pn5 {
  1056. nvidia,pins = "usb_vbus_en1_pn5";
  1057. nvidia,function = "safe";
  1058. nvidia,enable-input = <0x0>;
  1059. nvidia,pull = <0x0>;
  1060. nvidia,tristate = <0x0>;
  1061. nvidia,open-drain = <0x0>;
  1062. };
  1063. };
  1064.  
  1065. unused_lowpower {
  1066. linux,phandle = <0x5>;
  1067. phandle = <0x5>;
  1068.  
  1069. dap_mclk1_req_pee2 {
  1070. nvidia,pins = "dap_mclk1_req_pee2";
  1071. nvidia,function = "safe";
  1072. nvidia,enable-input = <0x0>;
  1073. nvidia,pull = <0x1>;
  1074. nvidia,tristate = <0x1>;
  1075. };
  1076.  
  1077. gpio_x4_aud_px4 {
  1078. nvidia,pins = "gpio_x4_aud_px4";
  1079. nvidia,function = "safe";
  1080. nvidia,enable-input = <0x0>;
  1081. nvidia,pull = <0x1>;
  1082. nvidia,tristate = <0x1>;
  1083. };
  1084.  
  1085. gpio_x5_aud_px5 {
  1086. nvidia,pins = "gpio_x5_aud_px5";
  1087. nvidia,function = "safe";
  1088. nvidia,enable-input = <0x0>;
  1089. nvidia,pull = <0x1>;
  1090. nvidia,tristate = <0x1>;
  1091. };
  1092.  
  1093. gpio_x6_aud_px6 {
  1094. nvidia,pins = "gpio_x6_aud_px6";
  1095. nvidia,function = "safe";
  1096. nvidia,enable-input = <0x0>;
  1097. nvidia,pull = <0x1>;
  1098. nvidia,tristate = <0x1>;
  1099. };
  1100.  
  1101. gpio_w2_aud_pw2 {
  1102. nvidia,pins = "gpio_w2_aud_pw2";
  1103. nvidia,function = "safe";
  1104. nvidia,enable-input = <0x0>;
  1105. nvidia,pull = <0x1>;
  1106. nvidia,tristate = <0x1>;
  1107. };
  1108.  
  1109. dvfs_pwm_px0 {
  1110. nvidia,pins = "dvfs_pwm_px0";
  1111. nvidia,function = "safe";
  1112. nvidia,enable-input = <0x0>;
  1113. nvidia,pull = <0x1>;
  1114. nvidia,tristate = <0x1>;
  1115. };
  1116.  
  1117. gpio_x1_aud_px1 {
  1118. nvidia,pins = "gpio_x1_aud_px1";
  1119. nvidia,function = "safe";
  1120. nvidia,enable-input = <0x0>;
  1121. nvidia,pull = <0x1>;
  1122. nvidia,tristate = <0x1>;
  1123. };
  1124.  
  1125. dvfs_clk_px2 {
  1126. nvidia,pins = "dvfs_clk_px2";
  1127. nvidia,function = "safe";
  1128. nvidia,enable-input = <0x0>;
  1129. nvidia,pull = <0x1>;
  1130. nvidia,tristate = <0x1>;
  1131. };
  1132.  
  1133. dap3_din_pp1 {
  1134. nvidia,pins = "dap3_din_pp1";
  1135. nvidia,function = "safe";
  1136. nvidia,enable-input = <0x0>;
  1137. nvidia,pull = <0x1>;
  1138. nvidia,tristate = <0x1>;
  1139. };
  1140.  
  1141. dap3_dout_pp2 {
  1142. nvidia,pins = "dap3_dout_pp2";
  1143. nvidia,function = "safe";
  1144. nvidia,enable-input = <0x0>;
  1145. nvidia,pull = <0x1>;
  1146. nvidia,tristate = <0x1>;
  1147. };
  1148.  
  1149. dap3_fs_pp0 {
  1150. nvidia,pins = "dap3_fs_pp0";
  1151. nvidia,function = "safe";
  1152. nvidia,enable-input = <0x0>;
  1153. nvidia,pull = <0x1>;
  1154. nvidia,tristate = <0x1>;
  1155. };
  1156.  
  1157. dap3_sclk_pp3 {
  1158. nvidia,pins = "dap3_sclk_pp3";
  1159. nvidia,function = "safe";
  1160. nvidia,enable-input = <0x0>;
  1161. nvidia,pull = <0x1>;
  1162. nvidia,tristate = <0x1>;
  1163. };
  1164.  
  1165. ulpi_data0_po1 {
  1166. nvidia,pins = "ulpi_data0_po1";
  1167. nvidia,function = "safe";
  1168. nvidia,enable-input = <0x0>;
  1169. nvidia,pull = <0x1>;
  1170. nvidia,tristate = <0x1>;
  1171. };
  1172.  
  1173. ulpi_data1_po2 {
  1174. nvidia,pins = "ulpi_data1_po2";
  1175. nvidia,function = "safe";
  1176. nvidia,enable-input = <0x0>;
  1177. nvidia,pull = <0x1>;
  1178. nvidia,tristate = <0x1>;
  1179. };
  1180.  
  1181. ulpi_data2_po3 {
  1182. nvidia,pins = "ulpi_data2_po3";
  1183. nvidia,function = "safe";
  1184. nvidia,enable-input = <0x0>;
  1185. nvidia,pull = <0x1>;
  1186. nvidia,tristate = <0x1>;
  1187. };
  1188.  
  1189. ulpi_data3_po4 {
  1190. nvidia,pins = "ulpi_data3_po4";
  1191. nvidia,function = "safe";
  1192. nvidia,enable-input = <0x0>;
  1193. nvidia,pull = <0x1>;
  1194. nvidia,tristate = <0x1>;
  1195. };
  1196.  
  1197. ulpi_data6_po7 {
  1198. nvidia,pins = "ulpi_data6_po7";
  1199. nvidia,function = "safe";
  1200. nvidia,enable-input = <0x0>;
  1201. nvidia,pull = <0x1>;
  1202. nvidia,tristate = <0x1>;
  1203. };
  1204.  
  1205. ulpi_data7_po0 {
  1206. nvidia,pins = "ulpi_data7_po0";
  1207. nvidia,function = "safe";
  1208. nvidia,enable-input = <0x0>;
  1209. nvidia,pull = <0x1>;
  1210. nvidia,tristate = <0x1>;
  1211. };
  1212.  
  1213. pbb4 {
  1214. nvidia,pins = "pbb4";
  1215. nvidia,function = "safe";
  1216. nvidia,enable-input = <0x0>;
  1217. nvidia,pull = <0x1>;
  1218. nvidia,tristate = <0x1>;
  1219. };
  1220.  
  1221. pcc1 {
  1222. nvidia,pins = "pcc1";
  1223. nvidia,function = "safe";
  1224. nvidia,enable-input = <0x0>;
  1225. nvidia,pull = <0x1>;
  1226. nvidia,tristate = <0x1>;
  1227. };
  1228.  
  1229. pcc2 {
  1230. nvidia,pins = "pcc2";
  1231. nvidia,function = "safe";
  1232. nvidia,enable-input = <0x0>;
  1233. nvidia,pull = <0x1>;
  1234. nvidia,tristate = <0x1>;
  1235. };
  1236.  
  1237. pg0 {
  1238. nvidia,pins = "pg0";
  1239. nvidia,function = "safe";
  1240. nvidia,enable-input = <0x0>;
  1241. nvidia,pull = <0x1>;
  1242. nvidia,tristate = <0x1>;
  1243. };
  1244.  
  1245. pg1 {
  1246. nvidia,pins = "pg1";
  1247. nvidia,function = "safe";
  1248. nvidia,enable-input = <0x0>;
  1249. nvidia,pull = <0x1>;
  1250. nvidia,tristate = <0x1>;
  1251. };
  1252.  
  1253. ph6 {
  1254. nvidia,pins = "ph6";
  1255. nvidia,function = "safe";
  1256. nvidia,enable-input = <0x0>;
  1257. nvidia,pull = <0x1>;
  1258. nvidia,tristate = <0x1>;
  1259. };
  1260.  
  1261. ph7 {
  1262. nvidia,pins = "ph7";
  1263. nvidia,function = "safe";
  1264. nvidia,enable-input = <0x0>;
  1265. nvidia,pull = <0x1>;
  1266. nvidia,tristate = <0x1>;
  1267. };
  1268.  
  1269. pg2 {
  1270. nvidia,pins = "pg2";
  1271. nvidia,function = "safe";
  1272. nvidia,enable-input = <0x0>;
  1273. nvidia,pull = <0x1>;
  1274. nvidia,tristate = <0x1>;
  1275. };
  1276.  
  1277. pg3 {
  1278. nvidia,pins = "pg3";
  1279. nvidia,function = "safe";
  1280. nvidia,enable-input = <0x0>;
  1281. nvidia,pull = <0x1>;
  1282. nvidia,tristate = <0x1>;
  1283. };
  1284.  
  1285. pg4 {
  1286. nvidia,pins = "pg4";
  1287. nvidia,function = "safe";
  1288. nvidia,enable-input = <0x0>;
  1289. nvidia,pull = <0x1>;
  1290. nvidia,tristate = <0x1>;
  1291. };
  1292.  
  1293. pg5 {
  1294. nvidia,pins = "pg5";
  1295. nvidia,function = "safe";
  1296. nvidia,enable-input = <0x0>;
  1297. nvidia,pull = <0x1>;
  1298. nvidia,tristate = <0x1>;
  1299. };
  1300.  
  1301. pg6 {
  1302. nvidia,pins = "pg6";
  1303. nvidia,function = "safe";
  1304. nvidia,enable-input = <0x0>;
  1305. nvidia,pull = <0x1>;
  1306. nvidia,tristate = <0x1>;
  1307. };
  1308.  
  1309. pg7 {
  1310. nvidia,pins = "pg7";
  1311. nvidia,function = "safe";
  1312. nvidia,enable-input = <0x0>;
  1313. nvidia,pull = <0x1>;
  1314. nvidia,tristate = <0x1>;
  1315. };
  1316.  
  1317. ph0 {
  1318. nvidia,pins = "ph0";
  1319. nvidia,function = "safe";
  1320. nvidia,enable-input = <0x0>;
  1321. nvidia,pull = <0x1>;
  1322. nvidia,tristate = <0x1>;
  1323. };
  1324.  
  1325. pk3 {
  1326. nvidia,pins = "pk3";
  1327. nvidia,function = "safe";
  1328. nvidia,enable-input = <0x0>;
  1329. nvidia,pull = <0x1>;
  1330. nvidia,tristate = <0x1>;
  1331. };
  1332.  
  1333. pi3 {
  1334. nvidia,pins = "pi3";
  1335. nvidia,function = "safe";
  1336. nvidia,enable-input = <0x0>;
  1337. nvidia,pull = <0x1>;
  1338. nvidia,tristate = <0x1>;
  1339. };
  1340.  
  1341. pi2 {
  1342. nvidia,pins = "pi2";
  1343. nvidia,function = "safe";
  1344. nvidia,enable-input = <0x0>;
  1345. nvidia,pull = <0x0>;
  1346. nvidia,tristate = <0x0>;
  1347. };
  1348.  
  1349. pi5 {
  1350. nvidia,pins = "pi5";
  1351. nvidia,function = "safe";
  1352. nvidia,enable-input = <0x0>;
  1353. nvidia,pull = <0x1>;
  1354. nvidia,tristate = <0x1>;
  1355. };
  1356.  
  1357. pi4 {
  1358. nvidia,pins = "pi4";
  1359. nvidia,function = "safe";
  1360. nvidia,enable-input = <0x0>;
  1361. nvidia,pull = <0x1>;
  1362. nvidia,tristate = <0x1>;
  1363. };
  1364.  
  1365. pi7 {
  1366. nvidia,pins = "pi7";
  1367. nvidia,function = "safe";
  1368. nvidia,enable-input = <0x0>;
  1369. nvidia,pull = <0x1>;
  1370. nvidia,tristate = <0x1>;
  1371. };
  1372.  
  1373. pex_l0_clkreq_n_pdd2 {
  1374. nvidia,pins = "pex_l0_clkreq_n_pdd2";
  1375. nvidia,function = "safe";
  1376. nvidia,enable-input = <0x0>;
  1377. nvidia,pull = <0x1>;
  1378. nvidia,tristate = <0x1>;
  1379. };
  1380.  
  1381. pex_l0_rst_n_pdd1 {
  1382. nvidia,pins = "pex_l0_rst_n_pdd1";
  1383. nvidia,function = "safe";
  1384. nvidia,enable-input = <0x0>;
  1385. nvidia,pull = <0x1>;
  1386. nvidia,tristate = <0x1>;
  1387. };
  1388.  
  1389. pex_l1_clkreq_n_pdd6 {
  1390. nvidia,pins = "pex_l1_clkreq_n_pdd6";
  1391. nvidia,function = "safe";
  1392. nvidia,enable-input = <0x0>;
  1393. nvidia,pull = <0x1>;
  1394. nvidia,tristate = <0x1>;
  1395. };
  1396.  
  1397. pex_l1_rst_n_pdd5 {
  1398. nvidia,pins = "pex_l1_rst_n_pdd5";
  1399. nvidia,function = "safe";
  1400. nvidia,enable-input = <0x0>;
  1401. nvidia,pull = <0x1>;
  1402. nvidia,tristate = <0x1>;
  1403. };
  1404.  
  1405. pex_wake_n_pdd3 {
  1406. nvidia,pins = "pex_wake_n_pdd3";
  1407. nvidia,function = "safe";
  1408. nvidia,enable-input = <0x0>;
  1409. nvidia,pull = <0x1>;
  1410. nvidia,tristate = <0x1>;
  1411. };
  1412.  
  1413. usb_vbus_en2_pff1 {
  1414. nvidia,pins = "usb_vbus_en2_pff1";
  1415. nvidia,function = "safe";
  1416. nvidia,enable-input = <0x0>;
  1417. nvidia,pull = <0x1>;
  1418. nvidia,tristate = <0x1>;
  1419. };
  1420.  
  1421. pff2 {
  1422. nvidia,pins = "pff2";
  1423. nvidia,function = "safe";
  1424. nvidia,enable-input = <0x0>;
  1425. nvidia,pull = <0x1>;
  1426. nvidia,tristate = <0x1>;
  1427. };
  1428.  
  1429. clk2_out_pw5 {
  1430. nvidia,pins = "clk2_out_pw5";
  1431. nvidia,function = "safe";
  1432. nvidia,enable-input = <0x0>;
  1433. nvidia,pull = <0x1>;
  1434. nvidia,tristate = <0x1>;
  1435. };
  1436.  
  1437. clk2_req_pcc5 {
  1438. nvidia,pins = "clk2_req_pcc5";
  1439. nvidia,function = "safe";
  1440. nvidia,enable-input = <0x0>;
  1441. nvidia,pull = <0x1>;
  1442. nvidia,tristate = <0x1>;
  1443. };
  1444.  
  1445. sdmmc1_wp_n_pv3 {
  1446. nvidia,pins = "sdmmc1_wp_n_pv3";
  1447. nvidia,function = "safe";
  1448. nvidia,enable-input = <0x0>;
  1449. nvidia,pull = <0x1>;
  1450. nvidia,tristate = <0x1>;
  1451. };
  1452.  
  1453. kb_col1_pq1 {
  1454. nvidia,pins = "kb_col1_pq1";
  1455. nvidia,function = "safe";
  1456. nvidia,enable-input = <0x0>;
  1457. nvidia,pull = <0x1>;
  1458. nvidia,tristate = <0x1>;
  1459. };
  1460.  
  1461. kb_col2_pq2 {
  1462. nvidia,pins = "kb_col2_pq2";
  1463. nvidia,function = "safe";
  1464. nvidia,enable-input = <0x0>;
  1465. nvidia,pull = <0x1>;
  1466. nvidia,tristate = <0x1>;
  1467. };
  1468.  
  1469. kb_col3_pq3 {
  1470. nvidia,pins = "kb_col3_pq3";
  1471. nvidia,function = "safe";
  1472. nvidia,enable-input = <0x0>;
  1473. nvidia,pull = <0x1>;
  1474. nvidia,tristate = <0x1>;
  1475. };
  1476.  
  1477. kb_col4_pq4 {
  1478. nvidia,pins = "kb_col4_pq4";
  1479. nvidia,function = "safe";
  1480. nvidia,enable-input = <0x0>;
  1481. nvidia,pull = <0x1>;
  1482. nvidia,tristate = <0x1>;
  1483. };
  1484.  
  1485. kb_row10_ps2 {
  1486. nvidia,pins = "kb_row10_ps2";
  1487. nvidia,function = "safe";
  1488. nvidia,enable-input = <0x0>;
  1489. nvidia,pull = <0x1>;
  1490. nvidia,tristate = <0x1>;
  1491. };
  1492.  
  1493. kb_row13_ps5 {
  1494. nvidia,pins = "kb_row13_ps5";
  1495. nvidia,function = "safe";
  1496. nvidia,enable-input = <0x0>;
  1497. nvidia,pull = <0x1>;
  1498. nvidia,tristate = <0x1>;
  1499. };
  1500.  
  1501. kb_row14_ps6 {
  1502. nvidia,pins = "kb_row14_ps6";
  1503. nvidia,function = "safe";
  1504. nvidia,enable-input = <0x0>;
  1505. nvidia,pull = <0x1>;
  1506. nvidia,tristate = <0x1>;
  1507. };
  1508.  
  1509. kb_row15_ps7 {
  1510. nvidia,pins = "kb_row15_ps7";
  1511. nvidia,function = "soc";
  1512. nvidia,enable-input = <0x1>;
  1513. nvidia,pull = <0x2>;
  1514. nvidia,tristate = <0x0>;
  1515. };
  1516.  
  1517. kb_row16_pt0 {
  1518. nvidia,pins = "kb_row16_pt0";
  1519. nvidia,function = "safe";
  1520. nvidia,enable-input = <0x0>;
  1521. nvidia,pull = <0x1>;
  1522. nvidia,tristate = <0x1>;
  1523. };
  1524.  
  1525. kb_row17_pt1 {
  1526. nvidia,pins = "kb_row17_pt1";
  1527. nvidia,function = "safe";
  1528. nvidia,enable-input = <0x0>;
  1529. nvidia,pull = <0x1>;
  1530. nvidia,tristate = <0x1>;
  1531. };
  1532.  
  1533. kb_row3_pr3 {
  1534. nvidia,pins = "kb_row3_pr3";
  1535. nvidia,function = "safe";
  1536. nvidia,enable-input = <0x0>;
  1537. nvidia,pull = <0x1>;
  1538. nvidia,tristate = <0x1>;
  1539. };
  1540.  
  1541. kb_row6_pr6 {
  1542. nvidia,pins = "kb_row6_pr6";
  1543. nvidia,function = "safe";
  1544. nvidia,enable-input = <0x0>;
  1545. nvidia,pull = <0x1>;
  1546. nvidia,tristate = <0x1>;
  1547. };
  1548.  
  1549. kb_row7_pr7 {
  1550. nvidia,pins = "kb_row7_pr7";
  1551. nvidia,function = "safe";
  1552. nvidia,enable-input = <0x0>;
  1553. nvidia,pull = <0x1>;
  1554. nvidia,tristate = <0x1>;
  1555. };
  1556.  
  1557. kb_row9_ps1 {
  1558. nvidia,pins = "kb_row9_ps1";
  1559. nvidia,function = "safe";
  1560. nvidia,enable-input = <0x0>;
  1561. nvidia,pull = <0x1>;
  1562. nvidia,tristate = <0x1>;
  1563. };
  1564.  
  1565. clk3_out_pee0 {
  1566. nvidia,pins = "clk3_out_pee0";
  1567. nvidia,function = "safe";
  1568. nvidia,enable-input = <0x0>;
  1569. nvidia,pull = <0x1>;
  1570. nvidia,tristate = <0x1>;
  1571. };
  1572.  
  1573. pu0 {
  1574. nvidia,pins = "pu0";
  1575. nvidia,function = "safe";
  1576. nvidia,enable-input = <0x0>;
  1577. nvidia,pull = <0x1>;
  1578. nvidia,tristate = <0x1>;
  1579. };
  1580.  
  1581. pu1 {
  1582. nvidia,pins = "pu1";
  1583. nvidia,function = "safe";
  1584. nvidia,enable-input = <0x0>;
  1585. nvidia,pull = <0x1>;
  1586. nvidia,tristate = <0x1>;
  1587. };
  1588.  
  1589. pu2 {
  1590. nvidia,pins = "pu2";
  1591. nvidia,function = "safe";
  1592. nvidia,enable-input = <0x0>;
  1593. nvidia,pull = <0x1>;
  1594. nvidia,tristate = <0x1>;
  1595. };
  1596.  
  1597. pu3 {
  1598. nvidia,pins = "pu3";
  1599. nvidia,function = "safe";
  1600. nvidia,enable-input = <0x0>;
  1601. nvidia,pull = <0x1>;
  1602. nvidia,tristate = <0x1>;
  1603. };
  1604.  
  1605. pu4 {
  1606. nvidia,pins = "pu4";
  1607. nvidia,function = "safe";
  1608. nvidia,enable-input = <0x1>;
  1609. nvidia,pull = <0x1>;
  1610. nvidia,tristate = <0x1>;
  1611. };
  1612.  
  1613. owr {
  1614. nvidia,pins = "owr";
  1615. nvidia,function = "safe";
  1616. nvidia,enable-input = <0x0>;
  1617. nvidia,pull = <0x1>;
  1618. nvidia,tristate = <0x1>;
  1619. };
  1620.  
  1621. dp_hpd_pff0 {
  1622. nvidia,pins = "dp_hpd_pff0";
  1623. nvidia,function = "safe";
  1624. nvidia,enable-input = <0x0>;
  1625. nvidia,pull = <0x1>;
  1626. nvidia,tristate = <0x1>;
  1627. };
  1628. };
  1629.  
  1630. drive {
  1631. linux,phandle = <0x4>;
  1632. phandle = <0x4>;
  1633.  
  1634. drive_sdio1 {
  1635. nvidia,pins = "drive_sdio1";
  1636. nvidia,high-speed-mode = <0x1>;
  1637. nvidia,schmitt = <0x0>;
  1638. nvidia,pull-down-strength = <0x20>;
  1639. nvidia,pull-up-strength = <0x2a>;
  1640. nvidia,slew-rate-rising = <0x0>;
  1641. nvidia,slew-rate-falling = <0x0>;
  1642. };
  1643.  
  1644. drive_sdio3 {
  1645. nvidia,pins = "drive_sdio3";
  1646. nvidia,high-speed-mode = <0x1>;
  1647. nvidia,schmitt = <0x0>;
  1648. nvidia,pull-down-strength = <0x14>;
  1649. nvidia,pull-up-strength = <0x24>;
  1650. nvidia,slew-rate-rising = <0x0>;
  1651. nvidia,slew-rate-falling = <0x0>;
  1652. };
  1653.  
  1654. drive_gma {
  1655. nvidia,pins = "drive_gma";
  1656. nvidia,high-speed-mode = <0x1>;
  1657. nvidia,schmitt = <0x0>;
  1658. nvidia,low-power-mode = <0x3>;
  1659. nvidia,pull-down-strength = <0x1>;
  1660. nvidia,pull-up-strength = <0x2>;
  1661. nvidia,slew-rate-rising = <0x0>;
  1662. nvidia,slew-rate-falling = <0x0>;
  1663. nvidia,drive-type = <0x1>;
  1664. };
  1665. };
  1666. };
  1667.  
  1668. serial@70006000 {
  1669. compatible = "nvidia,tegra114-hsuart";
  1670. reg = <0x0 0x70006000 0x0 0x40>;
  1671. reg-shift = <0x2>;
  1672. interrupts = <0x0 0x24 0x4>;
  1673. nvidia,dma-request-selector = <0x6 0x8>;
  1674. nvidia,memory-clients = <0xe>;
  1675. status = "okay";
  1676. };
  1677.  
  1678. serial@70006040 {
  1679. compatible = "nvidia,tegra114-hsuart";
  1680. reg = <0x0 0x70006040 0x0 0x40>;
  1681. reg-shift = <0x2>;
  1682. interrupts = <0x0 0x25 0x4>;
  1683. nvidia,dma-request-selector = <0x6 0x9>;
  1684. nvidia,memory-clients = <0xe>;
  1685. status = "okay";
  1686. };
  1687.  
  1688. serial@70006200 {
  1689. compatible = "nvidia,tegra114-hsuart";
  1690. reg = <0x0 0x70006200 0x0 0x40>;
  1691. reg-shift = <0x2>;
  1692. interrupts = <0x0 0x2e 0x4>;
  1693. nvidia,dma-request-selector = <0x6 0xa>;
  1694. nvidia,memory-clients = <0xe>;
  1695. status = "okay";
  1696. };
  1697.  
  1698. serial@70006300 {
  1699. compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  1700. reg = <0x0 0x70006300 0x0 0x40>;
  1701. reg-shift = <0x2>;
  1702. interrupts = <0x0 0x5a 0x4>;
  1703. nvidia,dma-request-selector = <0x6 0x13>;
  1704. nvidia,memory-clients = <0xe>;
  1705. status = "disabled";
  1706. };
  1707.  
  1708. pwm@7000a000 {
  1709. compatible = "nvidia,tegra124-pwm";
  1710. reg = <0x0 0x7000a000 0x0 0x100>;
  1711. #pwm-cells = <0x2>;
  1712. status = "okay";
  1713. };
  1714.  
  1715. i2c@7000c000 {
  1716. #address-cells = <0x1>;
  1717. #size-cells = <0x0>;
  1718. compatible = "nvidia,tegra124-i2c";
  1719. reg = <0x0 0x7000c000 0x0 0x100>;
  1720. interrupts = <0x0 0x26 0x4>;
  1721. scl-gpio = <0x7 0x14 0x0>;
  1722. sda-gpio = <0x7 0x15 0x0>;
  1723. nvidia,memory-clients = <0xe>;
  1724. status = "okay";
  1725. clock-frequency = <0x61a80>;
  1726.  
  1727. mpu6515@69 {
  1728. compatible = "invensense,mpu6515";
  1729. reg = <0x69>;
  1730. interrupt-parent = <0x7>;
  1731. interrupts = <0x90 0x1>;
  1732. invensense,int_config = <0x10>;
  1733. invensense,level_shifter = <0x0>;
  1734. invensense,orientation = [ff 00 00 00 01 00 00 00 ff];
  1735. invensense,sec_slave_type = <0x0>;
  1736. invensense,key = <0x4ecc7eeb 0xf61e3522 0x340d65 0x32e99489>;
  1737. vlogic-supply = <0x8>;
  1738. vdd-supply = <0x9>;
  1739. };
  1740.  
  1741. ak8963c@0d {
  1742. compatible = "ak,ak8963";
  1743. reg = <0xd>;
  1744. orientation = [ff 00 00 00 01 00 00 00 ff];
  1745. config = "mpu";
  1746. vid-supply = <0x8>;
  1747. vdd-supply = <0x9>;
  1748. };
  1749.  
  1750. cm3217@10 {
  1751. compatible = "capella,cm3217";
  1752. reg = <0x10>;
  1753. vdd-supply = <0x9>;
  1754. illuminance,resolution = "8740";
  1755. illuminance,max-range = "681613.7";
  1756. illuminance,power-consumed = "0.09";
  1757. };
  1758.  
  1759. ltr659@23 {
  1760. compatible = "lite-on,ltr659";
  1761. reg = <0x23>;
  1762. threshold = <0x50>;
  1763. vdd-supply = <0x9>;
  1764. vled-supply = <0x8>;
  1765. };
  1766. };
  1767.  
  1768. i2c@7000c400 {
  1769. #address-cells = <0x1>;
  1770. #size-cells = <0x0>;
  1771. compatible = "nvidia,tegra124-i2c";
  1772. reg = <0x0 0x7000c400 0x0 0x100>;
  1773. interrupts = <0x0 0x54 0x4>;
  1774. scl-gpio = <0x7 0x9d 0x0>;
  1775. sda-gpio = <0x7 0x9e 0x0>;
  1776. nvidia,memory-clients = <0xe>;
  1777. status = "okay";
  1778. clock-frequency = <0x186a0>;
  1779.  
  1780. max17048@36 {
  1781. compatible = "maxim,max17048";
  1782. reg = <0x36>;
  1783. status = "disabled";
  1784. interrupt-parent = <0x7>;
  1785. interrupts = <0x85 0x0>;
  1786. tz-name = "battery-temp";
  1787. alert-threshold = <0x0>;
  1788. one-percent-alerts = <0x1>;
  1789. valert-max = <0x13ec>;
  1790. valert-min = <0x0>;
  1791. vreset-threshold = <0x960>;
  1792. vreset-disable = <0x1>;
  1793. hib-threshold = <0x30>;
  1794. hib-active-threshold = <0x80>;
  1795. bits = <0x12>;
  1796. rcomp = <0x39>;
  1797. rcomp-seg = <0x200>;
  1798. soccheck-a = <0x77>;
  1799. soccheck-b = <0x79>;
  1800. ocvtest = <0xda90>;
  1801. data-tbl = <0x98 0x80 0xb3 0x50 0xb7 0x90 0xb9 0x0 0xba 0x70 0xbc 0x10 0xbc 0x50 0xbc 0xa0 0xbd 0x20 0xbe 0x30 0xbf 0x40 0xc2 0xf0 0xc4 0x20 0xc7 0xe0 0xcb 0xf0 0xd0 0x90 0x0 0x40 0x6 0x70 0xe 0x50 0x12 0x0 0x18 0xd0 0x33 0x10 0x31 0x40 0x35 0xd0 0x18 0xd0 0x19 0x0 0xb 0xf0 0xc 0x10 0xd 0x10 0x7 0x90 0x8 0x0 0x8 0x0>;
  1802. };
  1803.  
  1804. lc709203f@0b {
  1805. compatible = "onsemi,lc709203f";
  1806. reg = <0xb>;
  1807. interrupt-parent = <0x7>;
  1808. interrupts = <0x85 0x0>;
  1809. onsemi,thermistor-beta = <0xd6b>;
  1810. onsemi,kernel-maximum-soc = <0x63>;
  1811. onsemi,alert-low-rsoc = <0x0>;
  1812. onsemi,alert-low-voltage = <0x0>;
  1813. status = "okay";
  1814. onsemi,kernel-threshold-soc = <0x2>;
  1815. io-channels = <0xa 0x1>;
  1816. io-channel-names = "battery-current";
  1817. };
  1818.  
  1819. hpa2163@6b {
  1820. compatible = "ti,bq2419x";
  1821. reg = <0x6b>;
  1822. interrupt-parent = <0x7>;
  1823. interrupts = <0x48 0x0>;
  1824.  
  1825. charger {
  1826. status = "okay";
  1827. regulator-name = "batt_regulator";
  1828. regulator-max-microamp = <0x2dc6c0>;
  1829. ti,watchdog-timeout = <0x28>;
  1830. ti,rtc-alarm-time = <0xe10>;
  1831. ti,auto-recharge-time = <0x708>;
  1832. ti,disbale-suspend-during-charging;
  1833. ti,charge-voltage-limit-millivolt = <0x1100>;
  1834. ti,charge-term-current-limit-milliamp = <0x1>;
  1835. ti,temp-range = <0xa 0xf 0x19 0x2d 0x3c>;
  1836. ti,charge-current-limit = <0x410 0x410 0xa28 0x1450 0xa28>;
  1837. ti,thermal-zone = "battery";
  1838. ti,temp-polling-time-sec = <0x5>;
  1839. ti,ir-comp-voltage-millivolt = <0x1>;
  1840. ti,ir-comp-resister-ohm = <0x46>;
  1841. ti,auto-recharge-time-power-off = <0xe10>;
  1842. ti,auto-recharge-time-suspend = <0xe10>;
  1843. ti,charge-thermal-voltage-limit = <0x1100 0x1100 0x1100 0x1100 0x1068>;
  1844. ti,soc-range = <0x32 0x3c 0x46 0x50 0x55 0x5a 0x5f 0x65>;
  1845. ti,input-voltage-soc-limit = <0x1068 0x10b8 0x1108 0x1158 0x11a8 0x11f8 0x1248 0x1298>;
  1846.  
  1847. consumers {
  1848.  
  1849. c1 {
  1850. regulator-consumer-supply = "usb_bat_chg";
  1851. regulator-consumer-device = "tegra-udc.0";
  1852. };
  1853.  
  1854. c2 {
  1855. regulator-consumer-supply = "usb_bat_chg";
  1856. regulator-consumer-device = "tegra-otg";
  1857. };
  1858. };
  1859. };
  1860.  
  1861. vbus {
  1862. regulator-name = "vbus_regulator";
  1863. ti,otg-iusb-gpio = <0x7 0x44 0x0>;
  1864.  
  1865. consumers {
  1866.  
  1867. c1 {
  1868. regulator-consumer-supply = "usb_vbus";
  1869. regulator-consumer-device = "tegra-ehci.0";
  1870. };
  1871.  
  1872. c2 {
  1873. regulator-consumer-supply = "usb_vbus";
  1874. regulator-consumer-device = "tegra-otg";
  1875. };
  1876. };
  1877. };
  1878. };
  1879.  
  1880. iqs253@44 {
  1881. compatible = "azoteq,iqs253";
  1882. reg = <0x44>;
  1883. vddhi-supply = <0x9>;
  1884. vendor = "Azoteq";
  1885. proximity,max-range = [32 00];
  1886. proximity,integration-time = "16000000";
  1887. proximity,power-consumed = "1.67";
  1888. rdy-gpio = <0x7 0x55 0x1>;
  1889. wake-gpio = <0x7 0xb3 0x1>;
  1890. sar-gpio = <0x7 0x42 0x1>;
  1891. };
  1892.  
  1893. ina3221x@40 {
  1894. compatible = "ti,ina3221x";
  1895. reg = <0x40>;
  1896. ti,trigger-config = <0x7203>;
  1897. ti,continuous-config = <0x7c07>;
  1898. #address-cells = <0x1>;
  1899. #size-cells = <0x0>;
  1900. #io-channel-cells = <0x1>;
  1901. linux,phandle = <0xa>;
  1902. phandle = <0xa>;
  1903.  
  1904. channel@0 {
  1905. reg = <0x0>;
  1906. ti,rail-name = "VDD_BAT";
  1907. ti,current-warning-limit-ma = <0x1f40>;
  1908. ti,current-critical-limit-ma = <0x2328>;
  1909. ti,shunt-resistor-mohm = <0x1>;
  1910. };
  1911.  
  1912. channel@1 {
  1913. reg = <0x1>;
  1914. ti,rail-name = "VDD_USB_5V0";
  1915. ti,shunt-resistor-mohm = <0xa>;
  1916. };
  1917.  
  1918. channel@2 {
  1919. reg = <0x2>;
  1920. ti,rail-name = "VDD_SYS_MDM";
  1921. ti,shunt-resistor-mohm = <0x1>;
  1922. };
  1923. };
  1924. };
  1925.  
  1926. i2c@7000c500 {
  1927. #address-cells = <0x1>;
  1928. #size-cells = <0x0>;
  1929. compatible = "nvidia,tegra124-i2c";
  1930. reg = <0x0 0x7000c500 0x0 0x100>;
  1931. interrupts = <0x0 0x5c 0x4>;
  1932. scl-gpio = <0x7 0xd9 0x0>;
  1933. sda-gpio = <0x7 0xda 0x0>;
  1934. nvidia,memory-clients = <0xe>;
  1935. status = "okay";
  1936. clock-frequency = <0x61a80>;
  1937. };
  1938.  
  1939. i2c@7000c700 {
  1940. #address-cells = <0x1>;
  1941. #size-cells = <0x0>;
  1942. compatible = "nvidia,tegra124-i2c";
  1943. reg = <0x0 0x7000c700 0x0 0x100>;
  1944. interrupts = <0x0 0x78 0x4>;
  1945. scl-gpio = <0x7 0xac 0x0>;
  1946. sda-gpio = <0x7 0xad 0x0>;
  1947. nvidia,memory-clients = <0xe>;
  1948. status = "okay";
  1949. clock-frequency = <0x186a0>;
  1950. };
  1951.  
  1952. i2c@7000d000 {
  1953. #address-cells = <0x1>;
  1954. #size-cells = <0x0>;
  1955. compatible = "nvidia,tegra124-i2c";
  1956. reg = <0x0 0x7000d000 0x0 0x100>;
  1957. interrupts = <0x0 0x35 0x4>;
  1958. nvidia,require-cldvfs-clock;
  1959. scl-gpio = <0x7 0xce 0x0>;
  1960. sda-gpio = <0x7 0xcf 0x0>;
  1961. nvidia,memory-clients = <0xe>;
  1962. status = "okay";
  1963. clock-frequency = <0x61a80>;
  1964. nvidia,bit-banging-xfer-after-shutdown;
  1965.  
  1966. tps65913 {
  1967. compatible = "ti,palmas";
  1968. reg = <0x58>;
  1969. interrupts = <0x0 0x56 0x0>;
  1970. #interrupt-cells = <0x2>;
  1971. interrupt-controller;
  1972. linux,phandle = <0xb>;
  1973. phandle = <0xb>;
  1974.  
  1975. gpio {
  1976. compatible = "ti,palmas-gpio";
  1977. gpio-controller;
  1978. #gpio-cells = <0x2>;
  1979. linux,phandle = <0x17>;
  1980. phandle = <0x17>;
  1981. };
  1982.  
  1983. rtc {
  1984. compatible = "ti,palmas-rtc";
  1985. interrupt-parent = <0xb>;
  1986. interrupts = <0x8 0x0>;
  1987. };
  1988.  
  1989. pinmux {
  1990. compatible = "ti,tps65913-pinctrl";
  1991. pinctrl-names = "default";
  1992. pinctrl-0 = <0xc>;
  1993.  
  1994. pinmux {
  1995. linux,phandle = <0xc>;
  1996. phandle = <0xc>;
  1997.  
  1998. powergood {
  1999. pins = "powergood";
  2000. function = "powergood";
  2001. };
  2002.  
  2003. vac {
  2004. pins = "vac";
  2005. function = "vac";
  2006. };
  2007.  
  2008. pin_gpio0 {
  2009. pins = "gpio0";
  2010. function = "id";
  2011. bias-pull-up;
  2012. };
  2013.  
  2014. pin_gpio1 {
  2015. pins = "gpio1";
  2016. function = "gpio";
  2017. bias-disable;
  2018. };
  2019.  
  2020. pin_gpio6 {
  2021. pins = "gpio2", "gpio3", "gpio4", "gpio6", "gpio7";
  2022. function = "gpio";
  2023. };
  2024.  
  2025. pin_gpio5 {
  2026. pins = "gpio5";
  2027. function = "clk32kgaudio";
  2028. };
  2029. };
  2030. };
  2031.  
  2032. extcon {
  2033. compatible = "ti,palmas-usb";
  2034. extcon-name = "palmas-extcon";
  2035. ti,wakeup;
  2036. ti,enable-id-detection;
  2037. ti,enable-vbus-detection;
  2038. };
  2039.  
  2040. watchdog {
  2041. compatible = "ti,palmas-watchdog";
  2042. ti,system-watchdog-timer-period = <0x40>;
  2043. status = "disabled";
  2044. };
  2045.  
  2046. power_pm {
  2047. compatible = "ti,palmas-pm";
  2048. system-pmic-power-off;
  2049. };
  2050.  
  2051. palmas_ldousb_in {
  2052. compatible = "ti,palmas-ldousb-in";
  2053. ti,ldousb-in-threshold-voltage = <0x3567e0>;
  2054. ti,threshold-voltage-tolerance = <0x186a0>;
  2055. ti,enable-in1-above-threshold;
  2056. ldousb-in1-supply = <0xd>;
  2057. ldousb-in2-supply = <0xe>;
  2058. };
  2059.  
  2060. gpadc {
  2061. compatible = "ti,palmas-gpadc";
  2062. interrupt-parent = <0xb>;
  2063. interrupts = <0x12 0x0 0x10 0x0 0x11 0x0>;
  2064. ti,channel0-current-microamp = <0x5>;
  2065. ti,channel3-current-microamp = <0x190>;
  2066. ti,enable-channel3-dual-current;
  2067. ti,enable-extended-delay;
  2068. ti,auto-conversion-period-ms = <0x1f4>;
  2069.  
  2070. iio_map {
  2071.  
  2072. ch0 {
  2073. ti,adc-channel-number = <0x0>;
  2074. ti,adc-consumer-device = "1-000b";
  2075. ti,adc-consumer-channel = "batt_id";
  2076. };
  2077.  
  2078. ch1 {
  2079. ti,adc-channel-number = <0x1>;
  2080. ti,adc-consumer-device = "generic-adc-thermal.1";
  2081. ti,adc-consumer-channel = "thermistor";
  2082. };
  2083.  
  2084. ch3 {
  2085. ti,adc-channel-number = <0x3>;
  2086. ti,adc-consumer-device = "generic-adc-thermal.2";
  2087. ti,adc-consumer-channel = "tdiode";
  2088. };
  2089.  
  2090. ch5 {
  2091. ti,adc-channel-number = <0x5>;
  2092. ti,adc-consumer-device = "generic-adc-thermal.0";
  2093. ti,adc-consumer-channel = "battery-temp-channel";
  2094. };
  2095. };
  2096.  
  2097. auto_conv0 {
  2098. ti,adc-channel-number = <0x3>;
  2099. ti,adc-low-threshold = <0x7bc>;
  2100. ti,enable-shutdown;
  2101. };
  2102. };
  2103.  
  2104. clock {
  2105. compatible = "ti,palmas-clk";
  2106.  
  2107. clk32k_kg {
  2108. ti,clock-boot-enable;
  2109. };
  2110.  
  2111. clk32k_kg_audio {
  2112. ti,clock-boot-enable;
  2113. };
  2114. };
  2115.  
  2116. pmic {
  2117. compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
  2118. ldo1-in-supply = <0xf>;
  2119. ldo5-in-supply = <0x8>;
  2120. ldo9-in-supply = <0x9>;
  2121. ldoln-in-supply = <0xe>;
  2122. ldousb-in-supply = <0xe>;
  2123.  
  2124. regulators {
  2125.  
  2126. smps123 {
  2127. regulator-name = "vdd-cpu";
  2128. regulator-min-microvolt = <0xaae60>;
  2129. regulator-max-microvolt = <0x155cc0>;
  2130. regulator-always-on;
  2131. regulator-boot-on;
  2132. ti,roof-floor = <0x1>;
  2133. ti,config-flags = <0x8>;
  2134.  
  2135. consumers {
  2136.  
  2137. c1 {
  2138. regulator-consumer-supply = "vdd_cpu";
  2139. };
  2140. };
  2141. };
  2142.  
  2143. smps45 {
  2144. regulator-name = "vdd-gpu";
  2145. regulator-min-microvolt = <0xaae60>;
  2146. regulator-max-microvolt = <0x155cc0>;
  2147. regulator-init-microvolt = <0xf4240>;
  2148. regulator-boot-on;
  2149.  
  2150. consumers {
  2151.  
  2152. c1 {
  2153. regulator-consumer-supply = "vdd_gpu";
  2154. };
  2155. };
  2156. };
  2157.  
  2158. smps6 {
  2159. regulator-name = "vddio-ddr";
  2160. regulator-always-on;
  2161. regulator-boot-on;
  2162. linux,phandle = <0xf>;
  2163. phandle = <0xf>;
  2164.  
  2165. consumers {
  2166.  
  2167. c1 {
  2168. regulator-consumer-supply = "vddio_ddr";
  2169. };
  2170.  
  2171. c2 {
  2172. regulator-consumer-supply = "vddio_ddr_mclk";
  2173. };
  2174.  
  2175. c3 {
  2176. regulator-consumer-supply = "vddio_ddr3";
  2177. };
  2178.  
  2179. c4 {
  2180. regulator-consumer-supply = "vcore1_ddr3";
  2181. };
  2182. };
  2183. };
  2184.  
  2185. smps7 {
  2186. regulator-name = "vdd-core";
  2187. regulator-min-microvolt = <0xaae60>;
  2188. regulator-max-microvolt = <0x155cc0>;
  2189. regulator-always-on;
  2190. regulator-boot-on;
  2191. ti,roof-floor = <0x3>;
  2192.  
  2193. consumers {
  2194.  
  2195. c1 {
  2196. regulator-consumer-supply = "vdd_core";
  2197. };
  2198. };
  2199. };
  2200.  
  2201. smps8 {
  2202. regulator-name = "vdd-1v8";
  2203. regulator-always-on;
  2204. regulator-boot-on;
  2205. linux,phandle = <0x8>;
  2206. phandle = <0x8>;
  2207.  
  2208. consumers {
  2209.  
  2210. c1 {
  2211. regulator-consumer-supply = "dbvdd";
  2212. regulator-consumer-device = "tegra-snd-rt5639.0";
  2213. };
  2214.  
  2215. c2 {
  2216. regulator-consumer-supply = "avdd";
  2217. regulator-consumer-device = "tegra-snd-rt5639.0";
  2218. };
  2219.  
  2220. c3 {
  2221. regulator-consumer-supply = "avdd_osc";
  2222. };
  2223.  
  2224. c4 {
  2225. regulator-consumer-supply = "vddio_sys";
  2226. };
  2227.  
  2228. c5 {
  2229. regulator-consumer-supply = "vddio_sys_2";
  2230. };
  2231.  
  2232. c6 {
  2233. regulator-consumer-supply = "vddio_gmi";
  2234. };
  2235.  
  2236. c7 {
  2237. regulator-consumer-supply = "vddio_sdmmc";
  2238. regulator-consumer-device = "sdhci-tegra.0";
  2239. };
  2240.  
  2241. c8 {
  2242. regulator-consumer-supply = "vddio_sdmmc";
  2243. regulator-consumer-device = "sdhci-tegra.3";
  2244. };
  2245.  
  2246. c9 {
  2247. regulator-consumer-supply = "avdd_pll_utmip";
  2248. regulator-consumer-device = "tegra-udc.0";
  2249. };
  2250.  
  2251. c10 {
  2252. regulator-consumer-supply = "avdd_pll_utmip";
  2253. regulator-consumer-device = "tegra-ehci.0";
  2254. };
  2255.  
  2256. c11 {
  2257. regulator-consumer-supply = "avdd_pll_utmip";
  2258. regulator-consumer-device = "tegra-ehci.1";
  2259. };
  2260.  
  2261. c12 {
  2262. regulator-consumer-supply = "avdd_pll_utmip";
  2263. regulator-consumer-device = "tegra-ehci.2";
  2264. };
  2265.  
  2266. c14 {
  2267. regulator-consumer-supply = "vddio_audio";
  2268. };
  2269.  
  2270. c15 {
  2271. regulator-consumer-supply = "vddio_uart";
  2272. };
  2273.  
  2274. c16 {
  2275. regulator-consumer-supply = "vddio_bb";
  2276. };
  2277.  
  2278. c17 {
  2279. regulator-consumer-supply = "vdd_1v8_eeprom";
  2280. };
  2281.  
  2282. c18 {
  2283. regulator-consumer-supply = "vlogic";
  2284. regulator-consumer-device = "0-0069";
  2285. };
  2286.  
  2287. c19 {
  2288. regulator-consumer-supply = "vdd";
  2289. regulator-consumer-device = "0-0069";
  2290. };
  2291.  
  2292. c20 {
  2293. regulator-consumer-supply = "dmicvdd";
  2294. regulator-consumer-device = "tegra-snd-rt5639.0";
  2295. };
  2296.  
  2297. c21 {
  2298. regulator-consumer-supply = "dmicvdd";
  2299. regulator-consumer-device = "tegra-snd-rt5645.0";
  2300. };
  2301.  
  2302. c22 {
  2303. regulator-consumer-supply = "vid";
  2304. regulator-consumer-device = "0-000d";
  2305. };
  2306.  
  2307. c23 {
  2308. regulator-consumer-supply = "pwrdet_nand";
  2309. };
  2310.  
  2311. c24 {
  2312. regulator-consumer-supply = "pwrdet_sdmmc1";
  2313. };
  2314.  
  2315. c25 {
  2316. regulator-consumer-supply = "pwrdet_sdmmc4";
  2317. };
  2318.  
  2319. c26 {
  2320. regulator-consumer-supply = "pwrdet_audio";
  2321. };
  2322.  
  2323. c27 {
  2324. regulator-consumer-supply = "pwrdet_uart";
  2325. };
  2326.  
  2327. c28 {
  2328. regulator-consumer-supply = "pwrdet_bb";
  2329. };
  2330. };
  2331. };
  2332.  
  2333. smps9 {
  2334. regulator-name = "vdd-snsr";
  2335. regulator-min-microvolt = <0x325aa0>;
  2336. regulator-max-microvolt = <0x325aa0>;
  2337. regulator-always-on;
  2338. regulator-boot-on;
  2339. linux,phandle = <0x9>;
  2340. phandle = <0x9>;
  2341.  
  2342. consumers {
  2343.  
  2344. c1 {
  2345. regulator-consumer-supply = "vddio_sd_slot";
  2346. regulator-consumer-device = "sdhci-tegra.3";
  2347. };
  2348.  
  2349. c2 {
  2350. regulator-consumer-supply = "vdd";
  2351. regulator-consumer-device = "0-000d";
  2352. };
  2353.  
  2354. c3 {
  2355. regulator-consumer-supply = "vdd";
  2356. regulator-consumer-device = "0-004c";
  2357. };
  2358.  
  2359. c4 {
  2360. regulator-consumer-supply = "vdd";
  2361. regulator-consumer-device = "0-004d";
  2362. };
  2363. };
  2364. };
  2365.  
  2366. smps10_out1 {
  2367. regulator-name = "vdd-out1-5v0";
  2368. regulator-min-microvolt = <0x4c4b40>;
  2369. regulator-max-microvolt = <0x4c4b40>;
  2370. linux,phandle = <0x18>;
  2371. phandle = <0x18>;
  2372. };
  2373.  
  2374. smps10_out2 {
  2375. regulator-name = "vdd-out2-5v0";
  2376. regulator-min-microvolt = <0x4c4b40>;
  2377. regulator-max-microvolt = <0x4c4b40>;
  2378. linux,phandle = <0xe>;
  2379. phandle = <0xe>;
  2380.  
  2381. consumers {
  2382.  
  2383. c1 {
  2384. regulator-consumer-supply = "spkvdd";
  2385. regulator-consumer-device = "tegra-snd-rt5639.0";
  2386. };
  2387.  
  2388. c2 {
  2389. regulator-consumer-supply = "spkvdd";
  2390. regulator-consumer-device = "tegra-snd-rt5645.0";
  2391. };
  2392. };
  2393. };
  2394.  
  2395. ldo1 {
  2396. regulator-name = "avdd-pll";
  2397. regulator-always-on;
  2398. regulator-boot-on;
  2399. ti,roof-floor = <0x3>;
  2400.  
  2401. consumers {
  2402.  
  2403. c1 {
  2404. regulator-consumer-supply = "avdd_pll_m";
  2405. };
  2406.  
  2407. c2 {
  2408. regulator-consumer-supply = "avdd_pll_ap_c2_c3";
  2409. };
  2410.  
  2411. c3 {
  2412. regulator-consumer-supply = "avdd_pll_cud2dpd";
  2413. };
  2414.  
  2415. c4 {
  2416. regulator-consumer-supply = "avdd_pll_c4";
  2417. };
  2418.  
  2419. c5 {
  2420. regulator-consumer-supply = "vddio_ddr_hs";
  2421. };
  2422.  
  2423. c6 {
  2424. regulator-consumer-supply = "avdd_pll_erefe";
  2425. };
  2426.  
  2427. c7 {
  2428. regulator-consumer-supply = "avdd_pll_cg";
  2429. };
  2430.  
  2431. c8 {
  2432. regulator-consumer-supply = "avdd_pll_x";
  2433. };
  2434. };
  2435. };
  2436.  
  2437. ldo2 {
  2438. regulator-name = "avdd-lcd";
  2439. regulator-min-microvolt = <0x325aa0>;
  2440. regulator-max-microvolt = <0x325aa0>;
  2441.  
  2442. consumers {
  2443.  
  2444. c1 {
  2445. regulator-consumer-supply = "avdd_lcd";
  2446. regulator-consumer-device = "tegradc.0";
  2447. };
  2448. };
  2449. };
  2450.  
  2451. ldo3 {
  2452. regulator-name = "vdd-touch";
  2453. regulator-min-microvolt = <0x325aa0>;
  2454. regulator-max-microvolt = <0x325aa0>;
  2455. regulator-enable-ramp-delay = <0xbb8>;
  2456. ti,disable-pull-down;
  2457. linux,phandle = <0x19>;
  2458. phandle = <0x19>;
  2459. };
  2460.  
  2461. ldo4 {
  2462. regulator-name = "avdd-cam1";
  2463. regulator-min-microvolt = <0x2932e0>;
  2464. regulator-max-microvolt = <0x2932e0>;
  2465.  
  2466. consumers {
  2467.  
  2468. c1 {
  2469. regulator-consumer-supply = "avdd_ov5693";
  2470. regulator-consumer-device = "2-0010";
  2471. };
  2472. };
  2473. };
  2474.  
  2475. ldo5 {
  2476. regulator-name = "avdd-dsi-csi";
  2477. linux,phandle = <0x14>;
  2478. phandle = <0x14>;
  2479.  
  2480. consumers {
  2481.  
  2482. c1 {
  2483. regulator-consumer-supply = "vddio_hsic";
  2484. regulator-consumer-device = "tegra-ehci.1";
  2485. };
  2486.  
  2487. c2 {
  2488. regulator-consumer-supply = "vddio_hsic";
  2489. regulator-consumer-device = "tegra-ehci.2";
  2490. };
  2491.  
  2492. c4 {
  2493. regulator-consumer-supply = "avdd_dsi_csi";
  2494. regulator-consumer-device = "tegradc.0";
  2495. };
  2496.  
  2497. c5 {
  2498. regulator-consumer-supply = "avdd_dsi_csi";
  2499. regulator-consumer-device = "tegradc.1";
  2500. };
  2501.  
  2502. c6 {
  2503. regulator-consumer-supply = "avdd_dsi_csi";
  2504. regulator-consumer-device = "vi.0";
  2505. };
  2506.  
  2507. c7 {
  2508. regulator-consumer-supply = "avdd_dsi_csi";
  2509. regulator-consumer-device = "vi.1";
  2510. };
  2511.  
  2512. c8 {
  2513. regulator-consumer-supply = "vdd_lcd_bl";
  2514. regulator-consumer-device = "tegradc.0";
  2515. };
  2516.  
  2517. c9 {
  2518. regulator-consumer-supply = "pwrdet_mipi";
  2519. };
  2520. };
  2521. };
  2522.  
  2523. ldo6 {
  2524. regulator-name = "vpp-fuse";
  2525. regulator-min-microvolt = <0x1b7740>;
  2526. regulator-max-microvolt = <0x1b7740>;
  2527. linux,phandle = <0x12>;
  2528. phandle = <0x12>;
  2529. };
  2530.  
  2531. ldo7 {
  2532. regulator-name = "avdd-cam-af";
  2533. regulator-min-microvolt = <0x2932e0>;
  2534. regulator-max-microvolt = <0x2932e0>;
  2535.  
  2536. consumers {
  2537.  
  2538. c1 {
  2539. regulator-consumer-supply = "avdd_af1_cam";
  2540. };
  2541.  
  2542. c2 {
  2543. regulator-consumer-supply = "avdd_cam2_cam";
  2544. };
  2545.  
  2546. c3 {
  2547. regulator-consumer-supply = "vdd_af1";
  2548. regulator-consumer-device = "2-0010";
  2549. };
  2550.  
  2551. c4 {
  2552. regulator-consumer-supply = "vdd";
  2553. regulator-consumer-device = "2-000c";
  2554. };
  2555.  
  2556. c5 {
  2557. regulator-consumer-supply = "vana";
  2558. regulator-consumer-device = "2-0048";
  2559. };
  2560.  
  2561. c6 {
  2562. regulator-consumer-supply = "vana";
  2563. regulator-consumer-device = "2-0036";
  2564. };
  2565.  
  2566. c7 {
  2567. regulator-consumer-supply = "vin";
  2568. regulator-consumer-device = "2-0030";
  2569. };
  2570.  
  2571. c8 {
  2572. regulator-consumer-supply = "vana";
  2573. regulator-consumer-device = "2-0010";
  2574. };
  2575. };
  2576. };
  2577.  
  2578. ldo8 {
  2579. regulator-name = "vdd-rtc";
  2580. regulator-min-microvolt = <0xe7ef0>;
  2581. regulator-max-microvolt = <0xe7ef0>;
  2582. regulator-always-on;
  2583. regulator-boot-on;
  2584.  
  2585. consumers {
  2586.  
  2587. c1 {
  2588. regulator-consumer-supply = "vdd_rtc";
  2589. };
  2590. };
  2591. };
  2592.  
  2593. ldo9 {
  2594. regulator-name = "vddio-sdmmc-2";
  2595. regulator-min-microvolt = <0x1b7740>;
  2596. regulator-max-microvolt = <0x325aa0>;
  2597.  
  2598. consumers {
  2599.  
  2600. c1 {
  2601. regulator-consumer-supply = "vddio_sdmmc";
  2602. regulator-consumer-device = "sdhci-tegra.2";
  2603. };
  2604.  
  2605. c2 {
  2606. regulator-consumer-supply = "pwrdet_sdmmc3";
  2607. };
  2608. };
  2609. };
  2610.  
  2611. ldoln {
  2612. regulator-name = "vddio-hv";
  2613. regulator-always-on;
  2614. regulator-boot-on;
  2615.  
  2616. consumers {
  2617.  
  2618. c1 {
  2619. regulator-consumer-supply = "vddio_hv";
  2620. regulator-consumer-device = "tegradc.1";
  2621. };
  2622.  
  2623. c2 {
  2624. regulator-consumer-supply = "avdd_hdmi";
  2625. regulator-consumer-device = "tegradc.1";
  2626. };
  2627.  
  2628. c3 {
  2629. regulator-consumer-supply = "pwrdet_hv";
  2630. };
  2631.  
  2632. c4 {
  2633. regulator-consumer-supply = "vddio_pex_ctl";
  2634. regulator-consumer-device = "tegra-pcie";
  2635. };
  2636. };
  2637. };
  2638.  
  2639. ldousb {
  2640. regulator-name = "avdd-usb";
  2641. regulator-always-on;
  2642. regulator-boot-on;
  2643. linux,phandle = <0x13>;
  2644. phandle = <0x13>;
  2645.  
  2646. consumers {
  2647.  
  2648. c1 {
  2649. regulator-consumer-supply = "pwrdet_pex_ctl";
  2650. };
  2651.  
  2652. c2 {
  2653. regulator-consumer-supply = "avdd_usb";
  2654. regulator-consumer-device = "tegra-udc.0";
  2655. };
  2656.  
  2657. c3 {
  2658. regulator-consumer-supply = "avdd_usb";
  2659. regulator-consumer-device = "tegra-ehci.0";
  2660. };
  2661.  
  2662. c4 {
  2663. regulator-consumer-supply = "avdd_usb";
  2664. regulator-consumer-device = "tegra-ehci.1";
  2665. };
  2666.  
  2667. c5 {
  2668. regulator-consumer-supply = "avdd_usb";
  2669. regulator-consumer-device = "tegra-ehci.2";
  2670. };
  2671.  
  2672. c7 {
  2673. regulator-consumer-supply = "hvdd_pex";
  2674. regulator-consumer-device = "tegra-pcie";
  2675. };
  2676.  
  2677. c8 {
  2678. regulator-consumer-supply = "hvdd_pex_pll_e";
  2679. regulator-consumer-device = "tegra-pcie";
  2680. };
  2681. };
  2682. };
  2683. };
  2684. };
  2685. };
  2686. };
  2687.  
  2688. i2c@7000d100 {
  2689. #address-cells = <0x1>;
  2690. #size-cells = <0x0>;
  2691. compatible = "nvidia,tegra124-i2c";
  2692. reg = <0x0 0x7000d100 0x0 0x100>;
  2693. interrupts = <0x0 0x3f 0x4>;
  2694. nvidia,memory-clients = <0xe>;
  2695. status = "okay";
  2696. clock-frequency = <0x61a80>;
  2697. };
  2698.  
  2699. spi@7000d400 {
  2700. compatible = "nvidia,tegra114-spi";
  2701. reg = <0x0 0x7000d400 0x0 0x200>;
  2702. interrupts = <0x0 0x3b 0x4>;
  2703. nvidia,dma-request-selector = <0x6 0xf>;
  2704. nvidia,memory-clients = <0xe>;
  2705. #address-cells = <0x1>;
  2706. #size-cells = <0x0>;
  2707. status = "okay";
  2708. spi-max-frequency = <0x17d7840>;
  2709. };
  2710.  
  2711. spi@7000d600 {
  2712. compatible = "nvidia,tegra114-spi";
  2713. reg = <0x0 0x7000d600 0x0 0x200>;
  2714. interrupts = <0x0 0x52 0x4>;
  2715. nvidia,dma-request-selector = <0x6 0x10>;
  2716. nvidia,memory-clients = <0xe>;
  2717. #address-cells = <0x1>;
  2718. #size-cells = <0x0>;
  2719. status = "disabled";
  2720. };
  2721.  
  2722. spi@7000d800 {
  2723. compatible = "nvidia,tegra114-spi";
  2724. reg = <0x0 0x7000d800 0x0 0x200>;
  2725. interrupts = <0x0 0x53 0x4>;
  2726. nvidia,dma-request-selector = <0x6 0x11>;
  2727. nvidia,memory-clients = <0xe>;
  2728. #address-cells = <0x1>;
  2729. #size-cells = <0x0>;
  2730. status = "disabled";
  2731. };
  2732.  
  2733. spi@7000da00 {
  2734. compatible = "nvidia,tegra114-spi";
  2735. reg = <0x0 0x7000da00 0x0 0x200>;
  2736. interrupts = <0x0 0x5d 0x4>;
  2737. nvidia,dma-request-selector = <0x6 0x12>;
  2738. nvidia,memory-clients = <0xe>;
  2739. #address-cells = <0x1>;
  2740. #size-cells = <0x0>;
  2741. status = "okay";
  2742. spi-max-frequency = <0x17d7840>;
  2743. };
  2744.  
  2745. spi@7000dc00 {
  2746. compatible = "nvidia,tegra114-spi";
  2747. reg = <0x0 0x7000dc00 0x0 0x200>;
  2748. interrupts = <0x0 0x5e 0x4>;
  2749. nvidia,dma-request-selector = <0x6 0x1b>;
  2750. nvidia,memory-clients = <0xe>;
  2751. #address-cells = <0x1>;
  2752. #size-cells = <0x0>;
  2753. status = "disabled";
  2754. };
  2755.  
  2756. spi@7000de00 {
  2757. compatible = "nvidia,tegra114-spi";
  2758. reg = <0x0 0x7000de00 0x0 0x200>;
  2759. interrupts = <0x0 0x4f 0x4>;
  2760. nvidia,dma-request-selector = <0x6 0x1c>;
  2761. nvidia,memory-clients = <0xe>;
  2762. #address-cells = <0x1>;
  2763. #size-cells = <0x0>;
  2764. status = "disabled";
  2765. };
  2766.  
  2767. pmc {
  2768. compatible = "nvidia,tegra124-pmc";
  2769. reg = <0x0 0x7000e400 0x0 0x400>;
  2770. clocks = <0x10 0x105 0x11>;
  2771. clock-names = "pclk", "clk32k_in";
  2772. };
  2773.  
  2774. efuse@7000f800 {
  2775. compatible = "nvidia,tegra124-efuse";
  2776. reg = <0x0 0x7000f800 0x0 0x400>;
  2777. vpp_fuse-supply = <0x12>;
  2778. };
  2779.  
  2780. clocks {
  2781. compatible = "simple-bus";
  2782. #address-cells = <0x1>;
  2783. #size-cells = <0x0>;
  2784.  
  2785. clock {
  2786. compatible = "fixed-clock";
  2787. reg = <0x0>;
  2788. #clock-cells = <0x0>;
  2789. clock-frequency = <0x8000>;
  2790. linux,phandle = <0x11>;
  2791. phandle = <0x11>;
  2792. };
  2793. };
  2794.  
  2795. timer@60005000 {
  2796. compatible = "nvidia,tegra-nvtimer";
  2797. reg = <0x0 0x60005000 0x0 0x400>;
  2798. interrupts = <0x0 0x0 0x4 0x0 0x1 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x79 0x4 0x0 0x97 0x4 0x0 0x98 0x4 0x0 0x99 0x4 0x0 0x9a 0x4 0x0 0x9b 0x4 0x0 0x7a 0x4>;
  2799. clocks = <0x10 0x5>;
  2800. };
  2801.  
  2802. rtc {
  2803. compatible = "nvidia,tegra-rtc";
  2804. reg = <0x0 0x7000e000 0x0 0x100>;
  2805. interrupts = <0x0 0x2 0x4>;
  2806. clocks = <0x10 0x4>;
  2807. };
  2808.  
  2809. ahub {
  2810. compatible = "nvidia,tegra124-ahub";
  2811. reg = <0x0 0x70300000 0x0 0x200 0x0 0x70300800 0x0 0x800 0x0 0x70300200 0x0 0x200>;
  2812. interrupts = <0x0 0x67 0x4>;
  2813. nvidia,dma-request-selector = <0x6 0x1 0x6 0x2 0x6 0x3 0x6 0x4 0x6 0x6 0x6 0x7 0x6 0xc 0x6 0xd 0x6 0xe 0x6 0x1d>;
  2814. status = "disabled";
  2815. #address-cells = <0x1>;
  2816. #size-cells = <0x1>;
  2817. ranges = <0x70300000 0x0 0x70300000 0x10000>;
  2818.  
  2819. i2s@70301000 {
  2820. compatible = "nvidia,tegra124-i2s";
  2821. reg = <0x70301000 0x100>;
  2822. nvidia,ahub-cif-ids = <0x4 0x4>;
  2823. status = "disabled";
  2824. };
  2825.  
  2826. i2s@70301100 {
  2827. compatible = "nvidia,tegra124-i2s";
  2828. reg = <0x70301100 0x100>;
  2829. nvidia,ahub-cif-ids = <0x5 0x5>;
  2830. status = "disabled";
  2831. };
  2832.  
  2833. i2s@70301200 {
  2834. compatible = "nvidia,tegra124-i2s";
  2835. reg = <0x70301200 0x100>;
  2836. nvidia,ahub-cif-ids = <0x6 0x6>;
  2837. status = "disabled";
  2838. };
  2839.  
  2840. i2s@70301300 {
  2841. compatible = "nvidia,tegra124-i2s";
  2842. reg = <0x70301300 0x100>;
  2843. nvidia,ahub-cif-ids = <0x7 0x7>;
  2844. status = "disabled";
  2845. };
  2846.  
  2847. i2s@70301400 {
  2848. compatible = "nvidia,tegra124-i2s";
  2849. reg = <0x70301400 0x100>;
  2850. nvidia,ahub-cif-ids = <0x8 0x8>;
  2851. status = "disabled";
  2852. };
  2853.  
  2854. amx@70303000 {
  2855. compatible = "nvidia,tegra124-amx";
  2856. reg = <0x70303000 0x100>;
  2857. status = "disabled";
  2858. };
  2859.  
  2860. amx@70303100 {
  2861. compatible = "nvidia,tegra124-amx";
  2862. reg = <0x70303100 0x100>;
  2863. status = "disabled";
  2864. };
  2865.  
  2866. adx@70303800 {
  2867. compatible = "nvidia,tegra124-adx";
  2868. reg = <0x70303800 0x100>;
  2869. status = "disabled";
  2870. };
  2871.  
  2872. adx@70303900 {
  2873. compatible = "nvidia,tegra124-adx";
  2874. reg = <0x70303900 0x100>;
  2875. status = "disabled";
  2876. };
  2877.  
  2878. spdif@70306000 {
  2879. compatible = "nvidia,tegra124-spdif";
  2880. reg = <0x70306000 0x100>;
  2881. status = "disabled";
  2882. };
  2883. };
  2884.  
  2885. host1x {
  2886. compatible = "nvidia,tegra124-host1x", "simple-bus";
  2887. reg = <0x0 0x50000000 0x0 0x28000>;
  2888. interrupts = <0x0 0x41 0x4 0x0 0x43 0x4>;
  2889. nvidia,memory-clients = <0x4 0x6 0x7 0x11>;
  2890. #address-cells = <0x1>;
  2891. #size-cells = <0x1>;
  2892. ranges = <0x53000000 0x0 0x53000000 0x6000000 0x60001000 0x0 0x60001000 0xe200>;
  2893.  
  2894. vi {
  2895. compatible = "nvidia,tegra124-vi";
  2896. reg = <0x54080000 0x40000>;
  2897. interrupts = <0x0 0x45 0x4>;
  2898. nvidia,memory-clients = <0x12>;
  2899. };
  2900.  
  2901. isp@54600000 {
  2902. compatible = "nvidia,tegra124-isp";
  2903. reg = <0x54600000 0x40000>;
  2904. interrupts = <0x0 0x47 0x4>;
  2905. nvidia,memory-clients = <0x8 0x1d>;
  2906. };
  2907.  
  2908. isp@54680000 {
  2909. compatible = "nvidia,tegra124-isp";
  2910. reg = <0x54680000 0x40000>;
  2911. interrupts = <0x0 0x46 0x4>;
  2912. nvidia,memory-clients = <0x8 0x1d>;
  2913. };
  2914.  
  2915. dc@54200000 {
  2916. compatible = "nvidia,tegra124-dc";
  2917. reg = <0x54200000 0x40000>;
  2918. interrupts = <0x0 0x49 0x4>;
  2919. nvidia,memory-clients = <0x2>;
  2920. status = "disabled";
  2921.  
  2922. rgb {
  2923. status = "disabled";
  2924. };
  2925. };
  2926.  
  2927. dc@54240000 {
  2928. compatible = "nvidia,tegra124-dc";
  2929. reg = <0x54240000 0x40000>;
  2930. interrupts = <0x0 0x4a 0x4>;
  2931. nvidia,memory-clients = <0x3>;
  2932. status = "disabled";
  2933.  
  2934. rgb {
  2935. status = "disabled";
  2936. };
  2937. };
  2938.  
  2939. hdmi {
  2940. compatible = "nvidia,tegra124-hdmi";
  2941. reg = <0x54280000 0x40000>;
  2942. interrupts = <0x0 0x4b 0x4>;
  2943. status = "okay";
  2944. };
  2945.  
  2946. dsi {
  2947. compatible = "nvidia,tegra124-dsi";
  2948. reg = <0x54300000 0x40000 0x54400000 0x40000>;
  2949. status = "disabled";
  2950. };
  2951.  
  2952. vic {
  2953. compatible = "nvidia,tegra124-vic";
  2954. reg = <0x54340000 0x40000>;
  2955. nvidia,memory-clients = <0x13>;
  2956. };
  2957.  
  2958. msenc {
  2959. compatible = "nvidia,tegra124-msenc";
  2960. reg = <0x544c0000 0x40000>;
  2961. nvidia,memory-clients = <0xb>;
  2962. };
  2963.  
  2964. tsec {
  2965. compatible = "nvidia,tegra124-tsec";
  2966. reg = <0x54500000 0x40000>;
  2967. nvidia,memory-clients = <0x17>;
  2968. };
  2969.  
  2970. gk20a {
  2971. compatible = "nvidia,tegra124-gk20a";
  2972. reg = <0x57000000 0x1000000 0x58000000 0x1000000 0x538f0000 0x1000>;
  2973. interrupts = <0x0 0x9d 0x4 0x0 0x9e 0x4>;
  2974. nvidia,memory-clients = <0x1e 0x1f>;
  2975. };
  2976.  
  2977. nvavp {
  2978. compatible = "nvidia,tegra124-nvavp";
  2979. interrupts = <0x0 0x4 0x4>;
  2980. reg = <0x60001000 0xe200>;
  2981. };
  2982. };
  2983.  
  2984. xusb@70090000 {
  2985. compatible = "nvidia,tegra124-xhci";
  2986. reg = <0x0 0x70090000 0x0 0x8000 0x0 0x70098000 0x0 0x1000 0x0 0x70099000 0x0 0x1000 0x0 0x7009f000 0x0 0x1000>;
  2987. interrupts = <0x0 0x27 0x4 0x0 0x28 0x4 0x0 0x31 0x4 0x0 0x61 0x4 0x0 0x15 0x4>;
  2988. status = "okay";
  2989. nvidia,gpio_ss1_sata = <0x0>;
  2990. nvidia,portmap = <0x101>;
  2991. nvidia,ss_portmap = <0x0>;
  2992. nvidia,lane_owner = <0x4>;
  2993. nvidia,ulpicap = <0x0>;
  2994. hvdd_usb-supply = <0x13>;
  2995. avdd_pll_utmip-supply = <0x8>;
  2996. vddio_hsic-supply = <0x14>;
  2997. avddio_usb-supply = <0xe>;
  2998. };
  2999.  
  3000. mipical {
  3001. compatible = "nvidia,tegra124-mipical";
  3002. reg = <0x0 0x700e3000 0x0 0x100>;
  3003. };
  3004.  
  3005. pcie-controller {
  3006. compatible = "nvidia,tegra124-pcie";
  3007. status = "disabled";
  3008. };
  3009.  
  3010. sata-controller {
  3011. compatible = "nvidia,tegra124-sata";
  3012. reg = <0x0 0x70027000 0x0 0x2000 0x0 0x70021000 0x0 0x1000>;
  3013. interrupts = <0x0 0x17 0x4>;
  3014. status = "disabled";
  3015. };
  3016.  
  3017. psci {
  3018. compatible = "arm,psci";
  3019. method = "smc";
  3020. cpu_suspend = <0x84000001>;
  3021. cpu_on = <0x84000003>;
  3022. };
  3023.  
  3024. interrupt-controller@50041000 {
  3025. compatible = "arm,cortex-a15-gic";
  3026. interrupt-controller;
  3027. #interrupt-cells = <0x3>;
  3028. reg = <0x0 0x50041000 0x0 0x1000 0x0 0x50042000 0x0 0x100>;
  3029. linux,phandle = <0x1>;
  3030. phandle = <0x1>;
  3031. };
  3032.  
  3033. interrupt-controller@60004000 {
  3034. compatible = "nvidia,tegra-gic";
  3035. interrupt-controller;
  3036. reg = <0x0 0x60004000 0x0 0x40 0x0 0x60004100 0x0 0x40 0x0 0x60004200 0x0 0x40 0x0 0x60004300 0x0 0x40 0x0 0x60004400 0x0 0x40>;
  3037. };
  3038.  
  3039. timer {
  3040. compatible = "arm,armv7-timer";
  3041. interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04>;
  3042. };
  3043.  
  3044. dfll@70110000 {
  3045. compatible = "nvidia,tegra124-dfll";
  3046. reg = <0x0 0x70110000 0x0 0x400>;
  3047. out-clock-name = "dfll_cpu";
  3048. status = "okay";
  3049. board-params = <0x15>;
  3050. i2c-pmic-integration = <0x16>;
  3051. };
  3052.  
  3053. watchdog@60005100 {
  3054. compatible = "nvidia,tegra-wdt";
  3055. reg = <0x0 0x60005100 0x0 0x20 0x0 0x60005070 0x0 0x8>;
  3056. };
  3057.  
  3058. memory@0x80000000 {
  3059. device_type = "memory";
  3060. reg = <0x0 0x80000000 0x0 0x80000000>;
  3061. };
  3062.  
  3063. memory-controller@7001b000 {
  3064. compatible = "nvidia,tegra12-emc";
  3065. reg = <0x0 0x7001b000 0x0 0x800>;
  3066. #address-cells = <0x1>;
  3067. #size-cells = <0x0>;
  3068.  
  3069. emc-table@12750 {
  3070. compatible = "nvidia,tegra12-emc-table";
  3071. nvidia,revision = <0x19>;
  3072. nvidia,dvfs-version = "02_12750_NoCfgVersion_V5.0.18_V1.1";
  3073. clock-frequency = <0x31ce>;
  3074. nvidia,emc-min-mv = <0x320>;
  3075. nvidia,gk20a-min-mv = <0x320>;
  3076. nvidia,source = "pllp_out0";
  3077. nvidia,src-sel-reg = <0x4000003e>;
  3078. nvidia,burst-regs-num = <0xa5>;
  3079. nvidia,burst-up-down-regs-num = <0x1f>;
  3080. nvidia,emc-registers = <0x0 0x3 0x0 0x0 0x0 0x4 0xa 0x5 0xb 0x0 0x0 0x3 0x3 0x0 0x6 0x6 0x6 0x2 0x0 0x5 0x5 0x10000 0x3 0x0 0x0 0x0 0x0 0x4 0xc 0xd 0xf 0x60 0x0 0x18 0x2 0x2 0x1 0x0 0x7 0xf 0x5 0x5 0x4 0x5 0x4 0x0 0x0 0x5 0x5 0x64 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xfc000 0xfc000 0xfc000 0xfc000 0xfc00 0xfc00 0xfc00 0xfc00 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0x7 0x0 0x0 0x42 0xe000e 0xe000e 0x0 0x3 0xf2f3 0x800001c5 0xa 0x40040001 0x8000000a 0x1 0x1 0x2 0x0 0x2 0x1 0x3 0x8 0x3 0x2 0x3 0x6 0x6030203 0xa0502 0x77e30303 0x70000f03 0x1f0000>;
  3081. nvidia,emc-burst-up-down-regs = <0x1 0x7 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff0049 0xff0080 0xff0004 0xff0004 0x800ff 0xff 0xff0004 0xff00ff 0xff00ff 0xff0024 0xff00ff 0xff 0xff 0xff00ff 0xff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff>;
  3082. nvidia,emc-zcal-cnt-long = <0x42>;
  3083. nvidia,emc-acal-interval = <0x1fffff>;
  3084. nvidia,emc-ctt-term_ctrl = <0x802>;
  3085. nvidia,emc-cfg = <0x73240000>;
  3086. nvidia,emc-cfg-2 = <0x8c5>;
  3087. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3088. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3089. nvidia,emc-bgbias-ctl0 = <0x8>;
  3090. nvidia,emc-auto-cal-config2 = <0x0>;
  3091. nvidia,emc-auto-cal-config3 = <0x0>;
  3092. nvidia,emc-auto-cal-config = <0xa1430000>;
  3093. nvidia,emc-mode-0 = <0x80001221>;
  3094. nvidia,emc-mode-1 = <0x80100003>;
  3095. nvidia,emc-mode-2 = <0x80200008>;
  3096. nvidia,emc-mode-4 = <0x0>;
  3097. nvidia,emc-clock-latency-change = <0xe1dc>;
  3098. };
  3099.  
  3100. emc-table@20400 {
  3101. compatible = "nvidia,tegra12-emc-table";
  3102. nvidia,revision = <0x19>;
  3103. nvidia,dvfs-version = "02_20400_NoCfgVersion_V5.0.18_V1.1";
  3104. clock-frequency = <0x4fb0>;
  3105. nvidia,emc-min-mv = <0x320>;
  3106. nvidia,gk20a-min-mv = <0x320>;
  3107. nvidia,source = "pllp_out0";
  3108. nvidia,src-sel-reg = <0x40000026>;
  3109. nvidia,burst-regs-num = <0xa5>;
  3110. nvidia,burst-up-down-regs-num = <0x1f>;
  3111. nvidia,emc-registers = <0x0 0x5 0x0 0x0 0x0 0x4 0xa 0x5 0xb 0x0 0x0 0x3 0x3 0x0 0x6 0x6 0x6 0x2 0x0 0x5 0x5 0x10000 0x3 0x0 0x0 0x0 0x0 0x4 0xc 0xd 0xf 0x9a 0x0 0x26 0x2 0x2 0x1 0x0 0x7 0xf 0x6 0x6 0x4 0x5 0x4 0x0 0x0 0x5 0x5 0xa0 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xfc000 0xfc000 0xfc000 0xfc000 0xfc00 0xfc00 0xfc00 0xfc00 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0xb 0x0 0x0 0x42 0xe000e 0xe000e 0x0 0x3 0xf2f3 0x8000023a 0xa 0x40020001 0x80000012 0x1 0x1 0x2 0x0 0x2 0x1 0x3 0x8 0x3 0x2 0x3 0x6 0x6030203 0xa0502 0x76230303 0x70000f03 0x1f0000>;
  3112. nvidia,emc-burst-up-down-regs = <0x1 0xa 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff0049 0xff0080 0xff0004 0xff0004 0x800ff 0xff 0xff0004 0xff00ff 0xff00ff 0xff0024 0xff00ff 0xff 0xff 0xff00ff 0xff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff>;
  3113. nvidia,emc-zcal-cnt-long = <0x42>;
  3114. nvidia,emc-acal-interval = <0x1fffff>;
  3115. nvidia,emc-ctt-term_ctrl = <0x802>;
  3116. nvidia,emc-cfg = <0x73240000>;
  3117. nvidia,emc-cfg-2 = <0x8c5>;
  3118. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3119. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3120. nvidia,emc-bgbias-ctl0 = <0x8>;
  3121. nvidia,emc-auto-cal-config2 = <0x0>;
  3122. nvidia,emc-auto-cal-config3 = <0x0>;
  3123. nvidia,emc-auto-cal-config = <0xa1430000>;
  3124. nvidia,emc-mode-0 = <0x80001221>;
  3125. nvidia,emc-mode-1 = <0x80100003>;
  3126. nvidia,emc-mode-2 = <0x80200008>;
  3127. nvidia,emc-mode-4 = <0x0>;
  3128. nvidia,emc-clock-latency-change = <0x8b1a>;
  3129. };
  3130.  
  3131. emc-table@40800 {
  3132. compatible = "nvidia,tegra12-emc-table";
  3133. nvidia,revision = <0x19>;
  3134. nvidia,dvfs-version = "02_40800_NoCfgVersion_V5.0.18_V1.1";
  3135. clock-frequency = <0x9f60>;
  3136. nvidia,emc-min-mv = <0x320>;
  3137. nvidia,gk20a-min-mv = <0x320>;
  3138. nvidia,source = "pllp_out0";
  3139. nvidia,src-sel-reg = <0x40000012>;
  3140. nvidia,burst-regs-num = <0xa5>;
  3141. nvidia,burst-up-down-regs-num = <0x1f>;
  3142. nvidia,emc-registers = <0x1 0xa 0x0 0x1 0x0 0x4 0xa 0x5 0xb 0x0 0x0 0x3 0x3 0x0 0x6 0x6 0x6 0x2 0x0 0x5 0x5 0x10000 0x3 0x0 0x0 0x0 0x0 0x4 0xc 0xd 0xf 0x134 0x0 0x4d 0x2 0x2 0x1 0x0 0x8 0xf 0xc 0xc 0x4 0x5 0x4 0x0 0x0 0x5 0x5 0x13f 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xfc000 0xfc000 0xfc000 0xfc000 0xfc00 0xfc00 0xfc00 0xfc00 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0x15 0x0 0x0 0x42 0xe000e 0xe000e 0x0 0x3 0xf2f3 0x80000370 0xa 0xa0000001 0x80000017 0x1 0x1 0x2 0x0 0x2 0x1 0x3 0x8 0x3 0x2 0x3 0x6 0x6030203 0xa0502 0x74a30303 0x70000f03 0x1f0000>;
  3143. nvidia,emc-burst-up-down-regs = <0x1 0x14 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff0049 0xff0080 0xff0004 0xff0004 0x800ff 0xff 0xff0004 0xff00ff 0xff00ff 0xff0024 0xff00ff 0xff 0xff 0xff00ff 0xff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff 0xff00ff>;
  3144. nvidia,emc-zcal-cnt-long = <0x42>;
  3145. nvidia,emc-acal-interval = <0x1fffff>;
  3146. nvidia,emc-ctt-term_ctrl = <0x802>;
  3147. nvidia,emc-cfg = <0x73240000>;
  3148. nvidia,emc-cfg-2 = <0x8c5>;
  3149. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3150. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3151. nvidia,emc-bgbias-ctl0 = <0x8>;
  3152. nvidia,emc-auto-cal-config2 = <0x0>;
  3153. nvidia,emc-auto-cal-config3 = <0x0>;
  3154. nvidia,emc-auto-cal-config = <0xa1430000>;
  3155. nvidia,emc-mode-0 = <0x80001221>;
  3156. nvidia,emc-mode-1 = <0x80100003>;
  3157. nvidia,emc-mode-2 = <0x80200008>;
  3158. nvidia,emc-mode-4 = <0x0>;
  3159. nvidia,emc-clock-latency-change = <0x5172>;
  3160. };
  3161.  
  3162. emc-table@68000 {
  3163. compatible = "nvidia,tegra12-emc-table";
  3164. nvidia,revision = <0x19>;
  3165. nvidia,dvfs-version = "02_68000_NoCfgVersion_V5.0.18_V1.1";
  3166. clock-frequency = <0x109a0>;
  3167. nvidia,emc-min-mv = <0x320>;
  3168. nvidia,gk20a-min-mv = <0x320>;
  3169. nvidia,source = "pllp_out0";
  3170. nvidia,src-sel-reg = <0x4000000a>;
  3171. nvidia,burst-regs-num = <0xa5>;
  3172. nvidia,burst-up-down-regs-num = <0x1f>;
  3173. nvidia,emc-registers = <0x3 0x11 0x0 0x2 0x0 0x4 0xa 0x5 0xb 0x0 0x0 0x3 0x3 0x0 0x6 0x6 0x6 0x2 0x0 0x5 0x5 0x10000 0x3 0x0 0x0 0x0 0x0 0x4 0xc 0xd 0xf 0x202 0x0 0x80 0x2 0x2 0x1 0x0 0xf 0xf 0x13 0x13 0x4 0x5 0x4 0x1 0x0 0x5 0x5 0x213 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xfc000 0xfc000 0xfc000 0xfc000 0xfc00 0xfc00 0xfc00 0xfc00 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0x22 0x0 0x0 0x42 0xe000e 0xe000e 0x0 0x3 0xf2f3 0x8000050e 0xa 0x1 0x8000001e 0x1 0x1 0x2 0x0 0x2 0x1 0x3 0x8 0x3 0x2 0x3 0x6 0x6030203 0xa0502 0x74230403 0x70000f03 0x1f0000>;
  3174. nvidia,emc-burst-up-down-regs = <0x1 0x21 0xff00ff 0xff00ff 0xff00b0 0xff00ff 0xff00ec 0xff00ff 0xff00ec 0xe90049 0xff0080 0xff0004 0xff0004 0x800ff 0xff 0xff0004 0xff00ff 0xff00a3 0xff0024 0xff00ff 0xff 0xef 0xff00ff 0xef 0xff00ff 0xff00ff 0xee00ef 0xff00ff 0xff00ff 0xff00ff 0xff00ff>;
  3175. nvidia,emc-zcal-cnt-long = <0x42>;
  3176. nvidia,emc-acal-interval = <0x1fffff>;
  3177. nvidia,emc-ctt-term_ctrl = <0x802>;
  3178. nvidia,emc-cfg = <0x73240000>;
  3179. nvidia,emc-cfg-2 = <0x8c5>;
  3180. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3181. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3182. nvidia,emc-bgbias-ctl0 = <0x8>;
  3183. nvidia,emc-auto-cal-config2 = <0x0>;
  3184. nvidia,emc-auto-cal-config3 = <0x0>;
  3185. nvidia,emc-auto-cal-config = <0xa1430000>;
  3186. nvidia,emc-mode-0 = <0x80001221>;
  3187. nvidia,emc-mode-1 = <0x80100003>;
  3188. nvidia,emc-mode-2 = <0x80200008>;
  3189. nvidia,emc-mode-4 = <0x0>;
  3190. nvidia,emc-clock-latency-change = <0x29e0>;
  3191. };
  3192.  
  3193. emc-table@102000 {
  3194. compatible = "nvidia,tegra12-emc-table";
  3195. nvidia,revision = <0x19>;
  3196. nvidia,dvfs-version = "02_102000_NoCfgVersion_V5.0.18_V1.1";
  3197. clock-frequency = <0x18e70>;
  3198. nvidia,emc-min-mv = <0x320>;
  3199. nvidia,gk20a-min-mv = <0x320>;
  3200. nvidia,source = "pllp_out0";
  3201. nvidia,src-sel-reg = <0x40000006>;
  3202. nvidia,burst-regs-num = <0xa5>;
  3203. nvidia,burst-up-down-regs-num = <0x1f>;
  3204. nvidia,emc-registers = <0x4 0x1a 0x0 0x3 0x1 0x4 0xa 0x5 0xb 0x1 0x1 0x3 0x3 0x0 0x6 0x6 0x6 0x2 0x0 0x5 0x5 0x10000 0x3 0x0 0x0 0x0 0x0 0x4 0xc 0xd 0xf 0x304 0x0 0xc1 0x2 0x2 0x1 0x0 0x18 0xf 0x1c 0x1c 0x4 0x5 0x4 0x3 0x0 0x5 0x5 0x31c 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0xfc000 0xfc000 0xfc000 0xfc000 0xfc00 0xfc00 0xfc00 0xfc00 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0x33 0x0 0x0 0x42 0xe000e 0xe000e 0x0 0x3 0xf2f3 0x80000713 0xa 0x8000001 0x80000026 0x1 0x1 0x3 0x0 0x2 0x1 0x3 0x8 0x3 0x2 0x3 0x6 0x6030203 0xa0503 0x73c30504 0x70000f03 0x1f0000>;
  3205. nvidia,emc-burst-up-down-regs = <0x1 0x31 0xff00da 0xff00da 0xff0075 0xff00ff 0xff009d 0xff00ff 0xff009d 0x9b0049 0xff0080 0xff0004 0xff0004 0x800ad 0xff 0xff0004 0xff00c6 0xff006d 0xff0024 0xff00d6 0xff 0x9f 0xff00ff 0x9f 0xff00ff 0xff00ff 0x9f00a0 0xff00ff 0xff00ff 0xff00ff 0xff00da>;
  3206. nvidia,emc-zcal-cnt-long = <0x42>;
  3207. nvidia,emc-acal-interval = <0x1fffff>;
  3208. nvidia,emc-ctt-term_ctrl = <0x802>;
  3209. nvidia,emc-cfg = <0x73240000>;
  3210. nvidia,emc-cfg-2 = <0x8c5>;
  3211. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3212. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3213. nvidia,emc-bgbias-ctl0 = <0x8>;
  3214. nvidia,emc-auto-cal-config2 = <0x0>;
  3215. nvidia,emc-auto-cal-config3 = <0x0>;
  3216. nvidia,emc-auto-cal-config = <0xa1430000>;
  3217. nvidia,emc-mode-0 = <0x80001221>;
  3218. nvidia,emc-mode-1 = <0x80100003>;
  3219. nvidia,emc-mode-2 = <0x80200008>;
  3220. nvidia,emc-mode-4 = <0x0>;
  3221. nvidia,emc-clock-latency-change = <0x1aea>;
  3222. };
  3223.  
  3224. emc-table@204000 {
  3225. compatible = "nvidia,tegra12-emc-table";
  3226. nvidia,revision = <0x19>;
  3227. nvidia,dvfs-version = "02_204000_NoCfgVersion_V5.0.18_V1.1";
  3228. clock-frequency = <0x31ce0>;
  3229. nvidia,emc-min-mv = <0x320>;
  3230. nvidia,gk20a-min-mv = <0x320>;
  3231. nvidia,source = "pllp_out0";
  3232. nvidia,src-sel-reg = <0x40000002>;
  3233. nvidia,burst-regs-num = <0xa5>;
  3234. nvidia,burst-up-down-regs-num = <0x1f>;
  3235. nvidia,emc-registers = <0x9 0x35 0x0 0x6 0x2 0x5 0xa 0x5 0xb 0x2 0x2 0x3 0x3 0x0 0x5 0x5 0x6 0x2 0x0 0x4 0x6 0x10000 0x3 0x0 0x0 0x0 0x0 0x3 0xd 0xf 0x11 0x607 0x0 0x181 0x2 0x2 0x1 0x0 0x32 0xf 0x38 0x38 0x4 0x5 0x4 0x7 0x0 0x5 0x5 0x638 0x0 0x0 0x0 0x1069a298 0x2c00a0 0x8000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x14000 0x0 0x0 0x14000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x78000 0x78000 0x78000 0x78000 0x7800 0x7800 0x7800 0x7800 0x10000280 0x0 0x111111 0x130b118 0x0 0x0 0x77ffc081 0x909 0x81f1f108 0x7070004 0x3f 0x16eeeee 0x51451400 0x514514 0x514514 0x51451400 0x3f 0x66 0x0 0x20000 0x100 0xe000e 0xe000e 0x0 0x3 0xd2b3 0x80000d22 0xa 0x1000003 0x80000040 0x1 0x1 0x4 0x2 0x4 0x1 0x3 0x8 0x3 0x2 0x4 0x6 0x6040203 0xa0504 0x73840a05 0x70000f03 0x1f0000>;
  3236. nvidia,emc-burst-up-down-regs = <0x1 0x62 0xff006d 0xff006d 0xff003c 0xff00af 0xff004f 0xff00af 0xff004f 0x4e0049 0xff0080 0xff0004 0xff0004 0x80057 0xff 0xff0004 0xff0063 0xff0036 0xff0024 0xff006b 0xff 0x50 0xff00ff 0x50 0xff00ff 0xd400ff 0x510050 0xff00ff 0xff00ff 0xff00c6 0xff006d>;
  3237. nvidia,emc-zcal-cnt-long = <0x42>;
  3238. nvidia,emc-acal-interval = <0x1fffff>;
  3239. nvidia,emc-ctt-term_ctrl = <0x802>;
  3240. nvidia,emc-cfg = <0x73240000>;
  3241. nvidia,emc-cfg-2 = <0x8cd>;
  3242. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3243. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3244. nvidia,emc-bgbias-ctl0 = <0x8>;
  3245. nvidia,emc-auto-cal-config2 = <0x0>;
  3246. nvidia,emc-auto-cal-config3 = <0x0>;
  3247. nvidia,emc-auto-cal-config = <0xa1430000>;
  3248. nvidia,emc-mode-0 = <0x80001221>;
  3249. nvidia,emc-mode-1 = <0x80100003>;
  3250. nvidia,emc-mode-2 = <0x80200008>;
  3251. nvidia,emc-mode-4 = <0x0>;
  3252. nvidia,emc-clock-latency-change = <0xd5c>;
  3253. };
  3254.  
  3255. emc-table@300000 {
  3256. compatible = "nvidia,tegra12-emc-table";
  3257. nvidia,revision = <0x19>;
  3258. nvidia,dvfs-version = "02_300000_NoCfgVersion_V5.0.18_V1.1";
  3259. clock-frequency = <0x493e0>;
  3260. nvidia,emc-min-mv = <0x334>;
  3261. nvidia,gk20a-min-mv = <0x334>;
  3262. nvidia,source = "pllc_out0";
  3263. nvidia,src-sel-reg = <0x20000002>;
  3264. nvidia,burst-regs-num = <0xa5>;
  3265. nvidia,burst-up-down-regs-num = <0x1f>;
  3266. nvidia,emc-registers = <0xd 0x4d 0x0 0x9 0x3 0x4 0x8 0x2 0x9 0x3 0x3 0x2 0x2 0x0 0x3 0x3 0x5 0x2 0x0 0x2 0x7 0x20000 0x3 0x0 0x0 0x0 0x0 0x1 0xe 0x10 0x12 0x8e4 0x0 0x239 0x1 0x8 0x1 0x0 0x4b 0xe 0x52 0x200 0x4 0x5 0x4 0x9 0x0 0x5 0x5 0x924 0x0 0x0 0x0 0x1049b098 0x2c00a0 0x8000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x8c000 0x8c000 0x0 0x8c000 0x8c000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x50000 0x50000 0x50000 0x50000 0x5000 0x5000 0x5000 0x5000 0x10000280 0x0 0x111111 0x1231339 0x0 0x0 0x77ffc081 0x303 0x81f1f108 0x7070004 0x0 0x16eeeee 0x51451420 0x514514 0x514514 0x51451400 0x3f 0x96 0x0 0x20000 0x100 0x173000e 0x173000e 0x0 0x3 0x52a3 0x800012d7 0x9 0x8000004 0x80000040 0x1 0x2 0x7 0x4 0x5 0x1 0x2 0x7 0x2 0x2 0x4 0x6 0x6040202 0xb0607 0x77450e08 0x70000f03 0x1f0000>;
  3267. nvidia,emc-burst-up-down-regs = <0x4 0x90 0xff004a 0xff004a 0xff003c 0xff0090 0xff0041 0xff0090 0xff0041 0x350049 0xff0080 0xff0004 0xff0004 0x8003b 0xff 0xff0004 0xff0043 0xff002d 0xff0024 0xff0049 0xff 0x36 0xff00ff 0x36 0xff00ff 0xd400ff 0x510036 0xff00ff 0xff00ff 0xff0087 0xff004a>;
  3268. nvidia,emc-zcal-cnt-long = <0x42>;
  3269. nvidia,emc-acal-interval = <0x1fffff>;
  3270. nvidia,emc-ctt-term_ctrl = <0x802>;
  3271. nvidia,emc-cfg = <0x73340000>;
  3272. nvidia,emc-cfg-2 = <0x8d5>;
  3273. nvidia,emc-sel-dpd-ctrl = <0x40128>;
  3274. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3275. nvidia,emc-bgbias-ctl0 = <0x0>;
  3276. nvidia,emc-auto-cal-config2 = <0x0>;
  3277. nvidia,emc-auto-cal-config3 = <0x0>;
  3278. nvidia,emc-auto-cal-config = <0xa1430000>;
  3279. nvidia,emc-mode-0 = <0x80000321>;
  3280. nvidia,emc-mode-1 = <0x80100002>;
  3281. nvidia,emc-mode-2 = <0x80200000>;
  3282. nvidia,emc-mode-4 = <0x0>;
  3283. nvidia,emc-clock-latency-change = <0xa78>;
  3284. };
  3285.  
  3286. emc-table@396000 {
  3287. compatible = "nvidia,tegra12-emc-table";
  3288. nvidia,revision = <0x19>;
  3289. nvidia,dvfs-version = "02_396000_NoCfgVersion_V5.0.18_V1.1";
  3290. clock-frequency = <0x60ae0>;
  3291. nvidia,emc-min-mv = <0x352>;
  3292. nvidia,gk20a-min-mv = <0x352>;
  3293. nvidia,source = "pllm_out0";
  3294. nvidia,src-sel-reg = <0x2>;
  3295. nvidia,burst-regs-num = <0xa5>;
  3296. nvidia,burst-up-down-regs-num = <0x1f>;
  3297. nvidia,emc-registers = <0x11 0x66 0x0 0xc 0x4 0x4 0x8 0x2 0xa 0x4 0x4 0x2 0x2 0x0 0x3 0x3 0x5 0x2 0x0 0x1 0x8 0x20000 0x3 0x0 0x0 0x0 0x0 0x0 0xf 0x10 0x12 0xbd1 0x0 0x2f4 0x1 0x8 0x1 0x0 0x63 0xf 0x6c 0x200 0x4 0x5 0x4 0xd 0x0 0x5 0x5 0xc11 0x0 0x0 0x0 0x1049b098 0x2c00a0 0x8000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x70000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x64000 0x64000 0x0 0x64000 0x64000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x40000 0x40000 0x40000 0x40000 0x4000 0x4000 0x4000 0x4000 0x10000280 0x0 0x111111 0x1231339 0x0 0x0 0x77ffc081 0x303 0x81f1f108 0x7070004 0x0 0x16eeeee 0x51451420 0x514514 0x514514 0x51451400 0x3f 0xc6 0x0 0x20000 0x100 0x15b000e 0x15b000e 0x0 0x3 0x52a3 0x8000188b 0x9 0xf000005 0x80000040 0x1 0x2 0x9 0x5 0x7 0x1 0x2 0x8 0x2 0x2 0x4 0x6 0x6040202 0xd0709 0x7586120a 0x70000f03 0x1f0000>;
  3298. nvidia,emc-burst-up-down-regs = <0xa 0xbe 0xff0038 0xff0038 0xff003c 0xff0090 0xff0041 0xff0090 0xff0041 0x280049 0xff0080 0xff0004 0xff0004 0x8002d 0xff 0xff0004 0xff0033 0xff0022 0xff0024 0xff0037 0xff 0x36 0xff00ff 0x36 0xff00ff 0xd400ff 0x510029 0xff00ff 0xff00ff 0xff0066 0xff0038>;
  3299. nvidia,emc-zcal-cnt-long = <0x42>;
  3300. nvidia,emc-acal-interval = <0x1fffff>;
  3301. nvidia,emc-ctt-term_ctrl = <0x802>;
  3302. nvidia,emc-cfg = <0x73340000>;
  3303. nvidia,emc-cfg-2 = <0x895>;
  3304. nvidia,emc-sel-dpd-ctrl = <0x40008>;
  3305. nvidia,emc-cfg-dig-dll = <0x2c0068>;
  3306. nvidia,emc-bgbias-ctl0 = <0x0>;
  3307. nvidia,emc-auto-cal-config2 = <0x0>;
  3308. nvidia,emc-auto-cal-config3 = <0x0>;
  3309. nvidia,emc-auto-cal-config = <0xa1430000>;
  3310. nvidia,emc-mode-0 = <0x80000521>;
  3311. nvidia,emc-mode-1 = <0x80100002>;
  3312. nvidia,emc-mode-2 = <0x80200000>;
  3313. nvidia,emc-mode-4 = <0x0>;
  3314. nvidia,emc-clock-latency-change = <0x884>;
  3315. };
  3316.  
  3317. emc-table@528000 {
  3318. compatible = "nvidia,tegra12-emc-table";
  3319. nvidia,revision = <0x19>;
  3320. nvidia,dvfs-version = "02_528000_NoCfgVersion_V5.0.18_V1.1";
  3321. clock-frequency = <0x80e80>;
  3322. nvidia,emc-min-mv = <0x370>;
  3323. nvidia,gk20a-min-mv = <0x366>;
  3324. nvidia,source = "pllm_ud";
  3325. nvidia,src-sel-reg = <0x80000000>;
  3326. nvidia,burst-regs-num = <0xa5>;
  3327. nvidia,burst-up-down-regs-num = <0x1f>;
  3328. nvidia,emc-registers = <0x18 0x88 0x0 0x10 0x6 0x6 0x9 0x2 0xd 0x6 0x6 0x2 0x2 0x0 0x3 0x3 0x6 0x2 0x0 0x1 0x9 0x30000 0x3 0x0 0x0 0x0 0x0 0x0 0x10 0x12 0x14 0xfd6 0x0 0x3f5 0x2 0xb 0x1 0x0 0x85 0x12 0x90 0x200 0x4 0x5 0x4 0x13 0x0 0x6 0x6 0x1017 0x0 0x0 0x0 0x1049b098 0xe01200b1 0x8000 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x44000 0x44000 0x0 0x44000 0x44000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x2 0x2 0x2 0x4 0x4 0x4 0x4 0x2 0x2 0x2 0x2 0x4 0x4 0x4 0x4 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0x100002a0 0x0 0x111111 0x123133d 0x0 0x0 0x77ffc085 0x303 0x81f1f108 0x7070004 0x0 0x16eeeee 0x51451420 0x514514 0x514514 0x51451400 0x606003f 0x0 0x0 0x20000 0x100 0x139000e 0x139000e 0x0 0x3 0x42a0 0x80002062 0xa 0xf000007 0x80000040 0x2 0x3 0xc 0x7 0xa 0x1 0x2 0x9 0x2 0x2 0x5 0x6 0x6050202 0x10090c 0x7428180d 0x70000f03 0x1f0000>;
  3329. nvidia,emc-burst-up-down-regs = <0xd 0xfd 0xc10038 0xc10038 0xc1003c 0xc10090 0xc10041 0xc10090 0xc10041 0x270049 0xc10080 0xc10004 0xc10004 0x80021 0xc1 0xc10004 0xc10026 0xc1001a 0xc10024 0xc10029 0xc1 0x36 0xc100c1 0x36 0xc100c1 0xd400ff 0x510029 0xc100c1 0xc100c1 0xc10065 0xc1002a>;
  3330. nvidia,emc-zcal-cnt-long = <0x42>;
  3331. nvidia,emc-acal-interval = <0x1fffff>;
  3332. nvidia,emc-ctt-term_ctrl = <0x802>;
  3333. nvidia,emc-cfg = <0x73300000>;
  3334. nvidia,emc-cfg-2 = <0x89d>;
  3335. nvidia,emc-sel-dpd-ctrl = <0x40008>;
  3336. nvidia,emc-cfg-dig-dll = <0xe0120069>;
  3337. nvidia,emc-bgbias-ctl0 = <0x0>;
  3338. nvidia,emc-auto-cal-config2 = <0x0>;
  3339. nvidia,emc-auto-cal-config3 = <0x0>;
  3340. nvidia,emc-auto-cal-config = <0xa1430000>;
  3341. nvidia,emc-mode-0 = <0x80000941>;
  3342. nvidia,emc-mode-1 = <0x80100002>;
  3343. nvidia,emc-mode-2 = <0x80200008>;
  3344. nvidia,emc-mode-4 = <0x0>;
  3345. nvidia,emc-clock-latency-change = <0x5a0>;
  3346. };
  3347.  
  3348. emc-table@600000 {
  3349. compatible = "nvidia,tegra12-emc-table";
  3350. nvidia,revision = <0x19>;
  3351. nvidia,dvfs-version = "02_600000_NoCfgVersion_V5.0.18_V1.1";
  3352. clock-frequency = <0x927c0>;
  3353. nvidia,emc-min-mv = <0x38e>;
  3354. nvidia,gk20a-min-mv = <0x38e>;
  3355. nvidia,source = "pllc_ud";
  3356. nvidia,src-sel-reg = <0xe0000000>;
  3357. nvidia,burst-regs-num = <0xa5>;
  3358. nvidia,burst-up-down-regs-num = <0x1f>;
  3359. nvidia,emc-registers = <0x1b 0x9b 0x0 0x13 0x7 0x7 0xb 0x3 0x10 0x7 0x7 0x2 0x2 0x0 0x5 0x5 0xa 0x2 0x0 0x3 0xb 0x70000 0x3 0x0 0x0 0x0 0x0 0x2 0x12 0x16 0x18 0x1208 0x0 0x482 0x2 0xd 0x1 0x0 0x97 0x15 0xa3 0x200 0x4 0x5 0x4 0x15 0x0 0x6 0x6 0x1248 0x0 0x0 0x0 0x1049b098 0xe00e00b1 0x8000 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3c000 0x3c000 0x0 0x3c000 0x3c000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x4 0x4 0x4 0x4 0x6 0x6 0x6 0x6 0x4 0x4 0x4 0x4 0x6 0x6 0x6 0x6 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0x100002a0 0x0 0x111111 0x121113d 0x0 0x0 0x77ffc085 0x303 0x81f1f108 0x7070004 0x0 0x16eeeee 0x51451420 0x514514 0x514514 0x51451400 0x606003f 0x0 0x0 0x20000 0x100 0x127000e 0x127000e 0x0 0x3 0x40a0 0x800024a9 0xe 0x9 0x80000040 0x3 0x4 0xe 0x9 0xb 0x1 0x3 0xb 0x2 0x2 0x5 0x7 0x7050202 0x130b0e 0x73a91b0f 0x70000f03 0x1f0000>;
  3360. nvidia,emc-burst-up-down-regs = <0xf 0x120 0xaa0038 0xaa0038 0xaa003c 0xaa0090 0xaa0041 0xaa0090 0xaa0041 0x270049 0xaa0080 0xaa0004 0xaa0004 0x8001d 0xaa 0xaa0004 0xaa0022 0xaa0018 0xaa0024 0xaa0024 0xaa 0x36 0xaa00aa 0x36 0xaa00aa 0xd400ff 0x510029 0xaa00aa 0xaa00aa 0xaa0065 0xaa0025>;
  3361. nvidia,emc-zcal-cnt-long = <0x42>;
  3362. nvidia,emc-acal-interval = <0x1fffff>;
  3363. nvidia,emc-ctt-term_ctrl = <0x802>;
  3364. nvidia,emc-cfg = <0x73300000>;
  3365. nvidia,emc-cfg-2 = <0x89d>;
  3366. nvidia,emc-sel-dpd-ctrl = <0x40008>;
  3367. nvidia,emc-cfg-dig-dll = <0xe00e0069>;
  3368. nvidia,emc-bgbias-ctl0 = <0x0>;
  3369. nvidia,emc-auto-cal-config2 = <0x0>;
  3370. nvidia,emc-auto-cal-config3 = <0x0>;
  3371. nvidia,emc-auto-cal-config = <0xa1430000>;
  3372. nvidia,emc-mode-0 = <0x80000b61>;
  3373. nvidia,emc-mode-1 = <0x80100002>;
  3374. nvidia,emc-mode-2 = <0x80200010>;
  3375. nvidia,emc-mode-4 = <0x0>;
  3376. nvidia,emc-clock-latency-change = <0x5a0>;
  3377. };
  3378.  
  3379. emc-table@792000 {
  3380. compatible = "nvidia,tegra12-emc-table";
  3381. nvidia,revision = <0x19>;
  3382. nvidia,dvfs-version = "02_792000_NoCfgVersion_V5.0.18_V1.1";
  3383. clock-frequency = <0xc15c0>;
  3384. nvidia,emc-min-mv = <0x3d4>;
  3385. nvidia,gk20a-min-mv = <0x3d4>;
  3386. nvidia,source = "pllm_ud";
  3387. nvidia,src-sel-reg = <0x80000000>;
  3388. nvidia,burst-regs-num = <0xa5>;
  3389. nvidia,burst-up-down-regs-num = <0x1f>;
  3390. nvidia,emc-registers = <0x24 0xcd 0x0 0x19 0xa 0x8 0xd 0x4 0x13 0xa 0xa 0x3 0x2 0x0 0x6 0x6 0xb 0x2 0x0 0x2 0xd 0x80000 0x4 0x0 0x0 0x0 0x0 0x1 0x14 0x18 0x1a 0x17e2 0x0 0x5f8 0x3 0x11 0x1 0x0 0xc7 0x18 0xd7 0x200 0x5 0x6 0x5 0x1d 0x0 0x8 0x8 0x1822 0x0 0x0 0x0 0x1049b098 0xe00700b1 0x8000 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x7 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x28000 0x28000 0x0 0x28000 0x28000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x7 0x7 0xa 0xa 0xa 0xa 0x7 0x7 0x7 0x7 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x100002a0 0x0 0x111111 0x120113d 0x0 0x0 0x77ffc085 0x606 0x81f1f108 0x7070004 0x0 0x16eeeee 0x61861820 0x555555 0x555555 0x61861800 0x606003f 0x0 0x0 0x20000 0x100 0xf7000e 0xf7000e 0x0 0x4 0x4080 0x80003012 0xf 0xe00000b 0x80000040 0x4 0x5 0x13 0xc 0xf 0x2 0x3 0xc 0x2 0x2 0x6 0x8 0x8060202 0x170e13 0x736c2414 0x70000f02 0x1f0000>;
  3391. nvidia,emc-burst-up-down-regs = <0x13 0x17c 0x810038 0x810038 0x81003c 0x810090 0x810041 0x810090 0x810041 0x270049 0x810080 0x810004 0x810004 0x80016 0x81 0x810004 0x810019 0x810018 0x810024 0x81001c 0x81 0x36 0x810081 0x36 0x810081 0xd400ff 0x510029 0x810081 0x810081 0x810065 0x81001c>;
  3392. nvidia,emc-zcal-cnt-long = <0x42>;
  3393. nvidia,emc-acal-interval = <0x1fffff>;
  3394. nvidia,emc-ctt-term_ctrl = <0x802>;
  3395. nvidia,emc-cfg = <0x73300000>;
  3396. nvidia,emc-cfg-2 = <0x89d>;
  3397. nvidia,emc-sel-dpd-ctrl = <0x40000>;
  3398. nvidia,emc-cfg-dig-dll = <0xe0070069>;
  3399. nvidia,emc-bgbias-ctl0 = <0x0>;
  3400. nvidia,emc-auto-cal-config2 = <0x0>;
  3401. nvidia,emc-auto-cal-config3 = <0x0>;
  3402. nvidia,emc-auto-cal-config = <0xa1430000>;
  3403. nvidia,emc-mode-0 = <0x80000d71>;
  3404. nvidia,emc-mode-1 = <0x80100002>;
  3405. nvidia,emc-mode-2 = <0x80200018>;
  3406. nvidia,emc-mode-4 = <0x0>;
  3407. nvidia,emc-clock-latency-change = <0x4b0>;
  3408. };
  3409.  
  3410. emc-table@924000 {
  3411. compatible = "nvidia,tegra12-emc-table";
  3412. nvidia,revision = <0x19>;
  3413. nvidia,dvfs-version = "02_924000_NoCfgVersion_V5.0.18_V1.1";
  3414. clock-frequency = <0xe1960>;
  3415. nvidia,emc-min-mv = <0x3f2>;
  3416. nvidia,gk20a-min-mv = <0x3f2>;
  3417. nvidia,source = "pllm_ud";
  3418. nvidia,src-sel-reg = <0x80000000>;
  3419. nvidia,burst-regs-num = <0xa5>;
  3420. nvidia,burst-up-down-regs-num = <0x1f>;
  3421. nvidia,emc-registers = <0x2b 0xf0 0x0 0x1e 0xb 0x9 0xf 0x5 0x16 0xb 0xb 0x4 0x2 0x0 0x7 0x7 0xd 0x2 0x0 0x2 0xf 0xa0000 0x4 0x0 0x0 0x0 0x0 0x1 0x16 0x1a 0x1c 0x1be7 0x0 0x6f9 0x4 0x15 0x1 0x0 0xe7 0x1b 0xfb 0x200 0x6 0x7 0x6 0x22 0x0 0xa 0xa 0x1c28 0x0 0x0 0x0 0x1049b898 0xe00400b1 0x8000 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x7fc008 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1c000 0x1c000 0x0 0x1c000 0x1c000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0x6 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x100002a0 0x0 0x111111 0x120113d 0x0 0x0 0x77ffc085 0x202 0x81f1f108 0x7070004 0x0 0x16eeeee 0x5d75d720 0x555555 0x555555 0x5d75d700 0x606003f 0x0 0x0 0x20000 0x128 0xcd000e 0xcd000e 0x0 0x4 0x4080 0x800037ea 0x11 0xe00000d 0x80000040 0x5 0x6 0x16 0xe 0x11 0x2 0x4 0xe 0x2 0x2 0x6 0x9 0x9060202 0x1a1016 0x734e2a17 0x70000f02 0x1f0000>;
  3422. nvidia,emc-burst-up-down-regs = <0x17 0x1bb 0x6e0038 0x6e0038 0x6e003c 0x6e0090 0x6e0041 0x6e0090 0x6e0041 0x270049 0x6e0080 0x6e0004 0x6e0004 0x80016 0x6e 0x6e0004 0x6e0019 0x6e0018 0x6e0024 0x6e001b 0x6e 0x36 0x6e006e 0x36 0x6e006e 0xd400ff 0x510029 0x6e006e 0x6e006e 0x6e0065 0x6e001c>;
  3423. nvidia,emc-zcal-cnt-long = <0x4c>;
  3424. nvidia,emc-acal-interval = <0x1fffff>;
  3425. nvidia,emc-ctt-term_ctrl = <0x802>;
  3426. nvidia,emc-cfg = <0x73300000>;
  3427. nvidia,emc-cfg-2 = <0x89d>;
  3428. nvidia,emc-sel-dpd-ctrl = <0x40000>;
  3429. nvidia,emc-cfg-dig-dll = <0xe0040069>;
  3430. nvidia,emc-bgbias-ctl0 = <0x0>;
  3431. nvidia,emc-auto-cal-config2 = <0x0>;
  3432. nvidia,emc-auto-cal-config3 = <0x0>;
  3433. nvidia,emc-auto-cal-config = <0xa1430000>;
  3434. nvidia,emc-mode-0 = <0x80000f15>;
  3435. nvidia,emc-mode-1 = <0x80100002>;
  3436. nvidia,emc-mode-2 = <0x80200020>;
  3437. nvidia,emc-mode-4 = <0x0>;
  3438. nvidia,emc-clock-latency-change = <0x49c>;
  3439. };
  3440. };
  3441.  
  3442. regulators {
  3443. compatible = "simple-bus";
  3444. #address-cells = <0x1>;
  3445. #size-cells = <0x0>;
  3446.  
  3447. regulator@0 {
  3448. compatible = "regulator-fixed";
  3449. reg = <0x0>;
  3450. regulator-name = "vdd_ac_bat";
  3451. regulator-min-microvolt = <0x4c4b40>;
  3452. regulator-max-microvolt = <0x4c4b40>;
  3453. regulator-always-on;
  3454. linux,phandle = <0xd>;
  3455. phandle = <0xd>;
  3456.  
  3457. consumers {
  3458.  
  3459. c1 {
  3460. regulator-consumer-supply = "vdd_sys_bl";
  3461. };
  3462.  
  3463. c2 {
  3464. regulator-consumer-supply = "vdd_wwan_mdm";
  3465. };
  3466. };
  3467. };
  3468.  
  3469. regulator@1 {
  3470. compatible = "regulator-fixed-sync";
  3471. reg = <0x1>;
  3472. regulator-name = "en-lcd-bl";
  3473. regulator-min-microvolt = <0x4c4b40>;
  3474. regulator-max-microvolt = <0x4c4b40>;
  3475. enable-active-high;
  3476. gpio = <0x7 0x3a 0x0>;
  3477. regulator-boot-on;
  3478.  
  3479. consumers {
  3480.  
  3481. c1 {
  3482. regulator-consumer-supply = "vdd_lcd_bl_en";
  3483. regulator-consumer-device = "tegradc.0";
  3484. };
  3485. };
  3486. };
  3487.  
  3488. regulator@2 {
  3489. compatible = "regulator-fixed-sync";
  3490. reg = <0x2>;
  3491. regulator-name = "vddio_sd";
  3492. regulator-min-microvolt = <0x325aa0>;
  3493. regulator-max-microvolt = <0x325aa0>;
  3494. gpio = <0x7 0x88 0x0>;
  3495. enable-active-high;
  3496. vin-supply = <0x9>;
  3497.  
  3498. consumers {
  3499.  
  3500. c1 {
  3501. regulator-consumer-supply = "vddio_sd_slot";
  3502. regulator-consumer-device = "sdhci-tegra.2";
  3503. };
  3504. };
  3505. };
  3506.  
  3507. regulator@3 {
  3508. compatible = "regulator-fixed-sync";
  3509. reg = <0x3>;
  3510. regulator-name = "vddio_dvdd_lcd";
  3511. regulator-min-microvolt = <0x1b7740>;
  3512. regulator-max-microvolt = <0x1b7740>;
  3513. gpio = <0x17 0x6 0x0>;
  3514. enable-active-high;
  3515. regulator-boot-on;
  3516. vin-supply = <0x8>;
  3517.  
  3518. consumers {
  3519.  
  3520. c1 {
  3521. regulator-consumer-supply = "dvdd_lcd";
  3522. regulator-consumer-device = "tegradc.0";
  3523. };
  3524.  
  3525. c2 {
  3526. regulator-consumer-supply = "vdd_lcd_1v8_s";
  3527. };
  3528. };
  3529. };
  3530.  
  3531. regulator@4 {
  3532. compatible = "regulator-fixed-sync";
  3533. reg = <0x4>;
  3534. regulator-name = "vdd_cam_af";
  3535. regulator-min-microvolt = <0x1b7740>;
  3536. regulator-max-microvolt = <0x1b7740>;
  3537. gpio = <0x17 0x4 0x0>;
  3538. enable-active-high;
  3539. vin-supply = <0x8>;
  3540.  
  3541. consumers {
  3542.  
  3543. c1 {
  3544. regulator-consumer-supply = "vif";
  3545. regulator-consumer-device = "2-0010";
  3546. };
  3547.  
  3548. c2 {
  3549. regulator-consumer-supply = "vif";
  3550. regulator-consumer-device = "2-0036";
  3551. };
  3552.  
  3553. c3 {
  3554. regulator-consumer-supply = "vif";
  3555. regulator-consumer-device = "2-0048";
  3556. };
  3557.  
  3558. c4 {
  3559. regulator-consumer-supply = "vddio_cam";
  3560. regulator-consumer-device = "tegra_camera";
  3561. };
  3562.  
  3563. c5 {
  3564. regulator-consumer-supply = "vddio_cam";
  3565. regulator-consumer-device = "vi";
  3566. };
  3567.  
  3568. c6 {
  3569. regulator-consumer-supply = "vdd_cam_1v8_mb";
  3570. };
  3571.  
  3572. c7 {
  3573. regulator-consumer-supply = "dovdd";
  3574. regulator-consumer-device = "2-0010";
  3575. };
  3576.  
  3577. c8 {
  3578. regulator-consumer-supply = "vif";
  3579. regulator-consumer-device = "2-000c";
  3580. };
  3581.  
  3582. c9 {
  3583. regulator-consumer-supply = "vdd_i2c";
  3584. regulator-consumer-device = "2-000c";
  3585. };
  3586.  
  3587. c10 {
  3588. regulator-consumer-supply = "pwrdet_cam";
  3589. };
  3590.  
  3591. c11 {
  3592. regulator-consumer-supply = "vi2c";
  3593. regulator-consumer-device = "2-0030";
  3594. };
  3595. };
  3596. };
  3597.  
  3598. regulator@5 {
  3599. compatible = "regulator-fixed-sync";
  3600. reg = <0x5>;
  3601. regulator-name = "vdd-hdmi-n5";
  3602. regulator-min-microvolt = <0x124f80>;
  3603. regulator-max-microvolt = <0x124f80>;
  3604. enable-active-high;
  3605. gpio = <0x7 0x6d 0x0>;
  3606. vin-supply = <0xf>;
  3607.  
  3608. consumers {
  3609.  
  3610. c1 {
  3611. regulator-consumer-supply = "avdd_hdmi_pll";
  3612. regulator-consumer-device = "tegradc.1";
  3613. };
  3614. };
  3615. };
  3616.  
  3617. regulator@6 {
  3618. compatible = "regulator-fixed-sync";
  3619. reg = <0x6>;
  3620. regulator-name = "vddio_hdmi_5v0";
  3621. regulator-min-microvolt = <0x4c4b40>;
  3622. regulator-max-microvolt = <0x4c4b40>;
  3623. gpio = <0x7 0x56 0x0>;
  3624. enable-active-high;
  3625. vin-supply = <0x18>;
  3626.  
  3627. consumers {
  3628.  
  3629. c1 {
  3630. regulator-consumer-supply = "vdd_hdmi_5v0";
  3631. regulator-consumer-device = "tegradc.1";
  3632. };
  3633. };
  3634. };
  3635.  
  3636. regulator@7 {
  3637. compatible = "regulator-fixed-sync";
  3638. reg = <0x7>;
  3639. regulator-name = "vdd_ts_1v8";
  3640. regulator-min-microvolt = <0x1b7740>;
  3641. regulator-max-microvolt = <0x1b7740>;
  3642. gpio = <0x7 0x51 0x0>;
  3643. enable-active-high;
  3644. vin-supply = <0x8>;
  3645.  
  3646. consumers {
  3647.  
  3648. c1 {
  3649. regulator-consumer-supply = "dvdd";
  3650. regulator-consumer-device = "spi0.0";
  3651. };
  3652. };
  3653. };
  3654.  
  3655. regulator@8 {
  3656. compatible = "regulator-fixed-sync";
  3657. reg = <0x8>;
  3658. regulator-name = "avdd_ts_3v3";
  3659. regulator-min-microvolt = <0x325aa0>;
  3660. regulator-max-microvolt = <0x325aa0>;
  3661. gpio = <0x17 0x2 0x0>;
  3662. enable-active-high;
  3663. vin-supply = <0x19>;
  3664. regulator-disable-parent-after-enable;
  3665.  
  3666. consumers {
  3667.  
  3668. c1 {
  3669. regulator-consumer-supply = "avdd";
  3670. regulator-consumer-device = "spi0.0";
  3671. };
  3672. };
  3673. };
  3674. };
  3675.  
  3676. gpio-keys {
  3677. compatible = "gpio-keys";
  3678.  
  3679. camera_focus {
  3680. label = "Camera Focus";
  3681. gpios = <0x7 0x82 0x1>;
  3682. linux,code = <0x210>;
  3683. };
  3684.  
  3685. power {
  3686. label = "Power";
  3687. gpios = <0x7 0x80 0x1>;
  3688. linux,code = <0x74>;
  3689. gpio-key,wakeup;
  3690. };
  3691.  
  3692. volume_down {
  3693. label = "Volume Down";
  3694. gpios = <0x7 0x87 0x1>;
  3695. linux,code = <0x72>;
  3696. };
  3697.  
  3698. volume_up {
  3699. label = "Volume Up";
  3700. gpios = <0x7 0x86 0x1>;
  3701. linux,code = <0x73>;
  3702. };
  3703.  
  3704. sw_table_mode {
  3705. label = "SW Table Mode";
  3706. gpios = <0x7 0xb3 0x0>;
  3707. linux,code = <0x1>;
  3708. linux,input-type = <0x5>;
  3709. gpio-key,wakeup;
  3710. debounce-interval = <0xc8>;
  3711. };
  3712.  
  3713. sw_lid {
  3714. label = "SW LID";
  3715. gpios = <0x7 0x8c 0x1>;
  3716. linux,code = <0x0>;
  3717. linux,input-type = <0x5>;
  3718. gpio-key,wakeup;
  3719. debounce-interval = <0x12c>;
  3720. };
  3721. };
  3722.  
  3723. sysedp_batmon_calc {
  3724. compatible = "nvidia,tegra124-sysedp_batmon_calc";
  3725. ocv_lut = <0x64 0x41f514 0x50 0x3e5309 0x3c 0x3bb7b3 0x28 0x39e900 0x14 0x387634 0x0 0x3567e0>;
  3726. ibat_lut = <0x258 0x2328 0xfffffda8 0x2328 0xfffffd44 0x0>;
  3727. rbat_data = <0x105d9 0x105d9 0xfe3a 0x1001b 0x12208 0x18b8e 0x22e5d 0x22e5d 0x105bc 0x105bc 0xfe5e 0xfb7d 0x1203b 0x1891e 0x22af1 0x22af1 0x1061f 0x1061f 0xff5b 0xfa00 0x1147a 0x16114 0x1c089 0x1c089 0x10750 0x10750 0x10166 0xfc15 0x11255 0x1548e 0x197f1 0x197f1 0x10ab0 0x10ab0 0x1062d 0x10199 0x117f2 0x15ef2 0x1a98e 0x1a98e 0x11a88 0x11a88 0x118bd 0x11772 0x13f8b 0x175ec 0x1cd9e 0x1cd9e>;
  3728. temp_axis = <0x258 0x1c2 0x12c 0xdc 0x96 0x32 0x0 0xffffff9c>;
  3729. capacity_axis = <0x64 0x50 0x3c 0x28 0x14 0x0>;
  3730. power_supply = "battery";
  3731. r_const = <0x9c40>;
  3732. vsys_min = <0x2dc6c0>;
  3733. };
  3734.  
  3735. cpu_dfll_board_params {
  3736. sample-rate = <0x30d4>;
  3737. fixed-output-forcing;
  3738. cf = <0xa>;
  3739. ci = <0x0>;
  3740. cg = <0x2>;
  3741. droop-cut-value = <0xf>;
  3742. droop-restore-ramp = <0x0>;
  3743. scale-out-ramp = <0x0>;
  3744. linux,phandle = <0x15>;
  3745. phandle = <0x15>;
  3746. };
  3747.  
  3748. cpu_dfll_pmic_integration {
  3749. pmic-i2c-address = <0xb0>;
  3750. pmic-i2c-voltage-register = <0x23>;
  3751. i2c-fs-rate = <0x61a80>;
  3752. sel-conversion-slope = <0x1>;
  3753. linux,phandle = <0x16>;
  3754. phandle = <0x16>;
  3755. };
  3756.  
  3757. usb-devices {
  3758.  
  3759. maxim-charger {
  3760. compatible = "maxim,max14675";
  3761. maxim,max-board-vbus-voltage-uv = <0xb71b00>;
  3762. };
  3763. };
  3764.  
  3765. chosen {
  3766. bootargs = "tegraid=40.0.0.00.00 vmalloc=256M video=tegrafb console=ttyS0,115200n8 earlyprintk";
  3767. linux,initrd-start = <0x85000000>;
  3768. linux,initrd-end = <0x851bc400>;
  3769. };
  3770. };
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