dram

https://github.com/integralfx/MemTestHelper/blob/master/DDR4%20OC%20Guide.md
soc voltage 1.0 to 1.1v
cldo_vddg
	soc should be at least 40mV above cldo_vddg

keep tRCDRD and tRCDWR the same
for even tCL, need to enable gear down mode
for odd tCL, disable GDM



set loose high timings
increase dram freq until unstable
tighten timings


start with 1.10v soc
set dram to 1.4v


set primary timings to 16-20-20-40 (tCL tRCD tRP tRAS), tCLW to 16
increase DRAM frequency until it doesn't boot
	set FCLK to half of effective DRAM frequency



run tm5 stress test

either try higher freq or lower timings
	for higher freq, loosen primary timing to 18 22 22 42, tCWL to 18
	dram voltage to 1.45
	do above steps for increasing dram freq

tightning timing
	run benchmark and memtest after each change to ensure performance is improving and stable

tighting secondary timings first
tRRDS tRRDL tFAW	safe 6 6 24	tight 4 6 16	extreme 4 4 16
tWR			safe 16		tight 12	extreme 10

min tFAW is tRRDS * 4


primary timings
tCL, drop by 1 until instable
same with tRCD and tRP
after all 3 timings are as tight
	tRAS = tCL + tRCD(RD) + 2, tRC = tRP + tRAS + x, x can be 8

tRFC in ns, 140-180 for b die
(140 or 180) * ddr_freq / 2000
so 180 * 3600 / 2000 = 324


tWTRS tWTRL	safe 4 12	tight 4 10	extreme 4 8
tRTP		safe 12		tight 10	extrme 8
tCWL		safe TCL	tight tCL-1	extreme tCL-2


tertiaries
tRDRDSCL tWRWRSCL 	safe 4 4	tight 3 3	extreme 2 2

tRDRD_sg/dg/dr/dd	safe 8/4/8/8	tight 7/4/7/7	extrme 6/4/6/6
tWRWR_sg/dg/dr/dd	safe 8/4/8/8	tight 7/4/7/7	extreme 6/4/6/6

tWRRD_sg/dg
tRDWR_sg/dg/dr/dd drop them all by 1 until unstable, usually run them all the same e.g. 9/9/9/9

tRDRD_dr/dd can be lowered a step further to 5
tWRWR_sg6 can cause write regression over tWRWR_sg 7
tREFI higher is better normally



command rate
try GDM disabled, CR 1
	adjust setup times then drive strengths if usntable
	setup csodt 50 addrcmdsetup 50 ckesetup 50
	strength clkdrv 60 addrcmddrv20 csodtcmddrv 20 ckedrv 30