`timescale 1ns/100ps
module lab1_2 (
    input wire [3:0] source_0,
    input wire [3:0] source_1,
    input wire [3:0] source_2,
    input wire [3:0] source_3,
    input wire [1:0] op_0,
    input wire [1:0] op_1,
    input wire [1:0] request,
    output reg [3:0] result
);
    reg [1:0] op_temp;

    always @(*) begin
        if (request[0] == 1'b1 && request[1] == 1'b1) begin
            op_temp = op_0;
        end
        else if (request[0] == 1'b1 && request[1] != 1'b1) begin
            op_temp = op_0;
        end
        else if (request[1] == 1'b1 && request[0] != 1'b1) begin
            op_temp = op_1;
        end

        lab1_1 lab1_1_inst (
            op(op_temp),
            a((request[0]) ? source_0 : source_2),
            b((request[0]) ? source_1 : source_3),
            d(result)
        );
    end
    /* Note that result can be either reg or wire.
    * It depends on how you design your module. */
    // add your design here
endmodule