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nelson33

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Sep 16th, 2023
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VeriLog 0.98 KB | Source Code | 0 0
  1. `timescale 1ns/100ps
  2. module lab1_2 (
  3.     input wire [3:0] source_0,
  4.     input wire [3:0] source_1,
  5.     input wire [3:0] source_2,
  6.     input wire [3:0] source_3,
  7.     input wire [1:0] op_0,
  8.     input wire [1:0] op_1,
  9.     input wire [1:0] request,
  10.     output reg [3:0] result
  11. );
  12.     reg [1:0] op_temp;
  13.  
  14.     always @(*) begin
  15.         if (request[0] == 1'b1 && request[1] == 1'b1) begin
  16.             op_temp = op_0;
  17.         end
  18.         else if (request[0] == 1'b1 && request[1] != 1'b1) begin
  19.             op_temp = op_0;
  20.         end
  21.         else if (request[1] == 1'b1 && request[0] != 1'b1) begin
  22.             op_temp = op_1;
  23.         end
  24.  
  25.         lab1_1 lab1_1_inst (
  26.             op(op_temp),
  27.             a((request[0]) ? source_0 : source_2),
  28.             b((request[0]) ? source_1 : source_3),
  29.             d(result)
  30.         );
  31.     end
  32.     /* Note that result can be either reg or wire.
  33.     * It depends on how you design your module. */
  34.     // add your design here
  35. endmodule
  36.  
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