module BCDcounter2(clk,en1,en2,eg,cl,Q,rcy);
    input clk;
    input en1;
    input en2;
    input eg;
    input cl;
    output [3:0] Q;
    output rcy;

    reg [3:0] Q;

wire ccy;
assign ccy = (Q == 9);
assign rcy = ccy & en1;
always @(posedge clk)
begin
   if (cl)
      Q <= 0;
   else
    if ((en1 & en2) | eg)
    begin
       if (!ccy) Q <= Q + 1;
       else Q <= 0;
        end
    else        Q <= Q;
end
endmodule