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  1. 5.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
  2. Processing micro80_top.CPU.EU_1Kx18_DP.mem_array:
  3. Properties: ports=2 bits=18432 rports=2 wports=0 dbits=18 abits=10 words=1024
  4. Checking rule #1 for bram type $__GW1NR_SDP (variant 1):
  5. Bram geometry: abits=10 dbits=16 wports=0 rports=0
  6. Estimated number of duplicates for more read ports: dups=1
  7. Metrics for $__GW1NR_SDP: awaste=0 dwaste=14 bwaste=14336 waste=14336 efficiency=56
  8. Rule #1 for bram type $__GW1NR_SDP (variant 1) accepted.
  9. Mapping to bram type $__GW1NR_SDP (variant 1):
  10. Read port #0 is in clock domain !~async~.
  11. Bram port B1.1 has incompatible clock type.
  12. Failed to map read port #0.
  13. Mapping to bram type $__GW1NR_SDP failed.
  14. Checking rule #1 for bram type $__GW1NR_SDP (variant 2):
  15. Bram geometry: abits=11 dbits=8 wports=0 rports=0
  16. Estimated number of duplicates for more read ports: dups=1
  17. Metrics for $__GW1NR_SDP: awaste=1024 dwaste=6 bwaste=14336 waste=14336 efficiency=37
  18. Rule #1 for bram type $__GW1NR_SDP (variant 2) accepted.
  19. Mapping to bram type $__GW1NR_SDP (variant 2):
  20. Read port #0 is in clock domain !~async~.
  21. Bram port B1.1 has incompatible clock type.
  22. Failed to map read port #0.
  23. Mapping to bram type $__GW1NR_SDP failed.
  24. Checking rule #1 for bram type $__GW1NR_SDP (variant 3):
  25. Bram geometry: abits=12 dbits=4 wports=0 rports=0
  26. Estimated number of duplicates for more read ports: dups=1
  27. Metrics for $__GW1NR_SDP: awaste=3072 dwaste=2 bwaste=14336 waste=14336 efficiency=22
  28. Rule #1 for bram type $__GW1NR_SDP (variant 3) accepted.
  29. Mapping to bram type $__GW1NR_SDP (variant 3):
  30. Read port #0 is in clock domain !~async~.
  31. Bram port B1.1 has incompatible clock type.
  32. Failed to map read port #0.
  33. Mapping to bram type $__GW1NR_SDP failed.
  34. Checking rule #1 for bram type $__GW1NR_SDP (variant 4):
  35. Bram geometry: abits=13 dbits=2 wports=0 rports=0
  36. Estimated number of duplicates for more read ports: dups=1
  37. Metrics for $__GW1NR_SDP: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12
  38. Rule #1 for bram type $__GW1NR_SDP (variant 4) accepted.
  39. Mapping to bram type $__GW1NR_SDP (variant 4):
  40. Read port #0 is in clock domain !~async~.
  41. Bram port B1.1 has incompatible clock type.
  42. Failed to map read port #0.
  43. Mapping to bram type $__GW1NR_SDP failed.
  44. Checking rule #1 for bram type $__GW1NR_SDP (variant 5):
  45. Bram geometry: abits=14 dbits=1 wports=0 rports=0
  46. Estimated number of duplicates for more read ports: dups=1
  47. Metrics for $__GW1NR_SDP: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6
  48. Rule #1 for bram type $__GW1NR_SDP (variant 5) accepted.
  49. Mapping to bram type $__GW1NR_SDP (variant 5):
  50. Read port #0 is in clock domain !~async~.
  51. Bram port B1.1 has incompatible clock type.
  52. Failed to map read port #0.
  53. Mapping to bram type $__GW1NR_SDP failed.
  54. Checking rule #1 for bram type $__GW1NR_SDP (variant 6):
  55. Bram geometry: abits=9 dbits=32 wports=0 rports=0
  56. Estimated number of duplicates for more read ports: dups=1
  57. Metrics for $__GW1NR_SDP: awaste=0 dwaste=14 bwaste=7168 waste=7168 efficiency=56
  58. Rule #1 for bram type $__GW1NR_SDP (variant 6) accepted.
  59. Mapping to bram type $__GW1NR_SDP (variant 6):
  60. Read port #0 is in clock domain !~async~.
  61. Bram port B1.1 has incompatible clock type.
  62. Failed to map read port #0.
  63. Mapping to bram type $__GW1NR_SDP failed.
  64. No acceptable bram resources found.
  65. Processing micro80_top.debug_ram.mem_array:
  66. Properties: ports=2 bits=32768 rports=1 wports=1 dbits=8 abits=12 words=4096
  67. Checking rule #1 for bram type $__GW1NR_SDP (variant 1):
  68. Bram geometry: abits=10 dbits=16 wports=0 rports=0
  69. Estimated number of duplicates for more read ports: dups=1
  70. Metrics for $__GW1NR_SDP: awaste=0 dwaste=8 bwaste=8192 waste=8192 efficiency=50
  71. Rule #1 for bram type $__GW1NR_SDP (variant 1) accepted.
  72. Mapping to bram type $__GW1NR_SDP (variant 1):
  73. Shuffle bit order to accommodate enable buckets of size 8..
  74. Results of bit order shuffling: 0 1 2 3 4 5 6 7
  75. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  76. Mapped to bram port A1.
  77. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  78. Mapped to bram port B1.1.
  79. Updated properties: dups=1 waste=8192 efficiency=50
  80. Storing for later selection.
  81. Checking rule #1 for bram type $__GW1NR_SDP (variant 2):
  82. Bram geometry: abits=11 dbits=8 wports=0 rports=0
  83. Estimated number of duplicates for more read ports: dups=1
  84. Metrics for $__GW1NR_SDP: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
  85. Rule #1 for bram type $__GW1NR_SDP (variant 2) accepted.
  86. Mapping to bram type $__GW1NR_SDP (variant 2):
  87. Shuffle bit order to accommodate enable buckets of size 8..
  88. Results of bit order shuffling: 0 1 2 3 4 5 6 7
  89. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  90. Mapped to bram port A1.
  91. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  92. Mapped to bram port B1.1.
  93. Updated properties: dups=1 waste=0 efficiency=100
  94. Storing for later selection.
  95. Checking rule #1 for bram type $__GW1NR_SDP (variant 3):
  96. Bram geometry: abits=12 dbits=4 wports=0 rports=0
  97. Estimated number of duplicates for more read ports: dups=1
  98. Metrics for $__GW1NR_SDP: awaste=0 dwaste=0 bwaste=0 waste=0 efficiency=100
  99. Rule #1 for bram type $__GW1NR_SDP (variant 3) accepted.
  100. Mapping to bram type $__GW1NR_SDP (variant 3):
  101. Shuffle bit order to accommodate enable buckets of size 4..
  102. Results of bit order shuffling: 0 1 2 3 4 5 6 7
  103. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  104. Mapped to bram port A1.
  105. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  106. Mapped to bram port B1.1.
  107. Updated properties: dups=1 waste=0 efficiency=100
  108. Storing for later selection.
  109. Checking rule #1 for bram type $__GW1NR_SDP (variant 4):
  110. Bram geometry: abits=13 dbits=2 wports=0 rports=0
  111. Estimated number of duplicates for more read ports: dups=1
  112. Metrics for $__GW1NR_SDP: awaste=4096 dwaste=0 bwaste=8192 waste=8192 efficiency=50
  113. Rule #1 for bram type $__GW1NR_SDP (variant 4) accepted.
  114. Mapping to bram type $__GW1NR_SDP (variant 4):
  115. Shuffle bit order to accommodate enable buckets of size 2..
  116. Results of bit order shuffling: 0 1 2 3 4 5 6 7
  117. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  118. Mapped to bram port A1.
  119. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  120. Mapped to bram port B1.1.
  121. Updated properties: dups=1 waste=8192 efficiency=50
  122. Storing for later selection.
  123. Checking rule #1 for bram type $__GW1NR_SDP (variant 5):
  124. Bram geometry: abits=14 dbits=1 wports=0 rports=0
  125. Estimated number of duplicates for more read ports: dups=1
  126. Metrics for $__GW1NR_SDP: awaste=12288 dwaste=0 bwaste=12288 waste=12288 efficiency=25
  127. Rule #1 for bram type $__GW1NR_SDP (variant 5) accepted.
  128. Mapping to bram type $__GW1NR_SDP (variant 5):
  129. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  130. Mapped to bram port A1.
  131. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  132. Mapped to bram port B1.1.
  133. Updated properties: dups=1 waste=12288 efficiency=25
  134. Storing for later selection.
  135. Checking rule #1 for bram type $__GW1NR_SDP (variant 6):
  136. Bram geometry: abits=9 dbits=32 wports=0 rports=0
  137. Estimated number of duplicates for more read ports: dups=1
  138. Metrics for $__GW1NR_SDP: awaste=0 dwaste=24 bwaste=12288 waste=12288 efficiency=25
  139. Rule #1 for bram type $__GW1NR_SDP (variant 6) accepted.
  140. Mapping to bram type $__GW1NR_SDP (variant 6):
  141. Shuffle bit order to accommodate enable buckets of size 8..
  142. Results of bit order shuffling: 0 1 2 3 4 5 6 7
  143. Write port #0 is in clock domain \XTAL_24MHZ_CLK.
  144. Mapped to bram port A1.
  145. Read port #0 is in clock domain \XTAL_24MHZ_CLK.
  146. Mapped to bram port B1.1.
  147. Updated properties: dups=1 waste=12288 efficiency=25
  148. Storing for later selection.
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