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-- Company:
-- Engineer:
--
-- Create Date:    17:02:27 04/18/2017
-- Design Name:
-- Module Name:    D_flip_flop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity D_flip_flop is
    Port ( D : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           clear : in  STD_LOGIC;
           Q : out  STD_LOGIC);
end D_flip_flop;

architecture Behavioral of D_flip_flop is

begin
  process(clk,clear)
    begin
	      if clear='0' then
			     Q<='0';
				elsif clk'event and clk='1' then
				  Q<=D;
				end if;
		end process;

end Behavioral;