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Seraph08
Sep 22nd, 2016
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  1. david@RosettaStoned:~/Android/cyanogenmod/device/oneplus/oneplus2$ git diff grarak/cm-14.0 seraph/cm-14.0
  2. diff --git a/BoardConfig.mk b/BoardConfig.mk
  3. index cd6441c..7e4569f 100644
  4. --- a/BoardConfig.mk
  5. +++ b/BoardConfig.mk
  6. @@ -45,7 +45,7 @@ TARGET_ARCH := arm64
  7. TARGET_ARCH_VARIANT := armv8-a
  8. TARGET_CPU_ABI := arm64-v8a
  9. TARGET_CPU_ABI2 :=
  10. -TARGET_CPU_VARIANT := generic
  11. +TARGET_CPU_VARIANT := cortex-a53
  12.  
  13. TARGET_2ND_ARCH := arm
  14. TARGET_2ND_ARCH_VARIANT := armv7-a-neon
  15. @@ -53,8 +53,13 @@ TARGET_2ND_CPU_ABI := armeabi-v7a
  16. TARGET_2ND_CPU_ABI2 := armeabi
  17. TARGET_2ND_CPU_VARIANT := cortex-a53.a57
  18.  
  19. +TARGET_CPU_CORTEX_A53 := true
  20. +
  21. +TARGET_BOARD_SUFFIX := _64
  22. TARGET_USES_64_BIT_BINDER := true
  23.  
  24. +BOARD_GLOBAL_CFLAGS += -DUSE_RIL_VERSION_11 -DCOMPAT_SENSORS_M
  25. +
  26. # Kernel
  27. BOARD_KERNEL_CMDLINE := androidboot.hardware=qcom user_debug=31 msm_rtb.filter=0x37 ehci-hcd.park=3 lpm_levels.sleep_disabled=1 boot_cpus=0-3 androidboot.selinux=permissive
  28. BOARD_KERNEL_BASE := 0x00000000
  29. @@ -116,6 +121,9 @@ BOARD_USES_QCNE := true
  30. # Cpusets
  31. ENABLE_CPUSETS := true
  32.  
  33. +# Crypto
  34. +TARGET_HW_DISK_ENCRYPTION := true
  35. +
  36. # GPS
  37. TARGET_NO_RPC := true
  38. USE_DEVICE_SPECIFIC_GPS := true
  39. @@ -139,6 +147,7 @@ TARGET_SPECIFIC_HEADER_PATH := $(PLATFORM_PATH)/include
  40. # Init
  41. TARGET_INIT_VENDOR_LIB := libinit_oneplus2
  42. TARGET_PLATFORM_DEVICE_BASE := /devices/soc.0/
  43. +TARGET_LIBINIT_DEFINES_FILE := $(PLATFORM_PATH)/init/init_oneplus2.cpp
  44.  
  45. # Keystore
  46. TARGET_PROVIDES_KEYMASTER := true
  47. @@ -148,6 +157,7 @@ TARGET_PROVIDES_LIBLIGHT := true
  48.  
  49. # RIL
  50. TARGET_RIL_VARIANT := caf
  51. +BOARD_GLOBAL_CFLAGS += -DUSE_RIL_VERSION_11
  52.  
  53. # RPC
  54. TARGET_NO_RPC := true
  55. @@ -155,6 +165,7 @@ TARGET_NO_RPC := true
  56. # Sensors
  57. USE_SENSOR_MULTI_HAL := true
  58. BOARD_GLOBAL_CFLAGS += -DCOMPAT_SENSORS_M
  59. +TARGET_PREFERS_AOSP_ROTATION_SENSOR := true
  60.  
  61. # Enable dexpreopt to speed boot time
  62. ifeq ($(HOST_OS),linux)
  63. diff --git a/README.md b/README.md
  64. new file mode 100644
  65. index 0000000..3a63e6f
  66. --- /dev/null
  67. +++ b/README.md
  68. @@ -0,0 +1,21 @@
  69. +Copyright 2015 - The CyanogenMod Project
  70. +
  71. +Device configuration for OnePlus Two.
  72. +=====================================
  73. +
  74. +Basic | Spec Sheet
  75. +-------:|:-------------------------
  76. +CPU | Quad-core 1.8 GHz ARM® Cortex™ A57 and quad-core 1.5 GHz ARM® Cortex™ A53
  77. +CHIPSET | Qualcomm MSM8994 Snapdragon 810
  78. +GPU | Adreno 430
  79. +Memory | 3/4 GB
  80. +Shipped Android Version | 5.1.1
  81. +Storage | 16/64 GB
  82. +Battery | 3300 mAh (non-removable)
  83. +Dimensions | 151.8 x 74.9 x 9.85 mm
  84. +Display | 1.920 x 1.080
  85. +Rear Camera | 13 MP, dual-LED flash
  86. +Front Camera | 5 MP
  87. +Release Date | July 2015
  88. +
  89. +![OnePlus Two](http://cdn2.gsmarena.com/vv/pics/oneplus/oneplus-two-1.jpg "OnePlus Two")
  90. diff --git a/audio/acdb/MTP_Bluetooth_cal.acdb b/audio/acdb/MTP_Bluetooth_cal.acdb
  91. new file mode 100644
  92. index 0000000..a97a161
  93. Binary files /dev/null and b/audio/acdb/MTP_Bluetooth_cal.acdb differ
  94. diff --git a/audio/acdb/MTP_General_cal.acdb b/audio/acdb/MTP_General_cal.acdb
  95. new file mode 100644
  96. index 0000000..a9077af
  97. Binary files /dev/null and b/audio/acdb/MTP_General_cal.acdb differ
  98. diff --git a/audio/acdb/MTP_Global_cal.acdb b/audio/acdb/MTP_Global_cal.acdb
  99. new file mode 100644
  100. index 0000000..cdf5719
  101. Binary files /dev/null and b/audio/acdb/MTP_Global_cal.acdb differ
  102. diff --git a/audio/acdb/MTP_Handset_cal.acdb b/audio/acdb/MTP_Handset_cal.acdb
  103. new file mode 100644
  104. index 0000000..69518bb
  105. Binary files /dev/null and b/audio/acdb/MTP_Handset_cal.acdb differ
  106. diff --git a/audio/acdb/MTP_Hdmi_cal.acdb b/audio/acdb/MTP_Hdmi_cal.acdb
  107. new file mode 100644
  108. index 0000000..655a4b4
  109. Binary files /dev/null and b/audio/acdb/MTP_Hdmi_cal.acdb differ
  110. diff --git a/audio/acdb/MTP_Headset_cal.acdb b/audio/acdb/MTP_Headset_cal.acdb
  111. new file mode 100644
  112. index 0000000..68ed6fb
  113. Binary files /dev/null and b/audio/acdb/MTP_Headset_cal.acdb differ
  114. diff --git a/audio/acdb/MTP_Speaker_cal.acdb b/audio/acdb/MTP_Speaker_cal.acdb
  115. new file mode 100644
  116. index 0000000..a8ac726
  117. Binary files /dev/null and b/audio/acdb/MTP_Speaker_cal.acdb differ
  118. diff --git a/audio/audio_policy.conf b/audio/audio_policy.conf
  119. index bff56cc..1fa881e 100644
  120. --- a/audio/audio_policy.conf
  121. +++ b/audio/audio_policy.conf
  122. @@ -67,9 +67,21 @@ audio_hw_modules {
  123. #ifndef VENDOR_EDIT
  124. #lifei@OnePlus.MultiMediaService, 2015/12/23,add MP2 offload playback
  125. #formats AUDIO_FORMAT_MP3|AUDIO_FORMAT_AC3|AUDIO_FORMAT_E_AC3|AUDIO_FORMAT_PCM_24_BIT_OFFLOAD|AUDIO_FORMAT_FLAC|AUDIO_FORMAT_AAC_LC|AUDIO_FORMAT_AAC_HE_V1|AUDIO_FORMAT_AAC_HE_V2
  126. -#else
  127. +
  128. + #else
  129. +
  130. + formats AUDIO_FORMAT_MP3|AUDIO_FORMAT_AC3|AUDIO_FORMAT_E_AC3|AUDIO_FORMAT_PCM_24_BIT_OFFLOAD|AUDIO_FORMAT_FLAC|AUDIO_FORMAT_AAC_LC|AUDIO_FORMAT_AAC_HE_V1|AUDIO_FORMAT_AAC_HE_V2|AUDIO_FORMAT_MP2
  131. +
  132. + formats AUDIO_FORMAT_MP3|AUDIO_FORMAT_AC3|AUDIO_FORMAT_E_AC3|AUDIO_FORMAT_PCM_24_BIT_OFFLOAD|AUDIO_FORMAT_FLAC|AUDIO_FORMAT_AAC_LC|AUDIO_FORMAT_AAC_HE_V1|AUDIO_FORMAT_AAC_HE_V2|AUDIO_FORMAT_PCM_16_BIT_OFFLOAD|AUDIO_FORMAT_MP2|AUDIO_FORMAT_AAC
  133. +
  134. formats AUDIO_FORMAT_MP3|AUDIO_FORMAT_AC3|AUDIO_FORMAT_E_AC3|AUDIO_FORMAT_PCM_24_BIT_OFFLOAD|AUDIO_FORMAT_FLAC|AUDIO_FORMAT_AAC_LC|AUDIO_FORMAT_AAC_HE_V1|AUDIO_FORMAT_AAC_HE_V2|AUDIO_FORMAT_MP2|AUDIO_FORMAT_AAC
  135. +
  136. + #endif/*VENDOR_EDIT*/
  137. +
  138. +#else
  139. + formats AUDIO_FORMAT_MP3|AUDIO_FORMAT_AC3|AUDIO_FORMAT_E_AC3|AUDIO_FORMAT_PCM_16_BIT_OFFLOAD|AUDIO_FORMAT_PCM_24_BIT_OFFLOAD|AUDIO_FORMAT_FLAC|AUDIO_FORMAT_AAC_LC|AUDIO_FORMAT_AAC_HE_V1|AUDIO_FORMAT_AAC_HE_V2|AUDIO_FORMAT_MP2
  140. #endif/*VENDOR_EDIT*/
  141. +
  142. devices AUDIO_DEVICE_OUT_SPEAKER|AUDIO_DEVICE_OUT_EARPIECE|AUDIO_DEVICE_OUT_WIRED_HEADSET|AUDIO_DEVICE_OUT_WIRED_HEADPHONE|AUDIO_DEVICE_OUT_ALL_SCO|AUDIO_DEVICE_OUT_AUX_DIGITAL|AUDIO_DEVICE_OUT_PROXY
  143. flags AUDIO_OUTPUT_FLAG_DIRECT|AUDIO_OUTPUT_FLAG_COMPRESS_OFFLOAD|AUDIO_OUTPUT_FLAG_NON_BLOCKING
  144. }
  145. diff --git a/camera/Android.mk b/camera/Android.mk
  146. index adbcc66..4206dab 100755
  147. --- a/camera/Android.mk
  148. +++ b/camera/Android.mk
  149. @@ -42,21 +42,4 @@ LOCAL_PRELINK_MODULE := false
  150.  
  151. include $(BUILD_SHARED_LIBRARY)
  152.  
  153. -include $(CLEAR_VARS)
  154. -
  155. -LOCAL_C_INCLUDES := \
  156. - system/media/camera/include
  157. -
  158. -LOCAL_SRC_FILES := \
  159. - CameraWrapper.cpp
  160. -
  161. -LOCAL_SHARED_LIBRARIES := \
  162. - libhardware liblog libgui libutils
  163. -
  164. -LOCAL_MODULE_RELATIVE_PATH := hw
  165. -LOCAL_MODULE := camera.$(TARGET_BOARD_PLATFORM)
  166. -LOCAL_MODULE_TAGS := optional
  167. -
  168. -include $(BUILD_SHARED_LIBRARY)
  169. -
  170. endif # !TARGET_SIMULATOR
  171. diff --git a/camera/CameraWrapper.cpp b/camera/CameraWrapper.cpp
  172. deleted file mode 100644
  173. index 17c4fdc..0000000
  174. --- a/camera/CameraWrapper.cpp
  175. +++ /dev/null
  176. @@ -1,158 +0,0 @@
  177. -/* Copyright (C) 2016, The CyanogenMod Project
  178. - *
  179. - * Licensed under the Apache License, Version 2.0 (the "License");
  180. - * you may not use this file except in compliance with the License.
  181. - * You may obtain a copy of the License at
  182. - *
  183. - * http://www.apache.org/licenses/LICENSE-2.0
  184. - *
  185. - * Unless required by applicable law or agreed to in writing, software
  186. - * distributed under the License is distributed on an "AS IS" BASIS,
  187. - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  188. - * See the License for the specific language governing permissions and
  189. - * limitations under the License.
  190. - */
  191. -
  192. -/**
  193. -* @file CameraWrapper.cpp
  194. -*
  195. -* This file wraps a vendor camera module.
  196. -*
  197. -*/
  198. -
  199. -//#define LOG_NDEBUG 0
  200. -
  201. -#define LOG_TAG "CameraWrapper"
  202. -#include <cutils/log.h>
  203. -
  204. -#include <dlfcn.h>
  205. -#include <hardware/hardware.h>
  206. -#include <hardware/camera.h>
  207. -#include <utils/threads.h>
  208. -#include <gui/SensorManager.h>
  209. -
  210. -static android::Mutex gCameraWrapperLock;
  211. -static camera_module_t *gVendorModule = 0;
  212. -
  213. -static int camera_device_open(const hw_module_t *module, const char *name,
  214. - hw_device_t **device);
  215. -static int camera_get_number_of_cameras(void);
  216. -static int camera_get_camera_info(int camera_id, struct camera_info *info);
  217. -
  218. -static struct hw_module_methods_t camera_module_methods = {
  219. - .open = camera_device_open
  220. -};
  221. -
  222. -camera_module_t HAL_MODULE_INFO_SYM = {
  223. - .common = {
  224. - .tag = HARDWARE_MODULE_TAG,
  225. - .module_api_version = CAMERA_MODULE_API_VERSION_1_0,
  226. - .hal_api_version = HARDWARE_HAL_API_VERSION,
  227. - .id = CAMERA_HARDWARE_MODULE_ID,
  228. - .name = "OnePlus 2 Camera Wrapper",
  229. - .author = "The CyanogenMod Project",
  230. - .methods = &camera_module_methods,
  231. - .dso = NULL, /* remove compilation warnings */
  232. - .reserved = {0}, /* remove compilation warnings */
  233. - },
  234. - .get_number_of_cameras = camera_get_number_of_cameras,
  235. - .get_camera_info = camera_get_camera_info,
  236. - .set_callbacks = NULL, /* remove compilation warnings */
  237. - .get_vendor_tag_ops = NULL, /* remove compilation warnings */
  238. - .open_legacy = NULL, /* remove compilation warnings */
  239. - .set_torch_mode = NULL, /* remove compilation warnings */
  240. - .init = NULL, /* remove compilation warnings */
  241. - .reserved = {0}, /* remove compilation warnings */
  242. -};
  243. -
  244. -static int load(const char *path,
  245. - const struct hw_module_t **pHmi)
  246. -{
  247. - int status = 0;
  248. - void *handle = NULL;
  249. - struct hw_module_t *hmi = NULL;
  250. -
  251. - handle = dlopen(path, RTLD_NOW);
  252. - if (handle == NULL) {
  253. - status = -EINVAL;
  254. - goto done;
  255. - }
  256. -
  257. - hmi = (struct hw_module_t *)dlsym(handle,
  258. - HAL_MODULE_INFO_SYM_AS_STR);
  259. - if (hmi == NULL) {
  260. - status = -EINVAL;
  261. - goto done;
  262. - }
  263. -
  264. - hmi->dso = handle;
  265. -
  266. - done:
  267. - *pHmi = hmi;
  268. -
  269. - return status;
  270. -}
  271. -
  272. -static int check_vendor_module()
  273. -{
  274. - int rv = 0;
  275. - ALOGV("%s", __FUNCTION__);
  276. -
  277. - if (gVendorModule)
  278. - return 0;
  279. -
  280. - rv = load("/system/lib/hw/camera.vendor.msm8994.so",
  281. - (const hw_module_t**)&gVendorModule);
  282. - if (rv)
  283. - ALOGE("failed to open vendor camera module");
  284. - return rv;
  285. -}
  286. -
  287. -static int camera_device_open(const hw_module_t *module __unused, const char *name,
  288. - hw_device_t **device)
  289. -{
  290. - int rv = 0;
  291. - int num_cameras = 0;
  292. - int cameraid;
  293. - int cameraretry;
  294. -
  295. - android::Mutex::Autolock lock(gCameraWrapperLock);
  296. -
  297. - ALOGV("%s", __FUNCTION__);
  298. -
  299. - if (name == NULL || check_vendor_module() != android::NO_ERROR) {
  300. - return -EINVAL;
  301. - }
  302. -
  303. - for (cameraretry = 0; cameraretry < 2; cameraretry++) {
  304. - rv = gVendorModule->common.methods->open(
  305. - (const hw_module_t*)gVendorModule, name,
  306. - device);
  307. - if (!rv)
  308. - break;
  309. -
  310. - ALOGV("%s: open failed - retrying attempt %d",__FUNCTION__, cameraretry);
  311. - }
  312. -
  313. - if (rv)
  314. - ALOGE("vendor camera open fail");
  315. -
  316. - return rv;
  317. -}
  318. -
  319. -static int camera_get_number_of_cameras(void)
  320. -{
  321. - ALOGV("%s", __FUNCTION__);
  322. - if (check_vendor_module())
  323. - return 0;
  324. - return gVendorModule->get_number_of_cameras();
  325. -}
  326. -
  327. -static int camera_get_camera_info(int camera_id, struct camera_info *info)
  328. -{
  329. - ALOGV("%s", __FUNCTION__);
  330. - if (check_vendor_module())
  331. - return 0;
  332. -
  333. - return gVendorModule->get_camera_info(camera_id, info);
  334. -}
  335. diff --git a/cm.dependencies b/cm.dependencies
  336. index e5d96c5..feb45ca 100644
  337. --- a/cm.dependencies
  338. +++ b/cm.dependencies
  339. @@ -1,10 +1,26 @@
  340. [
  341. + {
  342. + "remote": "github",
  343. + "repository": "CyanogenMod/android_device_qcom_common",
  344. + "target_path": "device/qcom/common",
  345. + "revision": "cm-14.0"
  346. + },
  347. + {
  348. + "remote": "github",
  349. + "repository": "Seraph08/android_kernel_oneplus_msm8994",
  350. + "target_path": "kernel/oneplus/msm8994",
  351. + "revision": "cm-14.0"
  352. + },
  353. {
  354. - "repository": "android_device_oppo_common",
  355. - "target_path": "device/oppo/common"
  356. + "remote": "github",
  357. + "repository": "Seraph08/android_device_oppo_common",
  358. + "target_path": "device/oppo/common",
  359. + "revision": "cm-14.0"
  360. },
  361. {
  362. - "repository": "android_kernel_oneplus_msm8994",
  363. - "target_path": "kernel/oneplus/msm8994"
  364. + "remote": "github",
  365. + "repository": "Seraph08/proprietary_vendor_oneplus",
  366. + "target_path": "vendor/oneplus",
  367. + "revision": "cm-14.0"
  368. }
  369. ]
  370. diff --git a/cm.mk b/cm.mk
  371. index c1d494c..b7a7866 100644
  372. --- a/cm.mk
  373. +++ b/cm.mk
  374. @@ -28,15 +28,3 @@ PRODUCT_MANUFACTURER := OnePlus
  375. PRODUCT_BRAND := OnePlus
  376.  
  377. PRODUCT_GMS_CLIENTID_BASE := android-oneplus
  378. -
  379. -TARGET_VENDOR_PRODUCT_NAME := OnePlus2
  380. -TARGET_VENDOR_DEVICE_NAME := OnePlus2
  381. -PRODUCT_BUILD_PROP_OVERRIDES += TARGET_DEVICE=OnePlus2 PRODUCT_NAME=OnePlus2
  382. -
  383. -PRODUCT_BUILD_PROP_OVERRIDES += \
  384. - BUILD_FINGERPRINT=OnePlus/OnePlus2/OnePlus2:6.0.1/MMB29M/1447840920:user/release-keys \
  385. - PRIVATE_BUILD_DESC="OnePlus2-user 6.0.1 MMB29M 20 dev-keys"
  386. -
  387. -PRODUCT_SYSTEM_PROPERTY_BLACKLIST += ro.product.model
  388. -
  389. -TARGET_VENDOR := oneplus
  390. diff --git a/configs/media_codecs.xml b/configs/media_codecs.xml
  391. index 3260c4a..1614f71 100644
  392. --- a/configs/media_codecs.xml
  393. +++ b/configs/media_codecs.xml
  394. @@ -326,7 +326,8 @@ Only the three quirks included above are recognized at this point:
  395. <Feature name="secure-playback" required="true" />
  396. <Limit name="concurrent-instances" max="6" />
  397. </MediaCodec>
  398. + <!-- Audio Software -->
  399. + <MediaCodec name="OMX.qti.audio.decoder.flac" type="audio/flac" />
  400. </Decoders>
  401. <Include href="media_codecs_google_video.xml" />
  402. - <Include href="media_codecs_ffmpeg.xml" />
  403. </MediaCodecs>
  404. diff --git a/configs/media_profiles.xml b/configs/media_profiles.xml
  405. index 8f71789..0183023 100644
  406. --- a/configs/media_profiles.xml
  407. +++ b/configs/media_profiles.xml
  408. @@ -373,61 +373,6 @@
  409. channels="2" />
  410. </EncoderProfile>
  411.  
  412. - <!-- CAMCORDER_QUALITY_HIGH_SPEED_LOW/720P : 720p@120fps; 27.0 Mbps -->
  413. - <EncoderProfile quality="highspeedlow" fileFormat="mp4" duration="30">
  414. - <Video codec="h264"
  415. - bitRate="27000000"
  416. - width="1280"
  417. - height="720"
  418. - frameRate="120" />
  419. - <!-- audio setting is ignored -->
  420. - <Audio codec="aac"
  421. - bitRate="96000"
  422. - sampleRate="48000"
  423. - channels="2" />
  424. - </EncoderProfile>
  425. -
  426. - <!-- CAMCORDER_QUALITY_HIGH_SPEED_HIGH/720P : 720p@120fps; 27.0 Mbps -->
  427. - <EncoderProfile quality="highspeedhigh" fileFormat="mp4" duration="30">
  428. - <Video codec="h264"
  429. - bitRate="27000000"
  430. - width="1280"
  431. - height="720"
  432. - frameRate="120" />
  433. - <!-- audio setting is ignored -->
  434. - <Audio codec="aac"
  435. - bitRate="96000"
  436. - sampleRate="48000"
  437. - channels="2" />
  438. - </EncoderProfile>
  439. -
  440. - <EncoderProfile quality="highspeed720p" fileFormat="mp4" duration="30">
  441. - <Video codec="h264"
  442. - bitRate="27000000"
  443. - width="1280"
  444. - height="720"
  445. - frameRate="120" />
  446. - <!-- audio setting is ignored -->
  447. - <Audio codec="aac"
  448. - bitRate="96000"
  449. - sampleRate="48000"
  450. - channels="2" />
  451. - </EncoderProfile>
  452. -
  453. - <!-- CAMCORDER_QUALITY_HIGH_SPEED_HIGH/1080P : 1080p@60fps; 34.0 Mbps -->
  454. - <EncoderProfile quality="highspeed1080p" fileFormat="mp4" duration="30">
  455. - <Video codec="h264"
  456. - bitRate="34000000"
  457. - width="1920"
  458. - height="1080"
  459. - frameRate="60" />
  460. - <!-- audio setting is ignored -->
  461. - <Audio codec="aac"
  462. - bitRate="96000"
  463. - sampleRate="48000"
  464. - channels="2" />
  465. - </EncoderProfile>
  466. -
  467. <ImageEncoding quality="95" />
  468. <ImageEncoding quality="80" />
  469. <ImageEncoding quality="70" />
  470. diff --git a/data-ipa-cfg-mgr/Android.mk b/data-ipa-cfg-mgr/Android.mk
  471. deleted file mode 100644
  472. index 39de891..0000000
  473. --- a/data-ipa-cfg-mgr/Android.mk
  474. +++ /dev/null
  475. @@ -1,18 +0,0 @@
  476. -#
  477. -# Copyright (C) 2015 The CyanogenMod Project
  478. -#
  479. -# Licensed under the Apache License, Version 2.0 (the "License");
  480. -# you may not use this file except in compliance with the License.
  481. -# You may obtain a copy of the License at
  482. -#
  483. -# http://www.apache.org/licenses/LICENSE-2.0
  484. -#
  485. -# Unless required by applicable law or agreed to in writing, software
  486. -# distributed under the License is distributed on an "AS IS" BASIS,
  487. -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  488. -# See the License for the specific language governing permissions and
  489. -# limitations under the License.
  490. -
  491. -LOCAL_PATH := $(call my-dir)
  492. -
  493. -include $(call first-makefiles-under,$(LOCAL_PATH))
  494. diff --git a/data-ipa-cfg-mgr/ipacm/src/Android.mk b/data-ipa-cfg-mgr/ipacm/src/Android.mk
  495. index 6720a17..dbecf66 100644
  496. --- a/data-ipa-cfg-mgr/ipacm/src/Android.mk
  497. +++ b/data-ipa-cfg-mgr/ipacm/src/Android.mk
  498. @@ -1,3 +1,5 @@
  499. +ifneq (,$(filter $(QCOM_BOARD_PLATFORMS),$(TARGET_BOARD_PLATFORM)))
  500. +ifneq (, $(filter aarch64 arm arm64, $(TARGET_ARCH)))
  501. LOCAL_PATH := $(call my-dir)
  502.  
  503. include $(CLEAR_VARS)
  504. @@ -10,6 +12,7 @@ LOCAL_C_INCLUDES += external/icu/icu4c/source/common
  505. else
  506. LOCAL_C_INCLUDES += external/icu4c/common
  507. endif
  508. +LOCAL_C_INCLUDES += external/dhcpcd
  509. LOCAL_C_INCLUDES += external/libxml2/include
  510. LOCAL_C_INCLUDES += external/libnetfilter_conntrack/include
  511. LOCAL_C_INCLUDES += external/libnfnetlink/include
  512. @@ -54,7 +57,8 @@ LOCAL_SHARED_LIBRARIES := libipanat
  513. LOCAL_SHARED_LIBRARIES += libxml2
  514. LOCAL_SHARED_LIBRARIES += libnfnetlink
  515. LOCAL_SHARED_LIBRARIES += libnetfilter_conntrack
  516. -include $(BUILD_EXECUTABLE)
  517. +LOCAL_SHARED_LIBRARIES += libdhcpcd
  518. +#include $(BUILD_EXECUTABLE)
  519.  
  520. ################################################################################
  521.  
  522. @@ -77,4 +81,7 @@ LOCAL_MODULE_PATH := $(TARGET_OUT_ETC)
  523. LOCAL_MODULE_TAGS := optional
  524. LOCAL_SRC_FILES := $(LOCAL_MODULE)
  525. LOCAL_MODULE_OWNER := ipacm
  526. -include $(BUILD_PREBUILT)
  527. +#include $(BUILD_PREBUILT)
  528. +
  529. +endif # $(TARGET_ARCH)
  530. +endif
  531. diff --git a/data-ipa-cfg-mgr/ipacm/src/IPACM_Lan.cpp b/data-ipa-cfg-mgr/ipacm/src/IPACM_Lan.cpp
  532. index 4b36c42..67ba5f5 100644
  533. --- a/data-ipa-cfg-mgr/ipacm/src/IPACM_Lan.cpp
  534. +++ b/data-ipa-cfg-mgr/ipacm/src/IPACM_Lan.cpp
  535. @@ -5436,11 +5436,11 @@ eth_bridge_client_rt_info* IPACM_Lan::eth_bridge_get_client_rt_info_ptr(uint8_t
  536. void* result;
  537. if(iptype == IPA_IP_v4)
  538. {
  539. - result = (void*)((char*)eth_bridge_usb_client_rt_info_v4 + index * client_rt_info_size_v4);
  540. + result = (void*)((void*)eth_bridge_usb_client_rt_info_v4 + index * client_rt_info_size_v4);
  541. }
  542. else
  543. {
  544. - result = (void*)((char*)eth_bridge_usb_client_rt_info_v6 + index * client_rt_info_size_v6);
  545. + result = (void*)((void*)eth_bridge_usb_client_rt_info_v6 + index * client_rt_info_size_v6);
  546. }
  547. return (eth_bridge_client_rt_info*)result;
  548. }
  549. diff --git a/data-ipa-cfg-mgr/ipacm/src/IPACM_Wan.cpp b/data-ipa-cfg-mgr/ipacm/src/IPACM_Wan.cpp
  550. index f7e6c38..b21a763 100644
  551. --- a/data-ipa-cfg-mgr/ipacm/src/IPACM_Wan.cpp
  552. +++ b/data-ipa-cfg-mgr/ipacm/src/IPACM_Wan.cpp
  553. @@ -1024,7 +1024,7 @@ int IPACM_Wan::handle_route_add_evt(ipa_ip_type iptype)
  554. break;
  555. }
  556.  
  557. - //if(tx_prop->tx[cnt].hdr_name != NULL)
  558. + if(tx_prop->tx[cnt].hdr_name != NULL)
  559. {
  560. memset(&sCopyHeader, 0, sizeof(sCopyHeader));
  561. memcpy(sCopyHeader.name,
  562. @@ -1104,7 +1104,7 @@ int IPACM_Wan::handle_route_add_evt(ipa_ip_type iptype)
  563. strcpy(rt_rule->rt_tbl_name, IPACM_Iface::ipacmcfg->rt_tbl_v6.name);
  564. }
  565.  
  566. - //if (tx_prop->tx[tx_index].hdr_name != NULL)
  567. + if (tx_prop->tx[tx_index].hdr_name != NULL)
  568. {
  569. IPACMDBG_H(" TX- header hdl %s \n", tx_prop->tx[tx_index].hdr_name);
  570. memset(&sRetHeader, 0, sizeof(sRetHeader));
  571. @@ -1686,7 +1686,7 @@ int IPACM_Wan::config_dft_firewall_rules(ipa_ip_type iptype)
  572. memset(&firewall_config, 0, sizeof(firewall_config));
  573. strncpy(firewall_config.firewall_config_file, "/etc/mobileap_firewall.xml", sizeof(firewall_config.firewall_config_file));
  574.  
  575. - //if (firewall_config.firewall_config_file)
  576. + if (firewall_config.firewall_config_file)
  577. {
  578. IPACMDBG_H("Firewall XML file is %s \n", firewall_config.firewall_config_file);
  579. if (IPACM_SUCCESS == IPACM_read_firewall_xml(firewall_config.firewall_config_file, &firewall_config))
  580. @@ -1711,11 +1711,11 @@ int IPACM_Wan::config_dft_firewall_rules(ipa_ip_type iptype)
  581. IPACMERR("QCMAP Firewall XML read failed, no that file, use default configuration \n");
  582. }
  583. }
  584. - /*else
  585. + else
  586. {
  587. IPACMERR("No firewall xml mentioned \n");
  588. return IPACM_FAILURE;
  589. - }*/
  590. + }
  591.  
  592. /* construct ipa_ioc_add_flt_rule with N firewall rules */
  593. ipa_ioc_add_flt_rule *m_pFilteringTable = NULL;
  594. @@ -2348,7 +2348,7 @@ int IPACM_Wan::config_dft_firewall_rules_ex(struct ipa_flt_rule_add *rules, int
  595. memset(&firewall_config, 0, sizeof(firewall_config));
  596. strncpy(firewall_config.firewall_config_file, "/etc/mobileap_firewall.xml", sizeof(firewall_config.firewall_config_file));
  597.  
  598. - //if (firewall_config.firewall_config_file)
  599. + if (firewall_config.firewall_config_file)
  600. {
  601. IPACMDBG_H("Firewall XML file is %s \n", firewall_config.firewall_config_file);
  602. if (IPACM_SUCCESS == IPACM_read_firewall_xml(firewall_config.firewall_config_file, &firewall_config))
  603. @@ -2360,11 +2360,11 @@ int IPACM_Wan::config_dft_firewall_rules_ex(struct ipa_flt_rule_add *rules, int
  604. IPACMERR("QCMAP Firewall XML read failed, no that file, use default configuration \n");
  605. }
  606. }
  607. - /*else
  608. - //{
  609. + else
  610. + {
  611. IPACMERR("No firewall xml mentioned \n");
  612. return IPACM_FAILURE;
  613. - }*/
  614. + }
  615.  
  616. /* add IPv6 frag rule when firewall is enabled*/
  617. if(iptype == IPA_IP_v6 && firewall_config.firewall_enable == true)
  618. diff --git a/data-ipa-cfg-mgr/ipacm/src/IPACM_Wlan.cpp b/data-ipa-cfg-mgr/ipacm/src/IPACM_Wlan.cpp
  619. index 3f2d1a2..cbcc797 100644
  620. --- a/data-ipa-cfg-mgr/ipacm/src/IPACM_Wlan.cpp
  621. +++ b/data-ipa-cfg-mgr/ipacm/src/IPACM_Wlan.cpp
  622. @@ -4697,22 +4697,22 @@ eth_bridge_client_rt_info* IPACM_Wlan::eth_bridge_get_client_rt_info_ptr(uint8_t
  623. {
  624. if(iptype == IPA_IP_v4)
  625. {
  626. - result = (void*)((char*)eth_bridge_wlan_client_rt_from_wlan_info_v4 + index * client_rt_info_size_v4);
  627. + result = (void*)((void*)eth_bridge_wlan_client_rt_from_wlan_info_v4 + index * client_rt_info_size_v4);
  628. }
  629. else
  630. {
  631. - result = (void*)((char*)eth_bridge_wlan_client_rt_from_wlan_info_v6 + index * client_rt_info_size_v6);
  632. + result = (void*)((void*)eth_bridge_wlan_client_rt_from_wlan_info_v6 + index * client_rt_info_size_v6);
  633. }
  634. }
  635. else
  636. {
  637. if(iptype == IPA_IP_v4)
  638. {
  639. - result = (void*)((char*)eth_bridge_wlan_client_rt_from_usb_info_v4 + index * client_rt_info_size_v4);
  640. + result = (void*)((void*)eth_bridge_wlan_client_rt_from_usb_info_v4 + index * client_rt_info_size_v4);
  641. }
  642. else
  643. {
  644. - result = (void*)((char*)eth_bridge_wlan_client_rt_from_usb_info_v6 + index * client_rt_info_size_v6);
  645. + result = (void*)((void*)eth_bridge_wlan_client_rt_from_usb_info_v6 + index * client_rt_info_size_v6);
  646. }
  647. }
  648. return (eth_bridge_client_rt_info*)result;
  649. diff --git a/data-ipa-cfg-mgr/ipanat/src/Android.mk b/data-ipa-cfg-mgr/ipanat/src/Android.mk
  650. index ecc64c4..a97b6ce 100644
  651. --- a/data-ipa-cfg-mgr/ipanat/src/Android.mk
  652. +++ b/data-ipa-cfg-mgr/ipanat/src/Android.mk
  653. @@ -1,3 +1,6 @@
  654. +ifneq (,$(filter $(QCOM_BOARD_PLATFORMS),$(TARGET_BOARD_PLATFORM)))
  655. +ifneq (, $(filter aarch64 arm arm64, $(TARGET_ARCH)))
  656. +
  657. LOCAL_PATH := $(call my-dir)
  658.  
  659. include $(CLEAR_VARS)
  660. @@ -16,3 +19,6 @@ LOCAL_MODULE_TAGS := optional
  661. LOCAL_PRELINK_MODULE := false
  662.  
  663. include $(BUILD_SHARED_LIBRARY)
  664. +
  665. +endif # $(TARGET_ARCH)
  666. +endif
  667. diff --git a/device.mk b/device.mk
  668. index b70414f..3c3606e 100644
  669. --- a/device.mk
  670. +++ b/device.mk
  671. @@ -101,7 +101,6 @@ PRODUCT_PACKAGES += \
  672.  
  673. # Camera
  674. PRODUCT_PACKAGES += \
  675. - camera.msm8994 \
  676. sensors.hal.tof \
  677. Snap
  678.  
  679. @@ -238,6 +237,7 @@ PRODUCT_PACKAGES += \
  680. librmnetctl \
  681. libxml2
  682.  
  683. +# Telephony-ext
  684. PRODUCT_PACKAGES += telephony-ext
  685. PRODUCT_BOOT_JARS += telephony-ext
  686.  
  687. diff --git a/overlay/frameworks/base/core/res/res/values/config.xml b/overlay/frameworks/base/core/res/res/values/config.xml
  688. index b2d2395..3516b55 100644
  689. --- a/overlay/frameworks/base/core/res/res/values/config.xml
  690. +++ b/overlay/frameworks/base/core/res/res/values/config.xml
  691. @@ -126,6 +126,7 @@
  692. 64 - Volume rocker
  693. For example, a device with Home, Back and Menu keys would set this
  694. config to 7. -->
  695. + <add-resource type="integer" name="config_deviceHardwareKeys"></add-resource>
  696. <integer name="config_deviceHardwareKeys">83</integer>
  697.  
  698. <!-- Hardware keys present on the device with the ability to wake, stored as a bit field.
  699. @@ -139,8 +140,8 @@
  700. 32 - Camera
  701. 64 - Volume rocker
  702. For example, a device with Home, Back and Menu keys would set this
  703. - config to 7. -->
  704. - <integer name="config_deviceHardwareWakeKeys">64</integer>
  705. + config to 7.
  706. + <integer name="config_deviceHardwareWakeKeys">64</integer> -->
  707.  
  708. <!-- Control the behavior when the user long presses the home button
  709. 0 - Nothing
  710. @@ -152,6 +153,7 @@
  711. This needs to match the constants in
  712. policy/src/com/android/internal/policy/impl/PhoneWindowManager.java
  713. -->
  714. + <add-resource type="integer" name="config_longPressOnHomeBehavior"></add-resource>
  715. <integer name="config_longPressOnHomeBehavior">3</integer>
  716.  
  717. <!-- Control the behavior when the user long presses the app switch button.
  718. @@ -164,6 +166,7 @@
  719. This needs to match the constants in
  720. policy/src/com/android/internal/policy/impl/PhoneWindowManager.java
  721. -->
  722. + <add-resource type="integer" name="config_longPressOnAppSwitchBehavior"></add-resource>
  723. <integer name="config_longPressOnAppSwitchBehavior">1</integer>
  724.  
  725. <!-- Boolean indicating whether the wifi chipset has dual frequency band support -->
  726. diff --git a/overlay/frameworks/opt/telephony/resources/res/values/config.xml b/overlay/frameworks/opt/telephony/resources/res/values/config.xml
  727. deleted file mode 100644
  728. index 5f2d264..0000000
  729. --- a/overlay/frameworks/opt/telephony/resources/res/values/config.xml
  730. +++ /dev/null
  731. @@ -1,36 +0,0 @@
  732. -<?xml version="1.0" encoding="utf-8"?>
  733. -<!-- Copyright (c) 2015, The Linux Foundation. All rights reserved.
  734. -
  735. - Redistribution and use in source and binary forms, with or without
  736. - modification, are permitted provided that the following conditions are
  737. - met:
  738. - * Redistributions of source code must retain the above copyright
  739. - notice, this list of conditions and the following disclaimer.
  740. - * Redistributions in binary form must reproduce the above
  741. - copyright notice, this list of conditions and the following
  742. - disclaimer in the documentation and/or other materials provided
  743. - with the distribution.
  744. - * Neither the name of The Linux Foundation nor the names of its
  745. - contributors may be used to endorse or promote products derived
  746. - from this software without specific prior written permission.
  747. -
  748. - THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  749. - WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  750. - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
  751. - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  752. - BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  753. - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  754. - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  755. - BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  756. - WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  757. - OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  758. - IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  759. --->
  760. -
  761. -<resources>
  762. - <!--The .jar file name which has the extended implementation
  763. - of telephony base classes.-->
  764. - <string name="telephony_plugin_jar_name" translatable="false">qti-telephony-common.jar</string>
  765. - <!--Fully qualified class name of telephony extended plugin.-->
  766. - <string name="telephony_plugin_class_name" translatable="false">com.qti.internal.telephony.QtiTelephonyPlugin</string>
  767. -</resources>
  768. diff --git a/proprietary-files.txt b/proprietary-files.txt
  769. index 19965da..d259621 100644
  770. --- a/proprietary-files.txt
  771. +++ b/proprietary-files.txt
  772. @@ -51,7 +51,7 @@ vendor/lib64/libbtnv.so
  773. # Camera
  774. bin/mm-qcamera-app
  775. bin/mm-qcamera-daemon
  776. -lib/hw/camera.msm8994.so:lib/hw/camera.vendor.msm8994.so
  777. +lib/hw/camera.msm8994.so
  778. lib/libFNVfbEngineLib.so
  779. lib/libmm-qcamera.so
  780. lib/libmmcamera_interface.so
  781. diff --git a/rootdir/etc/init.qcom.rc b/rootdir/etc/init.qcom.rc
  782. index feece7e..b8b3632 100755
  783. --- a/rootdir/etc/init.qcom.rc
  784. +++ b/rootdir/etc/init.qcom.rc
  785. @@ -126,10 +126,6 @@ on init
  786. chown root system /proc/tri-state-key/keyCode_bottom
  787. chmod 0660 /proc/tri-state-key/keyCode_bottom
  788.  
  789. - # PCC Calibration
  790. - chown system system /sys/devices/virtual/graphics/fb0/rgb
  791. - chmod 0660 /sys/devices/virtual/graphics/fb0/rgb
  792. -
  793. # for product mode flashlight
  794. chown system system /proc/qcom_flash
  795.  
  796. @@ -169,6 +165,18 @@ on init
  797. chown root system /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  798. chmod 0660 /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  799.  
  800. + # GPU Tuning
  801. + chown root system /sys/class/kgsl/kgsl-3d0/dispatch/inflight
  802. + chmod 0660 /sys/class/kgsl/kgsl-3d0/dispatch/inflight
  803. + chown root system /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  804. + chmod 0660 /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  805. +
  806. + # GPU Tuning
  807. + chown root system /sys/class/kgsl/kgsl-3d0/dispatch/inflight
  808. + chmod 0660 /sys/class/kgsl/kgsl-3d0/dispatch/inflight
  809. + chown root system /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  810. + chmod 0660 /sys/class/kgsl/kgsl-3d0/dispatch/inflight_low_latency
  811. +
  812. # Enable cgroup_freezer
  813. mkdir /sys/fs/cgroup/freezer 0750 root system
  814. mount cgroup none /sys/fs/cgroup/freezer freezer
  815. @@ -203,6 +211,12 @@ on boot
  816. start rmt_storage
  817. start rfs_access
  818.  
  819. + # update foreground cpuset now that processors are up
  820. + write /dev/cpuset/foreground/cpus 0-7
  821. + write /dev/cpuset/foreground/boost/cpus 4-7
  822. + write /dev/cpuset/background/cpus 0-2
  823. + write /dev/cpuset/system-background/cpus 0-3
  824. +
  825. chown bluetooth bluetooth /sys/module/bluetooth_power/parameters/power
  826. chown bluetooth net_bt /sys/class/rfkill/rfkill0/type
  827. chown bluetooth net_bt /sys/class/rfkill/rfkill0/state
  828. @@ -289,50 +303,15 @@ on boot
  829. # create symlink for fb1 as HDMI
  830. symlink /dev/graphics/fb1 /dev/graphics/hdmi
  831.  
  832. - # MDP idle notifier
  833. - chown system graphics /sys/class/graphics/fb0/idle_time
  834. - chmod 0664 /sys/class/graphics/fb0/idle_time
  835. -
  836. - # setup permissions for fb1 related nodes
  837. + # Graphics
  838. chown system graphics /sys/class/graphics/fb0/idle_time
  839. - chown system graphics /sys/class/graphics/fb0/dynamic_fps
  840. - chown system graphics /sys/class/graphics/fb0/dyn_pu
  841. - chown system graphics /sys/class/graphics/fb0/modes
  842. - chown system graphics /sys/class/graphics/fb0/mode
  843. -
  844. chmod 0664 /sys/devices/virtual/graphics/fb0/idle_time
  845. - chmod 0664 /sys/devices/virtual/graphics/fb0/dynamic_fps
  846. + chown system graphics /sys/class/graphics/fb0/dyn_pu
  847. chmod 0664 /sys/devices/virtual/graphics/fb0/dyn_pu
  848. - chmod 0664 /sys/devices/virtual/graphics/fb0/modes
  849. + chown system graphics /sys/class/graphics/fb0/mode
  850. chmod 0664 /sys/devices/virtual/graphics/fb0/mode
  851. -
  852. - chown system graphics /sys/class/graphics/fb1/hpd
  853. - chown system graphics /sys/class/graphics/fb1/res_info
  854. - chown system graphics /sys/class/graphics/fb1/vendor_name
  855. - chown system graphics /sys/class/graphics/fb1/product_description
  856. - chown system graphics /sys/class/graphics/fb1/video_mode
  857. - chown system graphics /sys/class/graphics/fb1/format_3d
  858. - chown system graphics /sys/class/graphics/fb1/s3d_mode
  859. - chown system graphics /sys/class/graphics/fb1/cec/enable
  860. - chown system graphics /sys/class/graphics/fb1/cec/logical_addr
  861. - chown system graphics /sys/class/graphics/fb1/cec/rd_msg
  862. - chown system graphics /sys/class/graphics/fb1/pa
  863. - chown system graphics /sys/class/graphics/fb1/cec/wr_msg
  864. - chown system graphics /sys/class/graphics/fb1/hdcp/tp
  865. -
  866. - chmod 0664 /sys/devices/virtual/graphics/fb1/hpd
  867. - chmod 0664 /sys/devices/virtual/graphics/fb1/res_info
  868. - chmod 0664 /sys/devices/virtual/graphics/fb1/vendor_name
  869. - chmod 0664 /sys/devices/virtual/graphics/fb1/product_description
  870. - chmod 0664 /sys/devices/virtual/graphics/fb1/video_mode
  871. - chmod 0664 /sys/devices/virtual/graphics/fb1/format_3d
  872. - chmod 0664 /sys/devices/virtual/graphics/fb1/s3d_mode
  873. - chmod 0664 /sys/devices/virtual/graphics/fb1/cec/enable
  874. - chmod 0664 /sys/devices/virtual/graphics/fb1/cec/logical_addr
  875. - chmod 0664 /sys/devices/virtual/graphics/fb1/cec/rd_msg
  876. - chmod 0664 /sys/devices/virtual/graphics/fb1/pa
  877. - chmod 0664 /sys/devices/virtual/graphics/fb1/cec/wr_msg
  878. - chmod 0664 /sys/devices/virtual/graphics/fb1/hdcp/tp
  879. + chown system graphics /sys/class/graphics/fb0/modes
  880. + chmod 0664 /sys/devices/virtual/graphics/fb0/modes
  881.  
  882. # Allow access for CCID command/response timeout configuration
  883. chown system system /sys/module/ccid_bridge/parameters/bulk_msg_timeout
  884. diff --git a/system.prop b/system.prop
  885. index a80061d..c0003fd 100644
  886. --- a/system.prop
  887. +++ b/system.prop
  888. @@ -8,7 +8,7 @@ ro.qc.sdk.audio.fluencetype=fluence
  889. ro.qc.sdk.audio.ssr=false
  890. persist.audio.ssr.3mic=false
  891. media.aac_51_output_enabled=true
  892. -audio.offload.pcm.16bit.enable=false
  893. +audio.offload.pcm.16bit.enable=true
  894. audio.offload.pcm.24bit.enable=true
  895. use.voice.path.for.pcm.voip=true
  896. audio.offload.multiple.enabled=true
  897. @@ -24,7 +24,6 @@ ro.bluetooth.wipower=true
  898.  
  899. # Camera
  900. camera.disable_zsl_mode=1
  901. -persist.camera.HAL3.enabled=0
  902. persist.camera.cpp.duplication=false
  903.  
  904. # CEC
  905. @@ -99,6 +98,9 @@ ro.qc.sdk.sensors.gestures=true
  906. ro.qc.sdk.gestures.camera=false
  907. ro.qc.sdk.camera.facialproc=false
  908.  
  909. +# Storage
  910. +ro.sys.sdcardfs=true
  911. +
  912. # Time services
  913. persist.timed.enable=true
  914.  
  915. diff --git a/vendorsetup.sh b/vendorsetup.sh
  916. index a231aa7..1e551d6 100755
  917. --- a/vendorsetup.sh
  918. +++ b/vendorsetup.sh
  919. @@ -1,3 +1,2 @@
  920. -add_lunch_combo cm_oneplus2-user
  921. add_lunch_combo cm_oneplus2-userdebug
  922. -add_lunch_combo cm_oneplus2-eng
  923.  
  924.  
  925.  
  926. KERNEL:
  927.  
  928. david@RosettaStoned:~/Android/cyanogenmod/kernel/oneplus/msm8994$ git diff grarak/cm-14.0 seraph/cm-14.0
  929. diff --git a/arch/arm64/boot/dts/14049_HW/msm8994.dtsi b/arch/arm64/boot/dts/14049_HW/msm8994.dtsi
  930. new file mode 100644
  931. index 0000000..3542c21
  932. --- /dev/null
  933. +++ b/arch/arm64/boot/dts/14049_HW/msm8994.dtsi
  934. @@ -0,0 +1,3920 @@
  935. +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  936. + *
  937. + * This program is free software; you can redistribute it and/or modify
  938. + * it under the terms of the GNU General Public License version 2 and
  939. + * only version 2 as published by the Free Software Foundation.
  940. + *
  941. + * This program is distributed in the hope that it will be useful,
  942. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  943. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  944. + * GNU General Public License for more details.
  945. + */
  946. +
  947. +/memreserve/ 0x00000000 0x00001000;
  948. +/memreserve/ 0xac1c0000 0x00001000;
  949. +
  950. +#include "skeleton64.dtsi"
  951. +#include <dt-bindings/clock/msm-clocks-8994.h>
  952. +
  953. +/ {
  954. + model = "Qualcomm Technologies, Inc. MSM 8994";
  955. + compatible = "qcom,msm8994";
  956. + qcom,msm-id = <207 0x0>;
  957. + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  958. + interrupt-parent = <&intc>;
  959. +
  960. + chosen {
  961. + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 sched_same_power_cost_cpus=0-3";
  962. + };
  963. +
  964. + aliases {
  965. + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  966. + /*do not enable sdhc2 and sdhc3
  967. + sdhc2 = &sdhc_2;
  968. + sdhc3 = &sdhc_3;
  969. + */
  970. + i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
  971. + i2c1 = &i2c_1;
  972. + i2c2 = &i2c_2;
  973. + i2c5 = &i2c_5;
  974. + spi0 = &spi_0;
  975. + /*#ifdef VENDOR_EDIT modify for fpc1021 fingerprints*/
  976. + spi12 = &spi_12;
  977. + /*#end VENDOR_EDIT*/
  978. + qup2 = &i2c_2;
  979. + };
  980. +
  981. + cpus {
  982. + #address-cells = <1>;
  983. + #size-cells = <0>;
  984. + cpu-map {
  985. + cluster0 {
  986. + core0 {
  987. + cpu = <&CPU0>;
  988. + };
  989. + core1 {
  990. + cpu = <&CPU1>;
  991. + };
  992. + core2 {
  993. + cpu = <&CPU2>;
  994. + };
  995. + core3 {
  996. + cpu = <&CPU3>;
  997. + };
  998. :
  999. +#include <dt-bindings/clock/msm-clocks-8994.h>
  1000. +
  1001. +/ {
  1002. + model = "Qualcomm Technologies, Inc. MSM 8994";
  1003. + compatible = "qcom,msm8994";
  1004. + qcom,msm-id = <207 0x0>;
  1005. + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  1006. + interrupt-parent = <&intc>;
  1007. +
  1008. + chosen {
  1009. + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 sched_same_power_cost_cpus=0-3";
  1010. + };
  1011. +
  1012. + aliases {
  1013. + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  1014. + /*do not enable sdhc2 and sdhc3
  1015. + sdhc2 = &sdhc_2;
  1016. + sdhc3 = &sdhc_3;
  1017. + */
  1018. + i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
  1019. + i2c1 = &i2c_1;
  1020. + i2c2 = &i2c_2;
  1021. + i2c5 = &i2c_5;
  1022. + spi0 = &spi_0;
  1023. + /*#ifdef VENDOR_EDIT modify for fpc1021 fingerprints*/
  1024. + spi12 = &spi_12;
  1025. + /*#end VENDOR_EDIT*/
  1026. + qup2 = &i2c_2;
  1027. :
  1028. +#include <dt-bindings/clock/msm-clocks-8994.h>
  1029. +
  1030. +/ {
  1031. + model = "Qualcomm Technologies, Inc. MSM 8994";
  1032. + compatible = "qcom,msm8994";
  1033. + qcom,msm-id = <207 0x0>;
  1034. + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  1035. + interrupt-parent = <&intc>;
  1036. +
  1037. + chosen {
  1038. + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 sched_same_power_cost_cpus=0-3";
  1039. + };
  1040. +
  1041. + aliases {
  1042. + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  1043. + /*do not enable sdhc2 and sdhc3
  1044. + sdhc2 = &sdhc_2;
  1045. + sdhc3 = &sdhc_3;
  1046. + */
  1047. + i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
  1048. + i2c1 = &i2c_1;
  1049. + i2c2 = &i2c_2;
  1050. + i2c5 = &i2c_5;
  1051. + spi0 = &spi_0;
  1052. + /*#ifdef VENDOR_EDIT modify for fpc1021 fingerprints*/
  1053. + spi12 = &spi_12;
  1054. + /*#end VENDOR_EDIT*/
  1055. + qup2 = &i2c_2;
  1056. + };
  1057. +
  1058. + cpus {
  1059. + #address-cells = <1>;
  1060. + #size-cells = <0>;
  1061. + cpu-map {
  1062. + cluster0 {
  1063. + core0 {
  1064. + cpu = <&CPU0>;
  1065. + };
  1066. + core1 {
  1067. + cpu = <&CPU1>;
  1068. + };
  1069. + core2 {
  1070. + cpu = <&CPU2>;
  1071. + };
  1072. + core3 {
  1073. + cpu = <&CPU3>;
  1074. + };
  1075. + };
  1076. +
  1077. + cluster1 {
  1078. + core0 {
  1079. + cpu = <&CPU4>;
  1080. + };
  1081. + core1 {
  1082. + cpu = <&CPU5>;
  1083. + };
  1084. + core2 {
  1085. + cpu = <&CPU6>;
  1086. + };
  1087. + core3 {
  1088. + cpu = <&CPU7>;
  1089. + };
  1090. + };
  1091. + };
  1092. +
  1093. + CPU0: cpu@0 {
  1094. + device_type = "cpu";
  1095. + compatible = "arm,cortex-a53";
  1096. + reg = <0x0>;
  1097. + enable-method = "qcom,8994-arm-cortex-acc";
  1098. + qcom,acc = <&acc0>;
  1099. + qcom,ldo = <&ldo0>;
  1100. + next-level-cache = <&L2_0>;
  1101. + // The currents(uA) correspond to the frequencies in the
  1102. + // frequency table.
  1103. + current = < 24140 //384000 kHZ
  1104. + 27200 //460800 kHZ
  1105. + 32300 //600000 kHZ
  1106. + 36940 //672000 kHz
  1107. + 41570 //768000 kHZ
  1108. + 49870 //864000 kHZ
  1109. + 57840 //960000 kHZ
  1110. + 79800 //1248000 kHZ
  1111. + 88810 //1344000 kHZ
  1112. + 102400 //1478400 kHZ
  1113. + 110900>; //1555200 kHZ
  1114. + L2_0: l2-cache {
  1115. + compatible = "arm,arch-cache";
  1116. + cache-level = <2>;
  1117. + power-domain = <&l2ccc_0>;
  1118. + qcom,dump-size = <0x0>; /* A53 L2 dump not supported */
  1119. + L2_tlb_0: l2-tlb {
  1120. + qcom,dump-size = <0x4000>;
  1121. + };
  1122. + };
  1123. + L1_I_0: l1-icache {
  1124. + compatible = "arm,arch-cache";
  1125. + qcom,dump-size = <0x9040>;
  1126. + };
  1127. + L1_D_0: l1-dcache {
  1128. + compatible = "arm,arch-cache";
  1129. + qcom,dump-size = <0x9040>;
  1130. + };
  1131. + };
  1132. +
  1133. + CPU1: cpu@1 {
  1134. + device_type = "cpu";
  1135. + compatible = "arm,cortex-a53";
  1136. + reg = <0x1>;
  1137. + enable-method = "qcom,8994-arm-cortex-acc";
  1138. + qcom,acc = <&acc1>;
  1139. + qcom,ldo = <&ldo1>;
  1140. + next-level-cache = <&L2_0>;
  1141. + // The currents(uA) correspond to the frequencies in the
  1142. + // frequency table.
  1143. + current = < 9415 //384000 kHZ
  1144. + 10608 //460800 kHZ
  1145. + 12597 //600000 kHZ
  1146. + 14407 //672000 kHz
  1147. + 16212 //768000 kHZ
  1148. + 19449 //864000 kHZ
  1149. + 22558 //960000 kHZ
  1150. + 31122 //1248000 kHZ
  1151. + 34636 //1344000 kHZ
  1152. + 39936 //1478400 kHZ
  1153. + 43251>; //1555200 kHZ
  1154. + L1_I_1: l1-icache {
  1155. + compatible = "arm,arch-cache";
  1156. + qcom,dump-size = <0x9040>;
  1157. + };
  1158. + L1_D_1: l1-dcache {
  1159. + compatible = "arm,arch-cache";
  1160. + qcom,dump-size = <0x9040>;
  1161. + };
  1162. + };
  1163. +
  1164. + CPU2: cpu@2 {
  1165. + device_type = "cpu";
  1166. + compatible = "arm,cortex-a53";
  1167. + reg = <0x2>;
  1168. + enable-method = "qcom,8994-arm-cortex-acc";
  1169. + qcom,acc = <&acc2>;
  1170. + qcom,ldo = <&ldo2>;
  1171. + next-level-cache = <&L2_0>;
  1172. + // The currents(uA) correspond to the frequencies in the
  1173. + // frequency table.
  1174. + current = < 9656 //384000 kHZ
  1175. + 10880 //460800 kHZ
  1176. + 12920 //600000 kHZ
  1177. + 14776 //672000 kHz
  1178. + 16628 //768000 kHZ
  1179. + 19948 //864000 kHZ
  1180. + 23136 //960000 kHZ
  1181. + 31920 //1248000 kHZ
  1182. + 35524 //1344000 kHZ
  1183. + 40960 //1478400 kHZ
  1184. + 44360>; //1555200 kHZ
  1185. + L1_I_2: l1-icache {
  1186. + compatible = "arm,arch-cache";
  1187. + qcom,dump-size = <0x9040>;
  1188. + };
  1189. + L1_D_2: l1-dcache {
  1190. + compatible = "arm,arch-cache";
  1191. + qcom,dump-size = <0x9040>;
  1192. + };
  1193. + };
  1194. +
  1195. + CPU3: cpu@3 {
  1196. + device_type = "cpu";
  1197. + compatible = "arm,cortex-a53";
  1198. + reg = <0x3>;
  1199. + enable-method = "qcom,8994-arm-cortex-acc";
  1200. + qcom,acc = <&acc3>;
  1201. + qcom,ldo = <&ldo3>;
  1202. + next-level-cache = <&L2_0>;
  1203. + // The currents(uA) correspond to the frequencies in the
  1204. + // frequency table.
  1205. + current = < 10139 //384000 kHZ
  1206. + 11424 //460800 kHZ
  1207. + 13566 //600000 kHZ
  1208. + 15515 //672000 kHz
  1209. + 17459 //768000 kHZ
  1210. + 20945 //864000 kHZ
  1211. + 24293 //960000 kHZ
  1212. + 33516 //1248000 kHZ
  1213. + 37300 //1344000 kHZ
  1214. + 43008 //1478400 kHZ
  1215. + 46578>; //1555200 kHZ
  1216. + L1_I_3: l1-icache {
  1217. + compatible = "arm,arch-cache";
  1218. + qcom,dump-size = <0x9040>;
  1219. + };
  1220. + L1_D_3: l1-dcache {
  1221. + compatible = "arm,arch-cache";
  1222. + qcom,dump-size = <0x9040>;
  1223. + };
  1224. + };
  1225. +
  1226. + CPU4: cpu@4 {
  1227. + device_type = "cpu";
  1228. + compatible = "arm,cortex-a57";
  1229. + reg = <0x100>;
  1230. + enable-method = "qcom,8994-arm-cortex-acc";
  1231. + qcom,acc = <&acc4>;
  1232. + qcom,ldo = <&ldo4>;
  1233. + next-level-cache = <&L2_1>;
  1234. + // The currents(uA) correspond to the frequencies in the
  1235. + // frequency table.
  1236. + current = < 86830 //384000 kHZ
  1237. + 103240 //480000 kHZ
  1238. + 129380 //633600 kHZ
  1239. + 155210 //768000 kHZ
  1240. + 177990 //864000 kHZ
  1241. + 195550 //960000 kHZ
  1242. + 265090 //1248000 kHZ
  1243. + 292770 //1344000 kHZ
  1244. + 322130 //1440000 kHZ
  1245. + 348190 //1536000 kHZ
  1246. + 370180 //1632000 kHZ
  1247. + 235196>; //1728000 kHZ
  1248. + L2_1: l2-cache {
  1249. + compatible = "arm,arch-cache";
  1250. + cache-level = <2>;
  1251. + qcom,dump-size = <0x280040>; /*A57 Cluster L2 size is 1MB */
  1252. + power-domain = <&l2ccc_1>;
  1253. + L2_tlb_1: l2-tlb {
  1254. + qcom,dump-size = <0x4000>;
  1255. + };
  1256. + };
  1257. + L1_itlb_100: l1-itlb {
  1258. + qcom,dump-size = <0x400>;
  1259. + };
  1260. + L1_dtlb_100: l1-dtlb {
  1261. + qcom,dump-size = <0x400>;
  1262. + };
  1263. + L1_I_100: l1-icache {
  1264. + compatible = "arm,arch-cache";
  1265. + qcom,dump-size = <0xd840>;
  1266. + };
  1267. + L1_D_100: l1-dcache {
  1268. + compatible = "arm,arch-cache";
  1269. + qcom,dump-size = <0x9040>;
  1270. + };
  1271. + };
  1272. +
  1273. + CPU5: cpu@5 {
  1274. + device_type = "cpu";
  1275. + compatible = "arm,cortex-a57";
  1276. + reg = <0x101>;
  1277. + enable-method = "qcom,8994-arm-cortex-acc";
  1278. + qcom,acc = <&acc5>;
  1279. + qcom,ldo = <&ldo5>;
  1280. + next-level-cache = <&L2_1>;
  1281. + // The currents(uA) correspond to the frequencies in the
  1282. + // frequency table.
  1283. + current = < 50361 //384000 kHZ
  1284. + 59879 //480000 kHZ
  1285. + 75040 //633600 kHZ
  1286. + 90144 //768000 kHZ
  1287. + 103234 //864000 kHZ
  1288. + 113419 //960000 kHZ
  1289. + 153752 //1248000 kHZ
  1290. + 169807 //1344000 kHZ
  1291. + 186835 //1440000 kHZ
  1292. + 201950 //1536000 kHZ
  1293. + 214704 //1632000 kHZ
  1294. + 235196>; //1728000 kHZ
  1295. + L1_itlb_101: l1-itlb {
  1296. + qcom,dump-size = <0x400>;
  1297. + };
  1298. + L1_dtlb_101: l1-dtlb {
  1299. + qcom,dump-size = <0x400>;
  1300. + };
  1301. + L1_I_101: l1-icache {
  1302. + compatible = "arm,arch-cache";
  1303. + qcom,dump-size = <0xd840>;
  1304. + };
  1305. + L1_D_101: l1-dcache {
  1306. + compatible = "arm,arch-cache";
  1307. + qcom,dump-size = <0x9040>;
  1308. + };
  1309. + };
  1310. +
  1311. + CPU6: cpu@6 {
  1312. + device_type = "cpu";
  1313. + compatible = "arm,cortex-a57";
  1314. + reg = <0x102>;
  1315. + enable-method = "qcom,8994-arm-cortex-acc";
  1316. + qcom,acc = <&acc6>;
  1317. + qcom,ldo = <&ldo6>;
  1318. + next-level-cache = <&L2_1>;
  1319. + // The currents(uA) correspond to the frequencies in the
  1320. + // frequency table.
  1321. + current = < 59913 //384000 kHZ
  1322. + 71236 //480000 kHZ
  1323. + 89272 //633600 kHZ
  1324. + 107240 //768000 kHZ
  1325. + 122813 //864000 kHZ
  1326. + 134930 //960000 kHZ
  1327. + 182912 //1248000 kHZ
  1328. + 202011 //1344000 kHZ
  1329. + 222270 //1440000 kHZ
  1330. + 240251 //1536000 kHZ
  1331. + 255424 //1632000 kHZ
  1332. + 279802>; //1728000 kHZ
  1333. + L1_itlb_102: l1-itlb {
  1334. + qcom,dump-size = <0x400>;
  1335. + };
  1336. + L1_dtlb_102: l1-dtlb {
  1337. + qcom,dump-size = <0x400>;
  1338. + };
  1339. + L1_I_102: l1-icache {
  1340. + compatible = "arm,arch-cache";
  1341. + qcom,dump-size = <0xd840>;
  1342. + };
  1343. + L1_D_102: l1-dcache {
  1344. + compatible = "arm,arch-cache";
  1345. + qcom,dump-size = <0x9040>;
  1346. + };
  1347. + };
  1348. +
  1349. + CPU7: cpu@7 {
  1350. + device_type = "cpu";
  1351. + compatible = "arm,cortex-a57";
  1352. + reg = <0x103>;
  1353. + enable-method = "qcom,8994-arm-cortex-acc";
  1354. + qcom,acc = <&acc7>;
  1355. + qcom,ldo = <&ldo7>;
  1356. + next-level-cache = <&L2_1>;
  1357. + // The currents(uA) correspond to the frequencies in the
  1358. + // frequency table.
  1359. + current = < 62518 //384000 kHZ
  1360. + 74333 //480000 kHZ
  1361. + 93154 //633600 kHZ
  1362. + 111902 //768000 kHZ
  1363. + 128153 //864000 kHZ
  1364. + 140796 //960000 kHZ
  1365. + 190865 //1248000 kHZ
  1366. + 210794 //1344000 kHZ
  1367. + 231934 //1440000 kHZ
  1368. + 250697 //1536000 kHZ
  1369. + 266530 //1632000 kHZ
  1370. + 291967>; //1728000 kHZ
  1371. + L1_itlb_103: l1-itlb {
  1372. + qcom,dump-size = <0x400>;
  1373. + };
  1374. + L1_dtlb_103: l1-dtlb {
  1375. + qcom,dump-size = <0x400>;
  1376. + };
  1377. + L1_I_103: l1-icache {
  1378. + compatible = "arm,arch-cache";
  1379. + qcom,dump-size = <0xd840>;
  1380. + };
  1381. + L1_D_103: l1-dcache {
  1382. + compatible = "arm,arch-cache";
  1383. + qcom,dump-size = <0x9040>;
  1384. + };
  1385. + };
  1386. + };
  1387. +
  1388. + soc: soc { };
  1389. +
  1390. + memory {
  1391. + #address-cells = <2>;
  1392. + #size-cells = <2>;
  1393. +
  1394. + secure_mem: secure_region@0 {
  1395. + linux,reserve-contiguous-region;
  1396. + reg = <0 0 0 0x12c00000>;
  1397. + label = "secure_mem";
  1398. + };
  1399. +
  1400. + adsp_mem: adsp_region@0 {
  1401. + linux,reserve-contiguous-region;
  1402. + reg = <0 0 0 0x3F00000>;
  1403. + label = "adsp_mem";
  1404. + };
  1405. +
  1406. + qsecom_mem: qsecom_region@0 {
  1407. + linux,reserve-contiguous-region;
  1408. + reg = <0 0 0 0x1800000>;
  1409. + label = "qseecom_mem";
  1410. + };
  1411. +
  1412. + audio_mem: audio_region@0 {
  1413. + linux,reserve-contiguous-region;
  1414. + linux,reserve-region;
  1415. + reg = <0 0 0 0x614000>;
  1416. + label = "audio_mem";
  1417. + };
  1418. +
  1419. + removed_regions: removed_regions@0 {
  1420. + linux,reserve-contiguous-region;
  1421. + linux,reserve-region;
  1422. + linux,remove-completely;
  1423. + reg = <0 0x06300000 0 0xD00000>;
  1424. + label = "memory_hole";
  1425. + };
  1426. + /*#ifdef VENDOR_EDIT*/
  1427. + nvbackup_regions: nvbackup_regions@0 {
  1428. + linux,reserve-contiguous-region;
  1429. + oem,reserve-region;
  1430. + reg = <0 0x06200000 0 0x100000>;
  1431. + label = "memory_nvbackup";
  1432. + };
  1433. + /*#endif VENDOR_EDIT*/
  1434. + dfps_data_mem: dfps_data_mem@0 {
  1435. + linux,reserve-contiguous-region;
  1436. + linux,reserve-region;
  1437. + reg = <0 0x03400000 0 0x1000>;
  1438. + label = "dfps_data_mem";
  1439. + };
  1440. + cont_splash_mem: cont_splash_mem@0 {
  1441. + linux,reserve-contiguous-region;
  1442. + linux,reserve-region;
  1443. + reg = <0 0x03401000 0 0x2200000>;
  1444. + label = "cont_splash_mem";
  1445. + };
  1446. +
  1447. + peripheral_mem: peripheral_region@0 {
  1448. + linux,reserve-contiguous-region;
  1449. + linux,reserve-region;
  1450. + linux,remove-completely;
  1451. + reg = <0 0x0ca00000 0 0x1f00000>;
  1452. + label = "peripheral_mem";
  1453. + };
  1454. +/*#ifdef VENDOR_EDIT //changhua.li add for enlarge TZ APP memory to 25M*/
  1455. + tzapp_mem: tzapp_region@0 {
  1456. +
  1457. + linux,reserve-contiguous-region;
  1458. +
  1459. + linux,reserve-region;
  1460. +
  1461. + linux,remove-completely;
  1462. +
  1463. + reg = <0 0x0E900000 0 0x1900000>;
  1464. +
  1465. + label = "tzapp_mem";
  1466. +
  1467. + };
  1468. +/*#endif VENDOR_EDIT*/
  1469. +
  1470. +
  1471. + modem_mem: modem_region@0 {
  1472. + linux,reserve-contiguous-region;
  1473. + linux,reserve-region;
  1474. + linux,remove-completely;
  1475. + reg = <0 0x07000000 0 0x5a00000>;
  1476. + label = "modem_mem";
  1477. + };
  1478. +
  1479. +/* #ifdef VENDOR_EDIT // add by xcb for ramoops 2015-03-31 */
  1480. + ramoops_mem: ramoops_region@0 {
  1481. + linux,reserve-contiguous-region;
  1482. + oem,reserve-region;//modify by jiachenghui for ramoops reserve region
  1483. + //linux,remove-completely;//del by jiachenghui for ramoops reserve region
  1484. + reg = <0 0xac000000 0 0x00100000>;//modify from 0x05800000 to 0xac000000 by jiachenghui for ramoops reserve region
  1485. + label = "ramoops_mem";
  1486. + };
  1487. +/* #endif VENDOR_EDIT */
  1488. +
  1489. + param_mem: param_region@0 {
  1490. + linux,reserve-contiguous-region;
  1491. + oem,reserve-region;
  1492. + //linux,remove-completely;
  1493. + reg = <0 0xac200000 0 0x00100000>;
  1494. + label = "param_mem";
  1495. + };
  1496. + mtp_regions: mtp_regions@0 {
  1497. + linux,reserve-contiguous-region;
  1498. + oem,reserve-region;
  1499. + reg = <0 0xAC400000 0 0x00100000>;
  1500. + label = "memory_mtp";
  1501. + };
  1502. + };
  1503. +};
  1504. +
  1505. +#include "msm-gdsc.dtsi"
  1506. +#include "msm8994-smp2p.dtsi"
  1507. +#include "msm8994-ipcrouter.dtsi"
  1508. +#include "msm8994-mdss.dtsi"
  1509. +#include "msm8994-mdss-pll.dtsi"
  1510. +#include "msm8994-bus.dtsi"
  1511. +
  1512. +&soc {
  1513. + #address-cells = <1>;
  1514. + #size-cells = <1>;
  1515. + ranges = <0 0 0 0xffffffff>;
  1516. + compatible = "simple-bus";
  1517. +
  1518. + cpuss@fd4a8000 {
  1519. + compatible = "qcom,cpuss-8994";
  1520. + reg = <0xfd4a8000 0x4>;
  1521. + };
  1522. +
  1523. + acc0:clock-controller@f908b004 {
  1524. + compatible = "qcom,arm-cortex-acc";
  1525. + reg = <0xf9070000 0x1000>,
  1526. + <0xf908b000 0x1000>,
  1527. + <0xf900b000 0x1000>;
  1528. + };
  1529. +
  1530. + acc1:clock-controller@f909b004 {
  1531. + compatible = "qcom,arm-cortex-acc";
  1532. + reg = <0xf9071000 0x1000>,
  1533. + <0xf909b000 0x1000>,
  1534. + <0xf900b000 0x1000>;
  1535. + };
  1536. +
  1537. + acc2:clock-controller@f90ab004 {
  1538. + compatible = "qcom,arm-cortex-acc";
  1539. + reg = <0xf9072000 0x1000>,
  1540. + <0xf90ab000 0x1000>,
  1541. + <0xf900b000 0x1000>;
  1542. + };
  1543. +
  1544. + acc3:clock-controller@f90bb004 {
  1545. + compatible = "qcom,arm-cortex-acc";
  1546. + reg = <0xf9073000 0x1000>,
  1547. + <0xf90bb000 0x1000>,
  1548. + <0xf900b000 0x1000>;
  1549. + };
  1550. +
  1551. + acc4:clock-controller@f90cb004 {
  1552. + compatible = "qcom,arm-cortex-acc";
  1553. + reg = <0xf9074000 0x1000>,
  1554. + <0xf90cb000 0x1000>,
  1555. + <0xf900b000 0x1000>;
  1556. + };
  1557. +
  1558. + acc5:clock-controller@f90db004 {
  1559. + compatible = "qcom,arm-cortex-acc";
  1560. + reg = <0xf9075000 0x1000>,
  1561. + <0xf90db000 0x1000>,
  1562. + <0xf900b000 0x1000>;
  1563. + };
  1564. +
  1565. + acc6:clock-controller@f90eb004 {
  1566. + compatible = "qcom,arm-cortex-acc";
  1567. + reg = <0xf9076000 0x1000>,
  1568. + <0xf90eb000 0x1000>,
  1569. + <0xf900b000 0x1000>;
  1570. + };
  1571. +
  1572. + acc7:clock-controller@f90fb004 {
  1573. + compatible = "qcom,arm-cortex-acc";
  1574. + reg = <0xf9077000 0x1000>,
  1575. + <0xf90fb000 0x1000>,
  1576. + <0xf900b000 0x1000>;
  1577. + };
  1578. +
  1579. + ldo0:ldo-vref@f9070000 {
  1580. + compatible = "qcom,8994-cpu-ldo-vref";
  1581. + reg = <0xf9070000 0x30>;
  1582. + qcom,ldo-vref-ret = <0x2a>;
  1583. + };
  1584. +
  1585. + ldo1:ldo-vref@f9071000 {
  1586. + compatible = "qcom,8994-cpu-ldo-vref";
  1587. + reg = <0xf9071000 0x30>;
  1588. + qcom,ldo-vref-ret = <0x2a>;
  1589. + };
  1590. +
  1591. + ldo2:ldo-vref@f9072000 {
  1592. + compatible = "qcom,8994-cpu-ldo-vref";
  1593. + reg = <0xf9072000 0x30>;
  1594. + qcom,ldo-vref-ret = <0x2a>;
  1595. + };
  1596. +
  1597. + ldo3:ldo-vref@f9073000 {
  1598. + compatible = "qcom,8994-cpu-ldo-vref";
  1599. + reg = <0xf9073000 0x30>;
  1600. + qcom,ldo-vref-ret = <0x2a>;
  1601. + };
  1602. +
  1603. + ldo4:ldo-vref@f9074000 {
  1604. + compatible = "qcom,8994-cpu-ldo-vref";
  1605. + reg = <0xf9074000 0x30>;
  1606. + qcom,ldo-vref-ret = <0x3e>;
  1607. + };
  1608. +
  1609. + ldo5:ldo-vref@f9075000 {
  1610. + compatible = "qcom,8994-cpu-ldo-vref";
  1611. + reg = <0xf9075000 0x30>;
  1612. + qcom,ldo-vref-ret = <0x3e>;
  1613. + };
  1614. +
  1615. + ldo6:ldo-vref@f9076000 {
  1616. + compatible = "qcom,8994-cpu-ldo-vref";
  1617. + reg = <0xf9076000 0x30>;
  1618. + qcom,ldo-vref-ret = <0x3e>;
  1619. + };
  1620. +
  1621. + ldo7:ldo-vref@f9077000 {
  1622. + compatible = "qcom,8994-cpu-ldo-vref";
  1623. + reg = <0xf9077000 0x30>;
  1624. + qcom,ldo-vref-ret = <0x3e>;
  1625. + };
  1626. +
  1627. + l2ccc_0: clock-controller@f900d000 {
  1628. + compatible = "qcom,8994-l2ccc";
  1629. + reg = <0xf900d000 0x1000>,
  1630. + <0xf911210c 0x4>;
  1631. + qcom,vctl-node = <&cluster0_spm>;
  1632. + };
  1633. +
  1634. + l2ccc_1: clock-controller@f900f000 {
  1635. + compatible = "qcom,8994-l2ccc";
  1636. + reg = <0xf900f000 0x1000>,
  1637. + <0xf911210c 0x4>;
  1638. + qcom,vctl-node = <&cluster1_spm>;
  1639. + qcom,vctl-val = <0xb8>;
  1640. + };
  1641. +
  1642. + intc: interrupt-controller@f9000000 {
  1643. + compatible = "qcom,msm-qgic2";
  1644. + interrupt-controller;
  1645. + #interrupt-cells = <3>;
  1646. + reg = <0xf9000000 0x1000>,
  1647. + <0xf9002000 0x1000>;
  1648. + };
  1649. +
  1650. + timer {
  1651. + compatible = "arm,armv8-timer";
  1652. + interrupts = <1 2 0xff08>,
  1653. + <1 3 0xff08>,
  1654. + <1 4 0xff08>,
  1655. + <1 1 0xff08>;
  1656. + clock-frequency = <19200000>;
  1657. + };
  1658. +
  1659. + qcom,mpm2-sleep-counter@fc4a3000 {
  1660. + compatible = "qcom,mpm2-sleep-counter";
  1661. + reg = <0xfc4a3000 0x1000>;
  1662. + clock-frequency = <32768>;
  1663. + };
  1664. +
  1665. + timer@f9020000 {
  1666. + #address-cells = <1>;
  1667. + #size-cells = <1>;
  1668. + ranges;
  1669. + compatible = "arm,armv7-timer-mem";
  1670. + reg = <0xf9020000 0x1000>;
  1671. + clock-frequency = <19200000>;
  1672. +
  1673. + frame@f9021000 {
  1674. + frame-number = <0>;
  1675. + interrupts = <0 9 0x4>,
  1676. + <0 8 0x4>;
  1677. + reg = <0xf9021000 0x1000>,
  1678. + <0xf9022000 0x1000>;
  1679. + };
  1680. +
  1681. + frame@f9023000 {
  1682. + frame-number = <1>;
  1683. + interrupts = <0 10 0x4>;
  1684. + reg = <0xf9023000 0x1000>;
  1685. + status = "disabled";
  1686. + };
  1687. +
  1688. + frame@f9024000 {
  1689. + frame-number = <2>;
  1690. + interrupts = <0 11 0x4>;
  1691. + reg = <0xf9024000 0x1000>;
  1692. + status = "disabled";
  1693. + };
  1694. +
  1695. + frame@f9025000 {
  1696. + frame-number = <3>;
  1697. + interrupts = <0 12 0x4>;
  1698. + reg = <0xf9025000 0x1000>;
  1699. + status = "disabled";
  1700. + };
  1701. +
  1702. + frame@f9026000 {
  1703. + frame-number = <4>;
  1704. + interrupts = <0 13 0x4>;
  1705. + reg = <0xf9026000 0x1000>;
  1706. + status = "disabled";
  1707. + };
  1708. +
  1709. + frame@f9027000 {
  1710. + frame-number = <5>;
  1711. + interrupts = <0 14 0x4>;
  1712. + reg = <0xf9027000 0x1000>;
  1713. + status = "disabled";
  1714. + };
  1715. +
  1716. + frame@f9028000 {
  1717. + frame-number = <6>;
  1718. + interrupts = <0 15 0x4>;
  1719. + reg = <0xf9028000 0x1000>;
  1720. + status = "disabled";
  1721. + };
  1722. + };
  1723. +
  1724. + restart@fc4ab000 {
  1725. + compatible = "qcom,pshold";
  1726. + reg = <0xfc4ab000 0x4>;
  1727. + };
  1728. +
  1729. + blsp1_uart3: serial@f991f000 {
  1730. + compatible = "qcom,msm-lsuart-v14";
  1731. + reg = <0xf991f000 0x1000>;
  1732. + interrupts = <0 109 0>;
  1733. + status = "disabled";
  1734. + clock-names = "core_clk", "iface_clk";
  1735. + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
  1736. + <&clock_gcc clk_gcc_blsp1_ahb_clk>;
  1737. + };
  1738. +
  1739. + blsp1_uart2: serial@f991e000 {
  1740. + compatible = "qcom,msm-lsuart-v14";
  1741. + reg = <0xf991e000 0x1000>;
  1742. + interrupts = <0 108 0>;
  1743. + status = "disabled";
  1744. + clock-names = "core_clk", "iface_clk";
  1745. + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
  1746. + <&clock_gcc clk_gcc_blsp1_ahb_clk>;
  1747. + };
  1748. +
  1749. + blsp2_uart2: uart@f995e000 { /* BLSP2 UART2 */
  1750. + compatible = "qcom,msm-hsuart-v14";
  1751. + reg = <0xf995e000 0x1000>,
  1752. + <0xf9944000 0x19000>;
  1753. + status = "disabled";
  1754. + reg-names = "core_mem", "bam_mem";
  1755. + interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
  1756. + #address-cells = <0>;
  1757. + interrupt-parent = <&blsp2_uart2>;
  1758. + interrupts = <0 1 2>;
  1759. + #interrupt-cells = <1>;
  1760. + interrupt-map-mask = <0xffffffff>;
  1761. + interrupt-map = <0 &intc 0 114 0
  1762. + 1 &intc 0 239 0
  1763. + 2 &msm_gpio 46 0>;
  1764. +
  1765. + qcom,inject-rx-on-wakeup;
  1766. + qcom,rx-char-to-inject = <0xFD>;
  1767. +
  1768. + qcom,bam-tx-ep-pipe-index = <2>;
  1769. + qcom,bam-rx-ep-pipe-index = <3>;
  1770. + qcom,master-id = <84>;
  1771. + clock-names = "core_clk", "iface_clk";
  1772. + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
  1773. + <&clock_gcc clk_gcc_blsp2_ahb_clk>;
  1774. + pinctrl-names = "sleep", "default";
  1775. + pinctrl-0 = <&hsuart_sleep>;
  1776. + pinctrl-1 = <&hsuart_active>;
  1777. +
  1778. + qcom,msm-bus,name = "buart8";
  1779. + qcom,msm-bus,num-cases = <2>;
  1780. + qcom,msm-bus,num-paths = <1>;
  1781. + qcom,msm-bus,vectors-KBps =
  1782. + <84 512 0 0>,
  1783. + <84 512 500 800>;
  1784. + };
  1785. +
  1786. + qcom,sps@f9984000 {
  1787. + compatible = "qcom,msm_sps";
  1788. + reg-names = "bam_mem", "core_mem";
  1789. + reg = <0xf9984000 0x15000>,
  1790. + <0xf9999000 0xb000>;
  1791. + interrupts = <0 94 0>;
  1792. + qcom,pipe-attr-ee;
  1793. + clocks = <&clock_rpm clk_pnoc_sps_clk>,
  1794. + <&clock_gcc clk_gcc_bam_dma_ahb_clk>;
  1795. + clock-names = "dfab_clk", "dma_bam_pclk";
  1796. + };
  1797. +
  1798. + pcie0: qcom,pcie@fc520000 {
  1799. + compatible = "qcom,pci-msm";
  1800. + cell-index = <0>;
  1801. +
  1802. + reg = <0xfc520000 0x2000>,
  1803. + <0xfc526000 0x1000>,
  1804. + <0xff000000 0xf1d>,
  1805. + <0xff000f20 0xa8>,
  1806. + <0xff100000 0x100000>,
  1807. + <0xff200000 0x100000>,
  1808. + <0xff300000 0xd00000>;
  1809. +
  1810. + reg-names = "parf", "phy", "dm_core", "elbi",
  1811. + "conf", "io", "bars";
  1812. +
  1813. + #address-cells = <0>;
  1814. + interrupt-parent = <&pcie0>;
  1815. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
  1816. + #interrupt-cells = <1>;
  1817. + interrupt-map-mask = <0xffffffff>;
  1818. + interrupt-map = <0 &intc 0 243 0
  1819. + 1 &intc 0 244 0
  1820. + 2 &intc 0 245 0
  1821. + 3 &intc 0 247 0
  1822. + 4 &intc 0 248 0
  1823. + 5 &intc 0 249 0
  1824. + 6 &intc 0 250 0
  1825. + 7 &intc 0 251 0
  1826. + 8 &intc 0 252 0
  1827. + 9 &intc 0 253 0
  1828. + 10 &intc 0 254 0
  1829. + 11 &intc 0 255 0>;
  1830. +
  1831. + interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
  1832. + "int_pls_pme", "int_pme_legacy", "int_pls_err",
  1833. + "int_aer_legacy", "int_pls_link_up",
  1834. + "int_pls_link_down", "int_bridge_flush_n";
  1835. +
  1836. + pinctrl-names = "default";
  1837. + pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
  1838. +
  1839. + perst-gpio = <&msm_gpio 53 0>;
  1840. + wake-gpio = <&msm_gpio 55 0>;
  1841. +
  1842. + gdsc-vdd-supply = <&gdsc_pcie_0>;
  1843. + vreg-1.8-supply = <&pm8994_l12>;
  1844. + vreg-0.9-supply = <&pm8994_l28>;
  1845. +
  1846. + qcom,ep-latency = <10>;
  1847. +
  1848. + qcom,msi-gicm-addr = <0xf9006040>;
  1849. + qcom,msi-gicm-base = <0x180>;
  1850. +
  1851. + qcom,msm-bus,name = "pcie0";
  1852. + qcom,msm-bus,num-cases = <2>;
  1853. + qcom,msm-bus,num-paths = <1>;
  1854. + qcom,msm-bus,vectors-KBps =
  1855. + <45 512 0 0>,
  1856. + <45 512 500 800>;
  1857. +
  1858. + qcom,scm-dev-id = <11>;
  1859. +
  1860. + clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
  1861. + <&clock_rpm clk_ln_bb_clk>,
  1862. + <&clock_gcc clk_gcc_pcie_0_aux_clk>,
  1863. + <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
  1864. + <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
  1865. + <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
  1866. + <&clock_gcc clk_pcie_0_phy_ldo>,
  1867. + <&clock_gcc clk_gcc_pcie_phy_0_reset>;
  1868. +
  1869. + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk",
  1870. + "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",
  1871. + "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_phy_reset";
  1872. +
  1873. + max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;
  1874. + };
  1875. +
  1876. + pcie1: qcom,pcie@fc528000 {
  1877. + compatible = "qcom,pci-msm";
  1878. + cell-index = <1>;
  1879. +
  1880. + reg = <0xfc528000 0x2000>,
  1881. + <0xfc52e000 0x1000>,
  1882. + <0xf8800000 0xf1d>,
  1883. + <0xf8800F20 0xa8>,
  1884. + <0xf8801000 0x7f000>,
  1885. + <0xf8880000 0x80000>,
  1886. + <0xf8900000 0x700000>;
  1887. +
  1888. + reg-names = "parf", "phy", "dm_core", "elbi",
  1889. + "conf", "io", "bars";
  1890. +
  1891. + #address-cells = <0>;
  1892. + interrupt-parent = <&pcie1>;
  1893. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
  1894. + #interrupt-cells = <1>;
  1895. + interrupt-map-mask = <0xffffffff>;
  1896. + interrupt-map = <0 &intc 0 271 0
  1897. + 1 &intc 0 272 0
  1898. + 2 &intc 0 273 0
  1899. + 3 &intc 0 274 0
  1900. + 4 &intc 0 275 0
  1901. + 5 &intc 0 276 0
  1902. + 6 &intc 0 277 0
  1903. + 7 &intc 0 278 0
  1904. + 8 &intc 0 279 0
  1905. + 9 &intc 0 280 0
  1906. + 10 &intc 0 281 0
  1907. + 11 &intc 0 282 0>;
  1908. +
  1909. + interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
  1910. + "int_pls_pme", "int_pme_legacy", "int_pls_err",
  1911. + "int_aer_legacy", "int_pls_link_up",
  1912. + "int_pls_link_down", "int_bridge_flush_n";
  1913. +
  1914. + pinctrl-names = "default", "sleep";
  1915. + pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
  1916. + pinctrl-1 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_sleep>;
  1917. +
  1918. + perst-gpio = <&msm_gpio 35 0>;
  1919. + wake-gpio = <&msm_gpio 37 0>;
  1920. +
  1921. + gdsc-vdd-supply = <&gdsc_pcie_1>;
  1922. + vreg-1.8-supply = <&pm8994_l12>;
  1923. + vreg-0.9-supply = <&pm8994_l28>;
  1924. +
  1925. + qcom,l1-supported;
  1926. + qcom,l1ss-supported;
  1927. + qcom,aux-clk-sync;
  1928. +
  1929. + qcom,ep-latency = <10>;
  1930. +
  1931. + qcom,msi-gicm-addr = <0xf9007040>;
  1932. + qcom,msi-gicm-base = <0x1a0>;
  1933. +
  1934. + qcom,ep-wakeirq;
  1935. +
  1936. + qcom,msm-bus,name = "pcie1";
  1937. + qcom,msm-bus,num-cases = <2>;
  1938. + qcom,msm-bus,num-paths = <1>;
  1939. + qcom,msm-bus,vectors-KBps =
  1940. + <100 512 0 0>,
  1941. + <100 512 500 800>;
  1942. +
  1943. + qcom,scm-dev-id = <12>;
  1944. +
  1945. + clocks = <&clock_gcc clk_gcc_pcie_1_pipe_clk>,
  1946. + <&clock_rpm clk_ln_bb_clk>,
  1947. + <&clock_gcc clk_gcc_pcie_1_aux_clk>,
  1948. + <&clock_gcc clk_gcc_pcie_1_cfg_ahb_clk>,
  1949. + <&clock_gcc clk_gcc_pcie_1_mstr_axi_clk>,
  1950. + <&clock_gcc clk_gcc_pcie_1_slv_axi_clk>,
  1951. + <&clock_gcc clk_pcie_1_phy_ldo>,
  1952. + <&clock_gcc clk_gcc_pcie_phy_1_reset>;
  1953. +
  1954. + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk",
  1955. + "pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk",
  1956. + "pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_phy_reset";
  1957. +
  1958. + max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;
  1959. + };
  1960. +
  1961. + ipa_hw: qcom,ipa@fd4c0000 {
  1962. + compatible = "qcom,ipa";
  1963. + reg = <0xfd4c0000 0x29000>,
  1964. + <0xfd4c4000 0x15820>;
  1965. + reg-names = "ipa-base", "bam-base";
  1966. + interrupts = <0 301 0>,
  1967. + <0 300 0>;
  1968. + interrupt-names = "ipa-irq", "bam-irq";
  1969. + qcom,ipa-hw-ver = <3>; /* IPA core version = IPAv2.0 */
  1970. + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
  1971. + qcom,wan-rx-ring-size = <192>;
  1972. + qcom,ee = <2>;
  1973. + clock-names = "core_clk";
  1974. + clocks = <&clock_rpm clk_ipa_clk>;
  1975. + qcom,msm-bus,name = "ipa";
  1976. + qcom,msm-bus,num-cases = <3>;
  1977. + qcom,msm-bus,num-paths = <2>;
  1978. + qcom,msm-bus,vectors-KBps =
  1979. + <90 512 0 0>, <90 585 0 0>, /* No vote */
  1980. + <90 512 100000 800000>, <90 585 100000 800000>, /* SVS */
  1981. + <90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */
  1982. + qcom,bus-vector-names = "MIN", "SVS", "PERF";
  1983. +
  1984. + };
  1985. +
  1986. + qcom,rmnet-ipa {
  1987. + compatible = "qcom,rmnet-ipa";
  1988. + qcom,rmnet-ipa-ssr;
  1989. + qcom,ipa-loaduC;
  1990. + };
  1991. +
  1992. + qcom,ipc-spinlock@fd484000 {
  1993. + compatible = "qcom,ipc-spinlock-sfpb";
  1994. + reg = <0xfd484000 0x400>;
  1995. + qcom,num-locks = <8>;
  1996. + };
  1997. +
  1998. + qcom,smem@6a00000 {
  1999. + compatible = "qcom,smem";
  2000. + reg = <0x6a00000 0x200000>,
  2001. + <0xf900d008 0x4>,
  2002. + <0xfc428000 0x4000>;
  2003. + reg-names = "smem", "irq-reg-base", "aux-mem1";
  2004. + qcom,mpu-enabled;
  2005. +
  2006. + qcom,smd-modem {
  2007. + compatible = "qcom,smd";
  2008. + qcom,smd-edge = <0>;
  2009. + qcom,smd-irq-offset = <0x0>;
  2010. + qcom,smd-irq-bitmask = <0x1000>;
  2011. + interrupts = <0 25 1>;
  2012. + label = "modem";
  2013. + qcom,not-loadable;
  2014. + };
  2015. +
  2016. + qcom,smsm-modem {
  2017. + compatible = "qcom,smsm";
  2018. + qcom,smsm-edge = <0>;
  2019. + qcom,smsm-irq-offset = <0x0>;
  2020. + qcom,smsm-irq-bitmask = <0x2000>;
  2021. + interrupts = <0 26 1>;
  2022. + };
  2023. +
  2024. + qcom,smd-adsp {
  2025. + compatible = "qcom,smd";
  2026. + qcom,smd-edge = <1>;
  2027. + qcom,smd-irq-offset = <0x0>;
  2028. + qcom,smd-irq-bitmask = <0x100>;
  2029. + interrupts = <0 156 1>;
  2030. + label = "adsp";
  2031. + };
  2032. +
  2033. + qcom,smsm-adsp {
  2034. + compatible = "qcom,smsm";
  2035. + qcom,smsm-edge = <1>;
  2036. + qcom,smsm-irq-offset = <0x0>;
  2037. + qcom,smsm-irq-bitmask = <0x200>;
  2038. + interrupts = <0 157 1>;
  2039. + };
  2040. +
  2041. + qcom,smd-rpm {
  2042. + compatible = "qcom,smd";
  2043. + qcom,smd-edge = <15>;
  2044. + qcom,smd-irq-offset = <0x0>;
  2045. + qcom,smd-irq-bitmask = <0x1>;
  2046. + interrupts = <0 168 1>;
  2047. + label = "rpm";
  2048. + qcom,irq-no-suspend;
  2049. + qcom,not-loadable;
  2050. + };
  2051. + };
  2052. +
  2053. + qcom,msm-imem@fe87f000 {
  2054. + compatible = "qcom,msm-imem";
  2055. + reg = <0xfe87f000 0x1000>; /* Address and size of IMEM */
  2056. + ranges = <0x0 0xfe87f000 0x1000>;
  2057. + #address-cells = <1>;
  2058. + #size-cells = <1>;
  2059. +
  2060. + download_mode@0 {
  2061. + compatible = "qcom,msm-imem-download_mode";
  2062. + reg = <0x0 8>;
  2063. + };
  2064. +
  2065. + mem_dump_table@10 {
  2066. + compatible = "qcom,msm-imem-mem_dump_table";
  2067. + reg = <0x10 8>;
  2068. + };
  2069. +
  2070. + restart_reason@65c {
  2071. + compatible = "qcom,msm-imem-restart_reason";
  2072. + reg = <0x65c 4>;
  2073. + };
  2074. +
  2075. + boot_stats@6b0 {
  2076. + compatible = "qcom,msm-imem-boot_stats";
  2077. + reg = <0x6b0 32>;
  2078. + };
  2079. +
  2080. + pil@94c {
  2081. + compatible = "qcom,msm-imem-pil";
  2082. + reg = <0x94c 200>;
  2083. + };
  2084. +
  2085. + emergency_download_mode@fe0 {
  2086. + compatible = "qcom,msm-imem-emergency_download_mode";
  2087. + reg = <0xfe0 12>;
  2088. + };
  2089. + };
  2090. +
  2091. + qcom,wdt@f9017000 {
  2092. + compatible = "qcom,msm-watchdog";
  2093. + reg = <0xf9017000 0x1000>;
  2094. + reg-names = "wdt-base";
  2095. + interrupts = <0 3 0>, <0 4 0>;
  2096. +//liyunbing@BSP, 2015/05/21, WDT bark-time too short cause some task timeout
  2097. + #qcom,bark-time = <11000>;
  2098. + qcom,bark-time = <15000>;
  2099. + qcom,pet-time = <10000>;
  2100. + qcom,ipi-ping;
  2101. + };
  2102. +
  2103. + qcom,msm-rtb {
  2104. + compatible = "qcom,msm-rtb";
  2105. + qcom,rtb-size = <0x100000>;
  2106. + };
  2107. +
  2108. + jtag_fuse: jtagfuse@fc4be024 {
  2109. + compatible = "qcom,jtag-fuse";
  2110. + reg = <0xfc4be024 0x8>;
  2111. + reg-names = "fuse-base";
  2112. + };
  2113. +
  2114. + jtag_mm0: jtagmm@fb840000 {
  2115. + compatible = "qcom,jtagv8-mm";
  2116. + reg = <0xfb840000 0x1000>,
  2117. + <0xfb810000 0x1000>;
  2118. + reg-names = "etm-base","debug-base";
  2119. +
  2120. + clocks = <&clock_rpm clk_qdss_clk>,
  2121. + <&clock_rpm clk_qdss_a_clk>;
  2122. + clock-names = "core_clk", "core_a_clk";
  2123. +
  2124. + qcom,coresight-jtagmm-cpu = <&CPU0>;
  2125. + };
  2126. +
  2127. + jtag_mm1: jtagmm@fb940000 {
  2128. + compatible = "qcom,jtagv8-mm";
  2129. + reg = <0xfb940000 0x1000>,
  2130. + <0xfb910000 0x1000>;
  2131. + reg-names = "etm-base","debug-base";
  2132. +
  2133. + clocks = <&clock_rpm clk_qdss_clk>,
  2134. + <&clock_rpm clk_qdss_a_clk>;
  2135. + clock-names = "core_clk", "core_a_clk";
  2136. +
  2137. + qcom,coresight-jtagmm-cpu = <&CPU1>;
  2138. + };
  2139. +
  2140. + jtag_mm2: jtagmm@fba40000 {
  2141. + compatible = "qcom,jtagv8-mm";
  2142. + reg = <0xfba40000 0x1000>,
  2143. + <0xfba10000 0x1000>;
  2144. + reg-names = "etm-base","debug-base";
  2145. +
  2146. + clocks = <&clock_rpm clk_qdss_clk>,
  2147. + <&clock_rpm clk_qdss_a_clk>;
  2148. + clock-names = "core_clk", "core_a_clk";
  2149. +
  2150. + qcom,coresight-jtagmm-cpu = <&CPU2>;
  2151. + };
  2152. +
  2153. + jtag_mm3: jtagmm@fbb40000 {
  2154. + compatible = "qcom,jtagv8-mm";
  2155. + reg = <0xfbb40000 0x1000>,
  2156. + <0xfbb10000 0x1000>;
  2157. + reg-names = "etm-base","debug-base";
  2158. +
  2159. + clocks = <&clock_rpm clk_qdss_clk>,
  2160. + <&clock_rpm clk_qdss_a_clk>;
  2161. + clock-names = "core_clk", "core_a_clk";
  2162. +
  2163. + qcom,coresight-jtagmm-cpu = <&CPU3>;
  2164. + };
  2165. +
  2166. + jtag_mm4: jtagmm@fbc40000 {
  2167. + compatible = "qcom,jtagv8-mm";
  2168. + reg = <0xfbc40000 0x1000>,
  2169. + <0xfbc10000 0x1000>;
  2170. + reg-names = "etm-base","debug-base";
  2171. +
  2172. + clocks = <&clock_rpm clk_qdss_clk>,
  2173. + <&clock_rpm clk_qdss_a_clk>;
  2174. + clock-names = "core_clk", "core_a_clk";
  2175. +
  2176. + qcom,coresight-jtagmm-cpu = <&CPU4>;
  2177. + };
  2178. +
  2179. + jtag_mm5: jtagmm@fbd40000 {
  2180. + compatible = "qcom,jtagv8-mm";
  2181. + reg = <0xfbd40000 0x1000>,
  2182. + <0xfbd10000 0x1000>;
  2183. + reg-names = "etm-base","debug-base";
  2184. +
  2185. + clocks = <&clock_rpm clk_qdss_clk>,
  2186. + <&clock_rpm clk_qdss_a_clk>;
  2187. + clock-names = "core_clk", "core_a_clk";
  2188. +
  2189. + qcom,coresight-jtagmm-cpu = <&CPU5>;
  2190. + };
  2191. +
  2192. + jtag_mm6: jtagmm@fbe40000 {
  2193. + compatible = "qcom,jtagv8-mm";
  2194. + reg = <0xfbe40000 0x1000>,
  2195. + <0xfbe10000 0x1000>;
  2196. + reg-names = "etm-base","debug-base";
  2197. +
  2198. + clocks = <&clock_rpm clk_qdss_clk>,
  2199. + <&clock_rpm clk_qdss_a_clk>;
  2200. + clock-names = "core_clk", "core_a_clk";
  2201. +
  2202. + qcom,coresight-jtagmm-cpu = <&CPU6>;
  2203. + };
  2204. +
  2205. + jtag_mm7: jtagmm@fbf40000 {
  2206. + compatible = "qcom,jtagv8-mm";
  2207. + reg = <0xfbf40000 0x1000>,
  2208. + <0xfbf10000 0x1000>;
  2209. + reg-names = "etm-base","debug-base";
  2210. +
  2211. + clocks = <&clock_rpm clk_qdss_clk>,
  2212. + <&clock_rpm clk_qdss_a_clk>;
  2213. + clock-names = "core_clk", "core_a_clk";
  2214. +
  2215. + qcom,coresight-jtagmm-cpu = <&CPU7>;
  2216. + };
  2217. +
  2218. + rpm_bus: qcom,rpm-smd {
  2219. + compatible = "qcom,rpm-smd";
  2220. + rpm-channel-name = "rpm_requests";
  2221. + rpm-channel-type = <15>; /* SMD_APPS_RPM */
  2222. + };
  2223. +
  2224. + qcom,msm-rng@f9bff000 {
  2225. + compatible = "qcom,msm-rng";
  2226. + reg = <0xf9bff000 0x200>;
  2227. + qcom,msm-bus,name = "msm-rng-noc";
  2228. + qcom,msm-bus,num-cases = <2>;
  2229. + qcom,msm-bus,num-paths = <1>;
  2230. + qcom,msm-bus,vectors-KBps =
  2231. + <88 618 0 0>,
  2232. + <88 618 0 800>;
  2233. + qcom,msm-rng-iface-clk;
  2234. + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
  2235. + clock-names = "iface_clk";
  2236. + };
  2237. +
  2238. + qcom,rmtfs_sharedmem@00000000 {
  2239. + compatible = "qcom,sharedmem-uio";
  2240. + reg = <0x00000000 0x00180000>;
  2241. + reg-names = "rmtfs";
  2242. + qcom,client-id = <0x00000001>;
  2243. + };
  2244. +
  2245. + qcom,dsp_sharedmem@00000000 {
  2246. + compatible = "qcom,sharedmem-uio";
  2247. + reg = <0x00000000 0x00010000>;
  2248. + reg-names = "rfsa_dsp";
  2249. + qcom,client-id = <0x011013ec>;
  2250. + linux,contiguous-region = <&adsp_mem>;
  2251. + };
  2252. +
  2253. + qcom,mdm_sharedmem@00000000 {
  2254. + compatible = "qcom,sharedmem-uio";
  2255. + reg = <0x00000000 0x00010000>;
  2256. + reg-names = "rfsa_mdm";
  2257. + qcom,client-id = <0x011013ed>;
  2258. + };
  2259. +
  2260. + qcom,sensors_sharedmem@00000000 {
  2261. + compatible = "qcom,sharedmem-uio";
  2262. + reg = <0x00000000 0x00010000>;
  2263. + reg-names = "rfsa_sensor";
  2264. + qcom,client-id = <0x011013ee>;
  2265. + linux,contiguous-region = <&adsp_mem>;
  2266. + };
  2267. +
  2268. + qcom,nvbackup_sharedmem@00000000 {
  2269. + compatible = "qcom,sharedmem-uio";
  2270. + reg = <0x06200000 0x001000000>;
  2271. + reg-names = "nvbackup";
  2272. + qcom,client-id = <0x00000001>;
  2273. + linux,contiguous-region = <&nvbackup_regions>;
  2274. + };
  2275. +
  2276. + sdhc_1: sdhci@f9824900 {
  2277. + compatible = "qcom,sdhci-msm";
  2278. + reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
  2279. + reg-names = "hc_mem", "core_mem";
  2280. +
  2281. + interrupts = <0 123 0>, <0 138 0>;
  2282. + interrupt-names = "hc_irq", "pwr_irq";
  2283. +
  2284. + qcom,bus-width = <8>;
  2285. + qcom,cpu-dma-latency-us = <301 70>;
  2286. + qcom,cpu-affinity = "affine_cores";
  2287. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  2288. + qcom,wakeup-on-idle;
  2289. +
  2290. + qcom,msm-bus,name = "sdhc1";
  2291. + qcom,msm-bus,num-cases = <9>;
  2292. + qcom,msm-bus,num-paths = <1>;
  2293. + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
  2294. + <78 512 1600 3200>, /* 400 KB/s*/
  2295. + <78 512 80000 160000>, /* 20 MB/s */
  2296. + <78 512 100000 200000>, /* 25 MB/s */
  2297. + <78 512 200000 400000>, /* 50 MB/s */
  2298. + <78 512 400000 800000>, /* 100 MB/s */
  2299. + <78 512 400000 800000>, /* 200 MB/s */
  2300. + <78 512 400000 800000>, /* 400 MB/s */
  2301. + <78 512 2048000 4096000>; /* Max. bandwidth */
  2302. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  2303. + 100000000 200000000 400000000 4294967295>;
  2304. +
  2305. + clock-names = "iface_clk", "core_clk";
  2306. + clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
  2307. + <&clock_gcc clk_gcc_sdcc1_apps_clk>;
  2308. +
  2309. + status = "disabled";
  2310. + };
  2311. +
  2312. + sdhc_2: sdhci@f98a4900 {
  2313. + compatible = "qcom,sdhci-msm";
  2314. + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  2315. + reg-names = "hc_mem", "core_mem";
  2316. +
  2317. + interrupts = <0 125 0>, <0 221 0>;
  2318. + interrupt-names = "hc_irq", "pwr_irq";
  2319. +
  2320. + clock-names = "iface_clk", "core_clk";
  2321. + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
  2322. + <&clock_gcc clk_gcc_sdcc2_apps_clk>;
  2323. +
  2324. + qcom,bus-width = <4>;
  2325. + qcom,cpu-dma-latency-us = <301 70>;
  2326. + qcom,cpu-affinity = "affine_cores";
  2327. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  2328. + qcom,wakeup-on-idle;
  2329. +
  2330. + qcom,msm-bus,name = "sdhc2";
  2331. + qcom,msm-bus,num-cases = <8>;
  2332. + qcom,msm-bus,num-paths = <1>;
  2333. + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
  2334. + <81 512 1600 3200>, /* 400 KB/s*/
  2335. + <81 512 80000 160000>, /* 20 MB/s */
  2336. + <81 512 100000 200000>, /* 25 MB/s */
  2337. + <81 512 200000 400000>, /* 50 MB/s */
  2338. + <81 512 400000 800000>, /* 100 MB/s */
  2339. + <81 512 800000 800000>, /* 200 MB/s */
  2340. + <81 512 2048000 4096000>; /* Max. bandwidth */
  2341. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  2342. + 100000000 200000000 4294967295>;
  2343. +
  2344. + status = "disabled";
  2345. + };
  2346. +
  2347. + sdhc_3: sdhci@f9864900 {
  2348. + compatible = "qcom,sdhci-msm";
  2349. + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
  2350. + reg-names = "hc_mem", "core_mem";
  2351. +
  2352. + interrupts = <0 127 0>, <0 224 0>;
  2353. + interrupt-names = "hc_irq", "pwr_irq";
  2354. +
  2355. + clock-names = "iface_clk", "core_clk";
  2356. + clocks = <&clock_gcc clk_gcc_sdcc3_ahb_clk>,
  2357. + <&clock_gcc clk_gcc_sdcc3_apps_clk>;
  2358. +
  2359. + qcom,bus-width = <4>;
  2360. + qcom,cpu-dma-latency-us = <301 70>;
  2361. + qcom,cpu-affinity = "affine_cores";
  2362. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  2363. + qcom,wakeup-on-idle;
  2364. +
  2365. + qcom,msm-bus,name = "sdhc3";
  2366. + qcom,msm-bus,num-cases = <8>;
  2367. + qcom,msm-bus,num-paths = <1>;
  2368. + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
  2369. + <79 512 1600 3200>, /* 400 KB/s*/
  2370. + <79 512 80000 160000>, /* 20 MB/s */
  2371. + <79 512 100000 200000>, /* 25 MB/s */
  2372. + <79 512 200000 400000>, /* 50 MB/s */
  2373. + <79 512 400000 800000>, /* 100 MB/s */
  2374. + <79 512 800000 800000>, /* 200 MB/s */
  2375. + <79 512 2048000 4096000>; /* Max. bandwidth */
  2376. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  2377. + 100000000 200000000 4294967295>;
  2378. + qcom,dat1-mpm-int = <47>;
  2379. + status = "disabled";
  2380. + };
  2381. +
  2382. + ufs_ice: ufsice@fc5a0000 {
  2383. + compatible = "qcom,ice";
  2384. + reg = <0xfc5a0000 0x8000>;
  2385. + interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";
  2386. + interrupts = <0 258 0>, <0 257 0>;
  2387. + status = "disabled";
  2388. + };
  2389. +
  2390. + ufsphy1: ufsphy@fc597000 {
  2391. + compatible = "qcom,ufs-phy-qmp-20nm";
  2392. + reg = <0xfc597000 0xda8>;
  2393. + reg-names = "phy_mem";
  2394. + #phy-cells = <0>;
  2395. + vdda-phy-supply = <&pm8994_l28>;
  2396. + vdda-pll-supply = <&pm8994_l12>;
  2397. + vdda-phy-max-microamp = <45000>;
  2398. + vdda-pll-max-microamp = <100>;
  2399. + vddp-ref-clk-supply = <&pm8994_l31>;
  2400. + vddp-ref-clk-max-microamp = <100>;
  2401. + vddp-ref-clk-always-on;
  2402. + clock-names = "ref_clk_src",
  2403. + "ref_clk",
  2404. + "tx_iface_clk",
  2405. + "rx_iface_clk";
  2406. + clocks = <&clock_rpm clk_ln_bb_clk>,
  2407. + <&clock_gcc clk_ufs_phy_ldo>,
  2408. + <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
  2409. + <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
  2410. + status = "disabled";
  2411. + };
  2412. +
  2413. + ufs1: ufshc@fc594000 {
  2414. + compatible = "qcom,ufshc";
  2415. + reg = <0xfc594000 0x2500>, <0xfd512074 0x4>;
  2416. + interrupts = <0 265 0>;
  2417. + phys = <&ufsphy1>;
  2418. + phy-names = "ufsphy";
  2419. + ufs-qcom-crypto = <&ufs_ice>;
  2420. + vdd-hba-supply = <&gdsc_ufs>;
  2421. + vdd-hba-fixed-regulator;
  2422. + vcc-supply = <&pm8994_l20>;
  2423. + vccq-supply = <&pm8994_l31>;
  2424. + vccq2-supply = <&pm8994_s4>;
  2425. + vcc-max-microamp = <750000>;
  2426. + vccq-max-microamp = <50000>;
  2427. + vccq2-max-microamp = <750000>;
  2428. +
  2429. + clock-names = "core_clk_src", "core_clk", "bus_clk", "iface_clk",
  2430. + "ref_clk", "rx_lane0_sync_clk", "tx_lane0_sync_clk",
  2431. + "rx_lane1_sync_clk", "tx_lane1_sync_clk";
  2432. + clocks =
  2433. + <&clock_gcc clk_ufs_axi_clk_src>,
  2434. + <&clock_gcc clk_gcc_ufs_axi_clk>,
  2435. + <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
  2436. + <&clock_gcc clk_gcc_ufs_ahb_clk>,
  2437. + <&clock_rpm clk_bb_clk1>,
  2438. + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>,
  2439. + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
  2440. + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>,
  2441. + <&clock_gcc clk_gcc_ufs_tx_symbol_1_clk>;
  2442. + qcom,msm-bus,name = "ufs1";
  2443. + qcom,msm-bus,num-cases = <22>;
  2444. + qcom,msm-bus,num-paths = <2>;
  2445. + qcom,msm-bus,vectors-KBps =
  2446. + <95 512 0 0>, <1 650 0 0>, /* No vote */
  2447. + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
  2448. + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
  2449. + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
  2450. + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
  2451. + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */
  2452. + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */
  2453. + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */
  2454. + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */
  2455. + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
  2456. + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
  2457. + <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */
  2458. + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */
  2459. + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */
  2460. + <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */
  2461. + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
  2462. + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
  2463. + <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */
  2464. + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */
  2465. + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */
  2466. + <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */
  2467. + <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
  2468. + qcom,bus-vector-names = "MIN",
  2469. + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
  2470. + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
  2471. + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
  2472. + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
  2473. + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
  2474. + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
  2475. + "MAX";
  2476. +
  2477. + qcom,cpu-affinity = "affine_cores";
  2478. + qcom,cpu-affinity-mask = <0xf>; /* little cluster */
  2479. + qcom,cpu-dma-latency-us = <301>;
  2480. +
  2481. + spm-level = <5>;
  2482. + status = "disabled";
  2483. + };
  2484. +
  2485. + spi_0: spi_epm: spi@f9923000 { /* BLSP1 QUP1 */
  2486. + compatible = "qcom,spi-qup-v2";
  2487. + #address-cells = <1>;
  2488. + #size-cells = <0>;
  2489. + reg-names = "spi_physical", "spi_bam_physical";
  2490. + reg = <0xf9923000 0x1000>,
  2491. + <0xf9904000 0x19000>;
  2492. + interrupt-names = "spi_irq", "spi_bam_irq";
  2493. + interrupts = <0 95 0>, <0 238 0>;
  2494. + spi-max-frequency = <19200000>;
  2495. +
  2496. + qcom,infinite-mode = <0>;
  2497. + qcom,use-bam;
  2498. + qcom,ver-reg-exists;
  2499. + qcom,bam-consumer-pipe-index = <12>;
  2500. + qcom,bam-producer-pipe-index = <13>;
  2501. + qcom,master-id = <86>;
  2502. + qcom,use-pinctrl;
  2503. + pinctrl-names = "spi_default", "spi_sleep";
  2504. + pinctrl-0 = <&spi_0_active &spi_0_cs1_active>;
  2505. + pinctrl-1 = <&spi_0_sleep &spi_0_cs1_sleep>;
  2506. +
  2507. + clock-names = "iface_clk", "core_clk";
  2508. +
  2509. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  2510. + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
  2511. + };
  2512. +//#ifdef VENDOR_EDIT
  2513. +/* add for fpc1021 fingerprints */
  2514. + spi_12: spi@f9968000 {
  2515. + compatible = "qcom,spi-qup-v2";
  2516. + //cell-index = <12>; //changhua
  2517. + #address-cells = <1>;
  2518. + #size-cells = <0>;
  2519. + reg-names = "spi_physical"/*, "spi_bam_physical"*/;
  2520. +
  2521. + /*Add BAM physical address
  2522. + BLSP1: 0xf9904000
  2523. + BLSP2: 0xf9944000
  2524. + */
  2525. +
  2526. + reg = <0xf9968000 0x1000>/*,
  2527. + <0xf9944000 0x19000>*/;
  2528. +
  2529. + interrupt-names = "spi12_irq"/*, "spi_bam_irq"*/;
  2530. +
  2531. + /* Add BAM IRQ
  2532. + BLSP1: 238
  2533. + BLSP2: 239 ??271??? 239 is offset
  2534. + */
  2535. + interrupts = <0 106 0>/*, <0 239 0>*/;
  2536. +
  2537. + spi-max-frequency = <4800000>;
  2538. +
  2539. + /* //changhua
  2540. + qcom,gpio-mosi = <&msm_gpio 85 0>;
  2541. + qcom,gpio-miso = <&msm_gpio 86 0>;
  2542. + qcom,gpio-clk = <&msm_gpio 88 0>;
  2543. + qcom,gpio-cs0 = <&msm_gpio 87 0>;
  2544. + */
  2545. +
  2546. + clock-names = "iface_clk", "core_clk";
  2547. + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
  2548. + <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>;
  2549. +
  2550. + qcom,master-id = <86>;
  2551. + /*qcom,infinite-mode = <0>;
  2552. + qcom,use-bam;
  2553. + qcom,ver-reg-exists;
  2554. + qcom,bam-consumer-pipe-index = <22>;
  2555. + qcom,bam-producer-pipe-index = <23>;
  2556. + */
  2557. + /*lichanghua add for use pinctrl*/
  2558. + /* Assign runtime functions to pins */
  2559. +
  2560. + qcom,use-pinctrl;
  2561. + pinctrl-names = "spi_default", "spi_sleep";
  2562. + pinctrl-0 = <&spi_12_active &spi_12_cs0_active>;
  2563. + pinctrl-1 = <&spi_12_sleep &spi_12_cs0_sleep>;
  2564. +
  2565. + qcom,shared;
  2566. +
  2567. + /*lichanghua add for use pinctrl end*/
  2568. + };
  2569. +//#endif/*VENDOR_EDIT*/
  2570. +
  2571. + qcom,msm-ssc-sensors {
  2572. + compatible = "qcom,msm-ssc-sensors";
  2573. + };
  2574. +
  2575. + qcom,msm-pacman {
  2576. + compatible = "qcom,msm-pacman";
  2577. + };
  2578. +
  2579. + wcd9xxx_intc: wcd9xxx-irq {
  2580. + compatible = "qcom,wcd9xxx-irq";
  2581. + interrupt-controller;
  2582. + #interrupt-cells = <1>;
  2583. + interrupt-parent = <&msm_gpio>;
  2584. + interrupts = <72 0>;
  2585. + interrupt-names = "cdc-int";
  2586. + pinctrl-names = "default";
  2587. + pinctrl-0 = <&wcd_intr_default>;
  2588. + };
  2589. +
  2590. + tspp: msm_tspp@f99d8000 {
  2591. + compatible = "qcom,msm_tspp";
  2592. + reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */
  2593. + <0xf99d9000 0x1000>, /* MSM_TSIF1_PHYS */
  2594. + <0xf99da000 0x1000>, /* MSM_TSPP_PHYS */
  2595. + <0xf99c4000 0x11000>; /* MSM_TSPP_BAM_PHYS */
  2596. + reg-names = "MSM_TSIF0_PHYS",
  2597. + "MSM_TSIF1_PHYS",
  2598. + "MSM_TSPP_PHYS",
  2599. + "MSM_TSPP_BAM_PHYS";
  2600. + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */
  2601. + <0 119 0>, /* TSIF0_IRQ */
  2602. + <0 120 0>, /* TSIF1_IRQ */
  2603. + <0 122 0>; /* TSIF_BAM_IRQ */
  2604. + interrupt-names = "TSIF_TSPP_IRQ",
  2605. + "TSIF0_IRQ",
  2606. + "TSIF1_IRQ",
  2607. + "TSIF_BAM_IRQ";
  2608. +
  2609. + clock-names = "iface_clk", "ref_clk";
  2610. + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>,
  2611. + <&clock_gcc clk_gcc_tsif_ref_clk>;
  2612. +
  2613. + qcom,msm-bus,name = "tsif";
  2614. + qcom,msm-bus,num-cases = <2>;
  2615. + qcom,msm-bus,num-paths = <1>;
  2616. + qcom,msm-bus,vectors-KBps =
  2617. + <82 512 0 0>, /* No vote */
  2618. + <82 512 12288 24576>; /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
  2619. +
  2620. + pinctrl-names = "disabled",
  2621. + "tsif0-mode1", "tsif0-mode2",
  2622. + "tsif1-mode1", "tsif1-mode2",
  2623. + "dual-tsif-mode1", "dual-tsif-mode2";
  2624. +
  2625. + pinctrl-0 = <>; /* disabled */
  2626. + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */
  2627. + pinctrl-2 = <&tsif0_signals_active
  2628. + &tsif0_sync_active>; /* tsif0-mode2 */
  2629. + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */
  2630. + pinctrl-4 = <&tsif1_signals_active
  2631. + &tsif1_sync_active>; /* tsif1-mode2 */
  2632. + pinctrl-5 = <&tsif0_signals_active
  2633. + &tsif1_signals_active>; /* dual-tsif-mode1 */
  2634. + pinctrl-6 = <&tsif0_signals_active
  2635. + &tsif0_sync_active
  2636. + &tsif1_signals_active
  2637. + &tsif1_sync_active>; /* dual-tsif-mode2 */
  2638. + };
  2639. +
  2640. + slim_msm: slim@fe12f000 {
  2641. + cell-index = <1>;
  2642. + compatible = "qcom,slim-ngd";
  2643. + reg = <0xfe12f000 0x2C000>,
  2644. + <0xfe104000 0x20000>;
  2645. + reg-names = "slimbus_physical", "slimbus_bam_physical";
  2646. + interrupts = <0 163 0>, <0 164 0>;
  2647. + interrupt-names = "slimbus_irq", "slimbus_bam_irq";
  2648. + qcom,apps-ch-pipes = <0x60000000>;
  2649. + qcom,ea-pc = <0x110>;
  2650. +
  2651. + tomtom_codec {
  2652. + compatible = "qcom,tomtom-slim-pgd";
  2653. + elemental-addr = [00 01 30 01 17 02];
  2654. +
  2655. + interrupt-parent = <&wcd9xxx_intc>;
  2656. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
  2657. + 17 18 19 20 21 22 23 24 25 26 27 28 29
  2658. + 30 31>;
  2659. +
  2660. + qcom,cdc-reset-gpio = <&msm_gpio 68 0>;
  2661. +
  2662. + cdc-vdd-buck-supply = <&pm8994_s5>;
  2663. + qcom,cdc-vdd-buck-voltage = <1800000 2150000>;
  2664. + qcom,cdc-vdd-buck-current = <650000>;
  2665. +
  2666. + cdc-vdd-tx-h-supply = <&pm8994_s4>;
  2667. + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
  2668. + qcom,cdc-vdd-tx-h-current = <45000>;
  2669. +
  2670. + cdc-vdd-rx-h-supply = <&pm8994_s4>;
  2671. + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
  2672. + qcom,cdc-vdd-rx-h-current = <45000>;
  2673. +
  2674. + cdc-vddpx-1-supply = <&pm8994_s4>;
  2675. + qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
  2676. + qcom,cdc-vddpx-1-current = <10000>;
  2677. +
  2678. + cdc-vdd-a-1p2v-supply = <&pm8994_l11>;
  2679. + qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
  2680. + qcom,cdc-vdd-a-1p2v-current = <2000>;
  2681. +
  2682. + cdc-vddcx-1-supply = <&pm8994_l11>;
  2683. + qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
  2684. + qcom,cdc-vddcx-1-current = <33000>;
  2685. +
  2686. + cdc-vddcx-2-supply = <&pm8994_l11>;
  2687. + qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
  2688. + qcom,cdc-vddcx-2-current = <33000>;
  2689. +
  2690. + qcom,cdc-static-supplies = "cdc-vdd-buck",
  2691. + "cdc-vdd-tx-h",
  2692. + "cdc-vdd-rx-h",
  2693. + "cdc-vddpx-1",
  2694. + "cdc-vdd-a-1p2v",
  2695. + "cdc-vddcx-1",
  2696. + "cdc-vddcx-2";
  2697. +
  2698. + qcom,cdc-micbias-ldoh-v = <0x3>;
  2699. + qcom,cdc-micbias-cfilt1-mv = <1800>;
  2700. + //#ifdef VENDOR_EDIT
  2701. + /*wangdongdong@MultiMedia.AudioDrv , 2015/3/24, modify micbias voltage*/
  2702. + /*kangjirui@MultiMedia.AudioDrv , 2015/4/18, modify micbias voltage for headset button error*/
  2703. + qcom,cdc-micbias-cfilt2-mv = <2700>;
  2704. + //#endif /* VENDOR_EDIT */
  2705. + qcom,cdc-micbias-cfilt3-mv = <1800>;
  2706. + qcom,cdc-micbias1-cfilt-sel = <0x0>;
  2707. + qcom,cdc-micbias2-cfilt-sel = <0x1>;
  2708. + qcom,cdc-micbias3-cfilt-sel = <0x2>;
  2709. + qcom,cdc-micbias4-cfilt-sel = <0x2>;
  2710. + qcom,cdc-mclk-clk-rate = <9600000>;
  2711. + qcom,cdc-slim-ifd = "tomtom-slim-ifd";
  2712. + qcom,cdc-slim-ifd-elemental-addr = [00 00 30 01 17 02];
  2713. + qcom,cdc-dmic-sample-rate = <4800000>;
  2714. + qcom,cdc-mad-dmic-rate = <600000>;
  2715. + qcom,cdc-variant = "WCD9330";
  2716. + qcom,cdc-spkdrv-ocp-curr-limit-mA = <2625>;
  2717. + };
  2718. + };
  2719. +
  2720. + spmi_bus: qcom,spmi@fc4c0000 {
  2721. + compatible = "qcom,spmi-pmic-arb";
  2722. + reg-names = "core", "intr", "cnfg";
  2723. + reg = <0xfc4cf000 0x1000>,
  2724. + <0xfc4cb000 0x1000>,
  2725. + <0xfc4ca000 0x1000>;
  2726. + /* 190,ee0_krait_hlos_spmi_periph_irq */
  2727. + /* 187,channel_0_krait_hlos_trans_done_irq */
  2728. + interrupts = <0 190 0>, <0 187 0>;
  2729. + qcom,pmic-arb-channel = <0>;
  2730. + qcom,pmic-arb-ee = <0>;
  2731. + #interrupt-cells = <3>;
  2732. + interrupt-controller;
  2733. + #address-cells = <1>;
  2734. + #size-cells = <0>;
  2735. + cell-index = <0>;
  2736. + };
  2737. +
  2738. + usb3: ssusb@f9200000 {
  2739. + compatible = "qcom,dwc-usb3-msm";
  2740. + status = "disabled";
  2741. + reg = <0xf9200000 0xfc000>,
  2742. + <0xfd4ab000 0x4>;
  2743. + #address-cells = <1>;
  2744. + #size-cells = <1>;
  2745. + ranges;
  2746. +
  2747. + interrupt-parent = <&usb3>;
  2748. + interrupts = <0 1>;
  2749. + #interrupt-cells = <1>;
  2750. + interrupt-map-mask = <0x0 0xffffffff>;
  2751. + interrupt-map = <0x0 0 &intc 0 133 0
  2752. + 0x0 1 &intc 0 180 0
  2753. + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>;
  2754. + interrupt-names = "hs_phy_irq", "pwr_event_irq", "pmic_id_irq";
  2755. +
  2756. + USB3_GDSC-supply = <&gdsc_usb30>;
  2757. + vdda33-supply = <&pm8994_l24>;
  2758. + vbus_dwc3-supply = <&smbcharger_charger_otg>;
  2759. + qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
  2760. + qcom,dwc-usb3-msm-qdss-tx-fifo-size = <8192>;
  2761. + qcom,usb-dbm = <&dbm_1p5>;
  2762. +
  2763. + qcom,msm-bus,name = "usb3";
  2764. + qcom,msm-bus,num-cases = <2>;
  2765. + qcom,msm-bus,num-paths = <1>;
  2766. + qcom,msm-bus,vectors-KBps =
  2767. + <61 512 0 0>,
  2768. + <61 512 240000 960000>;
  2769. +
  2770. + qcom,power-collapse-on-cable-disconnect;
  2771. + qcom,por-after-power-collapse;
  2772. +
  2773. + clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
  2774. + <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>,
  2775. + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
  2776. + <&clock_gcc clk_gcc_usb30_sleep_clk>,
  2777. + <&clock_rpm clk_ln_bb_clk>,
  2778. + <&clock_rpm clk_cxo_dwc3_clk>;
  2779. + clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
  2780. + "ref_clk", "xo";
  2781. +
  2782. + dwc3@f9200000 {
  2783. + compatible = "synopsys,dwc3";
  2784. + reg = <0xf9200000 0xfc000>;
  2785. + interrupt-parent = <&intc>;
  2786. + interrupts = <0 131 0>;
  2787. + tx-fifo-resize;
  2788. + snps,usb3-u1u2-disable;
  2789. + usb-phy = <&hsphy0>, <&ssphy0>;
  2790. + };
  2791. + };
  2792. +
  2793. + hsphy0: hsphy@f92f8800 {
  2794. + compatible = "qcom,usb-hsphy";
  2795. + status = "disabled";
  2796. + reg = <0xf92f8800 0x3ff>,
  2797. + <0xf9b3a000 0x110>;
  2798. + reg-names = "core", "phy_csr";
  2799. + // #ifdef VENDOR_EDIT
  2800. + /*modify by jiachenghui from 0x00D191A4 to 0x00D191A7 for OTG 2015-04-22*/
  2801. + /*change HS DC voltage-level to 0x0011 by jiachenghui for OTG detect issue 2015-05-23*/
  2802. + qcom,hsphy-init = <0x00D187A7>;
  2803. + //#endif /*VENDOR_EDIT*/
  2804. + vdd-supply = <&pm8994_s2_corner>;
  2805. + vddcx-supply = <&pm8994_s1_corner>;
  2806. + vdda18-supply = <&pm8994_l6>;
  2807. + vdda33-supply = <&pm8994_l24>;
  2808. + qcom,vdd-voltage-level = <1 5 7>;
  2809. + qcom,ext-vbus-id;
  2810. + qcom,vbus-valid-override;
  2811. + qcom,set-pllbtune;
  2812. + qcom,sleep-clk-reset;
  2813. + qcom,vdda-force-on;
  2814. + clocks = <&clock_gcc clk_gcc_usb2_hs_phy_sleep_clk>;
  2815. + clock-names = "phy_sleep_clk";
  2816. + };
  2817. +
  2818. + ssphy0: ssphy@f9b38000 {
  2819. + compatible = "qcom,usb-ssphy-qmp";
  2820. + status = "disabled";
  2821. + reg = <0xf9b38000 0x800>,
  2822. + <0xf9b3e000 0x3ff>;
  2823. + reg-names = "qmp_phy_base",
  2824. + "qmp_ahb2phy_base";
  2825. + vdd-supply = <&pm8994_l28>;
  2826. + vdda18-supply = <&pm8994_l6>;
  2827. + qcom,vdd-voltage-level = <0 1000000 1000000>;
  2828. + qcom,vbus-valid-override;
  2829. + qcom,no-pipe-clk-switch;
  2830. +
  2831. + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
  2832. + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
  2833. + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
  2834. + <&clock_gcc clk_gcc_usb3_phy_reset>,
  2835. + <&clock_gcc clk_gcc_usb3phy_phy_reset>,
  2836. + <&clock_gcc clk_usb_ss_phy_ldo>;
  2837. + clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
  2838. + "phy_phy_reset", "ldo_clk";
  2839. + };
  2840. +
  2841. + dbm_1p5: dbm@f92f8000 {
  2842. + compatible = "qcom,usb-dbm-1p5";
  2843. + reg = <0xf92f8000 0x1000>;
  2844. + qcom,reset-ep-after-lpm-resume;
  2845. + };
  2846. +
  2847. + qcom,usbbam@f9304000 {
  2848. + compatible = "qcom,usb-bam-msm";
  2849. + reg = <0xf9304000 0x9000>,
  2850. + <0xf92f880c 0x4>;
  2851. + reg-names = "ssusb", "qscratch_ram1_reg";
  2852. + interrupts = <0 132 0>;
  2853. + interrupt-names = "ssusb";
  2854. + clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
  2855. + <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>;
  2856. + clock-names = "mem_clk", "mem_iface_clk";
  2857. +
  2858. + qcom,usb-bam-fifo-baseaddr = <0xf9200000>;
  2859. + qcom,usb-bam-num-pipes = <16>;
  2860. + qcom,ignore-core-reset-ack;
  2861. + qcom,disable-clk-gating;
  2862. + qcom,usb-bam-override-threshold = <0x4001>;
  2863. + qcom,usb-bam-max-mbps-highspeed = <400>;
  2864. + qcom,usb-bam-max-mbps-superspeed = <3600>;
  2865. +
  2866. + qcom,pipe0 {
  2867. + label = "ssusb-ipa-out-0";
  2868. + qcom,usb-bam-mem-type = <2>;
  2869. + qcom,bam-type = <0>;
  2870. + qcom,dir = <0>;
  2871. + qcom,pipe-num = <0>;
  2872. + qcom,peer-bam = <2>;
  2873. + qcom,src-bam-physical-address = <0xf9304000>;
  2874. + qcom,src-bam-pipe-index = <1>;
  2875. + qcom,data-fifo-size = <0x8000>;
  2876. + qcom,descriptor-fifo-size = <0x2000>;
  2877. + qcom,reset-bam-on-connect;
  2878. + };
  2879. + qcom,pipe1 {
  2880. + label = "ssusb-ipa-in-0";
  2881. + qcom,usb-bam-mem-type = <2>;
  2882. + qcom,bam-type = <0>;
  2883. + qcom,dir = <1>;
  2884. + qcom,pipe-num = <0>;
  2885. + qcom,peer-bam = <2>;
  2886. + qcom,dst-bam-physical-address = <0xf9304000>;
  2887. + qcom,dst-bam-pipe-index = <0>;
  2888. + qcom,data-fifo-size = <0x8000>;
  2889. + qcom,descriptor-fifo-size = <0x2000>;
  2890. + qcom,reset-bam-on-connect;
  2891. + };
  2892. + qcom,pipe2 {
  2893. + label = "ssusb-qdss-in-0";
  2894. + qcom,usb-bam-mem-type = <1>;
  2895. + qcom,bam-type = <0>;
  2896. + qcom,dir = <1>;
  2897. + qcom,pipe-num = <0>;
  2898. + qcom,peer-bam = <1>;
  2899. + qcom,src-bam-physical-address = <0xfc37C000>;
  2900. + qcom,src-bam-pipe-index = <0>;
  2901. + qcom,dst-bam-physical-address = <0xf9304000>;
  2902. + qcom,dst-bam-pipe-index = <2>;
  2903. + qcom,data-fifo-offset = <0xf0000>;
  2904. + qcom,data-fifo-size = <0x1800>;
  2905. + qcom,descriptor-fifo-offset = <0xf4000>;
  2906. + qcom,descriptor-fifo-size = <0x1400>;
  2907. + qcom,reset-bam-on-connect;
  2908. + };
  2909. +
  2910. + /* USB BAM pipe (consumer) configuration for accelerated DPL */
  2911. + qcom,pipe3 {
  2912. + label = "ssusb-dpl-ipa-in-1";
  2913. + qcom,usb-bam-mem-type = <2>;
  2914. + qcom,bam-type = <0>;
  2915. + qcom,dir = <1>;
  2916. + qcom,pipe-num = <1>;
  2917. + qcom,peer-bam = <2>;
  2918. + qcom,dst-bam-physical-address = <0xf9304000>;
  2919. + qcom,dst-bam-pipe-index = <2>;
  2920. + qcom,data-fifo-size = <0x8000>;
  2921. + qcom,descriptor-fifo-size = <0x2000>;
  2922. + qcom,reset-bam-on-connect;
  2923. + };
  2924. + };
  2925. +
  2926. + usb_otg: usb@f9a55000 {
  2927. + compatible = "qcom,hsusb-otg";
  2928. + status = "disabled";
  2929. +
  2930. + reg = <0xf9a55000 0x400>;
  2931. + reg-names = "core";
  2932. + interrupts = <0 134 0 0 140 0>;
  2933. + interrupt-names = "core_irq", "async_irq";
  2934. +
  2935. + HSUSB_VDDCX-supply = <&pm8994_s2_corner>;
  2936. + HSUSB_1p8-supply = <&pm8994_l6>;
  2937. + HSUSB_3p3-supply = <&pm8994_l24>;
  2938. + qcom,vdd-voltage-level = <1 5 7>;
  2939. +
  2940. + clocks = <&clock_gcc clk_gcc_usb_hs_system_clk>,
  2941. + <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
  2942. + <&clock_gcc clk_gcc_usb2_hs_phy_sleep_clk>,
  2943. + <&clock_rpm clk_cxo_otg_clk>;
  2944. + clock-names = "core_clk", "iface_clk", "sleep_clk", "xo";
  2945. +
  2946. + qcom,hsusb-otg-phy-type = <2>;
  2947. + qcom,hsusb-otg-phy-init-seq = <0x63 0x81 0xffffffff>;
  2948. + qcom,hsusb-otg-mode = <1>;
  2949. + qcom,hsusb-otg-otg-control = <1>;
  2950. + };
  2951. +
  2952. + usb_ehci: ehci@f9a55000 {
  2953. + compatible = "qcom,ehci-host";
  2954. + status = "disabled";
  2955. + reg = <0xf9a55000 0x400>;
  2956. + interrupts = <0 134 0>, <0 140 0>;
  2957. + interrupt-names = "core_irq", "async_irq";
  2958. + hsusb_vdd_dig-supply = <&pm8994_s2_corner>;
  2959. + HSUSB_1p8-supply = <&pm8994_l6>;
  2960. + HSUSB_3p3-supply = <&pm8994_l24>;
  2961. + qcom,vdd-voltage-level = <1 2 3 5 7>;
  2962. + qcom,usb2-power-budget = <500>;
  2963. + usb-phy = <&qusb_phy>;
  2964. + qcom,pm-qos-latency = <30001>;
  2965. +
  2966. + qcom,msm-bus,name = "usb-hs";
  2967. + qcom,msm-bus,num-cases = <2>;
  2968. + qcom,msm-bus,num-paths = <1>;
  2969. + qcom,msm-bus,vectors-KBps =
  2970. + <87 512 0 0>,
  2971. + <87 512 40000 60000>;
  2972. +
  2973. + clocks = <&clock_gcc clk_gcc_usb_hs_system_clk>,
  2974. + <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
  2975. + <&clock_rpm clk_cxo_otg_clk>;
  2976. + clock-names = "core_clk", "iface_clk", "xo";
  2977. + };
  2978. +
  2979. + qusb_phy: qusb@f9b39000 {
  2980. + compatible = "qcom,qusb2phy";
  2981. + status = "disabled";
  2982. + reg = <0xf9b39000 0x17f>;
  2983. + reg-names = "qusb_phy_base";
  2984. + vdd-supply = <&pm8994_s2_corner>;
  2985. + vdda18-supply = <&pm8994_l6>;
  2986. + vdda33-supply = <&pm8994_l24>;
  2987. + qcom,vdd-voltage-level = <1 5 7>;
  2988. + qcom,qusb-tune = <0xa08391d5>;
  2989. + phy_type = "ulpi";
  2990. + clocks = <&clock_rpm clk_ln_bb_clk>,
  2991. + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
  2992. + <&clock_gcc clk_gcc_qusb2_phy_reset>;
  2993. + clock-names = "ref_clk", "cfg_ahb_clk", "phy_reset";
  2994. + };
  2995. +
  2996. + android_usb@fe87f0c8 {
  2997. + compatible = "qcom,android-usb";
  2998. + reg = <0xfe87f0c8 0xc8>;
  2999. + qcom,pm-qos-latency = <61 637 1261>;
  3000. + /*add by jiachenghui for cdrom,20150528*/
  3001. + /*#ifdef VENDOR_EDIT*/
  3002. + qcom,android-usb-cdrom;
  3003. + /*#ifdef VENDOR_EDIT*/
  3004. + /*end add by jiachenghui for cdrom,20150528*/
  3005. + };
  3006. +
  3007. + qcom,venus@fdce0000 {
  3008. + compatible = "qcom,pil-tz-generic";
  3009. + reg = <0xfdce0000 0x4000>;
  3010. +
  3011. + vdd-supply = <&gdsc_venus>;
  3012. + qcom,proxy-reg-names = "vdd";
  3013. + clock-names = "core_clk", "iface_clk",
  3014. + "bus_clk", "mem_clk", "scm_ce1_clk";
  3015. + qcom,proxy-clock-names = "core_clk", "iface_clk",
  3016. + "bus_clk", "mem_clk", "scm_ce1_clk";
  3017. + qcom,scm_ce1_clk-freq = <85710000>;
  3018. +
  3019. + clocks = <&clock_mmss clk_venus0_vcodec0_clk>,
  3020. + <&clock_mmss clk_venus0_ahb_clk>,
  3021. + <&clock_mmss clk_venus0_axi_clk>,
  3022. + <&clock_mmss clk_venus0_ocmemnoc_clk>,
  3023. + <&clock_rpm clk_scm_ce1_clk>;
  3024. +
  3025. + qcom,msm-bus,name = "pil-venus";
  3026. + qcom,msm-bus,num-cases = <2>;
  3027. + qcom,msm-bus,num-paths = <1>;
  3028. + qcom,msm-bus,vectors-KBps =
  3029. + <63 512 0 0>,
  3030. + <63 512 0 304000>;
  3031. + qcom,pas-id = <9>;
  3032. + qcom,proxy-timeout-ms = <100>;
  3033. + qcom,firmware-name = "venus";
  3034. + linux,contiguous-region = <&peripheral_mem>;
  3035. + };
  3036. +
  3037. + qcom,mss@fc880000 {
  3038. + compatible = "qcom,pil-q6v55-mss";
  3039. + reg = <0xfc880000 0x100>,
  3040. + <0xfd485000 0x400>,
  3041. + <0xfc820000 0x020>,
  3042. + <0xfc401680 0x004>;
  3043. + reg-names = "qdsp6_base", "halt_base", "rmb_base",
  3044. + "restart_reg";
  3045. +
  3046. + clocks = <&clock_rpm clk_cxo_clk_src>,
  3047. + <&clock_rpm clk_mss_cfg_ahb_clk>,
  3048. + <&clock_rpm clk_pnoc_modem_clk>,
  3049. + <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
  3050. + <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
  3051. + <&clock_gcc clk_gpll0_out_msscc>;
  3052. + clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
  3053. + "mem_clk", "gpll0_mss_clk";
  3054. + qcom,proxy-clock-names = "xo", "pnoc_clk";
  3055. + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
  3056. + "gpll0_mss_clk";
  3057. +
  3058. + interrupts = <0 24 1>;
  3059. + vdd_mss-supply = <&pm8994_s7>;
  3060. + vdd_cx-supply = <&pm8994_s1_corner>;
  3061. + vdd_mx-supply = <&pm8994_s2_corner>;
  3062. + vdd_mx-uV = <7>;
  3063. + vdd_pll-supply = <&pm8994_l12>;
  3064. + qcom,vdd_pll = <1800000>;
  3065. + qcom,firmware-name = "modem";
  3066. + qcom,pil-self-auth;
  3067. + qcom,mba-image-is-not-elf;
  3068. + qcom,sysmon-id = <0>;
  3069. + qcom,ssctl-instance-id = <0x12>;
  3070. + qcom,override-acc;
  3071. + qcom,ahb-clk-vote;
  3072. + qcom,pnoc-clk-vote;
  3073. +
  3074. + /* GPIO inputs from mss */
  3075. + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
  3076. + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
  3077. + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
  3078. + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
  3079. +
  3080. + /* GPIO output to mss */
  3081. + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
  3082. +
  3083. + linux,contiguous-region = <&modem_mem>;
  3084. + };
  3085. +
  3086. + qcom,lpass@fe200000 {
  3087. + compatible = "qcom,pil-tz-generic";
  3088. + reg = <0xfe200000 0x00100>;
  3089. + interrupts = <0 162 1>;
  3090. +
  3091. + vdd_cx-supply = <&pm8994_s1_corner>;
  3092. + qcom,proxy-reg-names = "vdd_cx";
  3093. + qcom,vdd_cx-uV-uA = <7 100000>;
  3094. +
  3095. + clocks = <&clock_rpm clk_cxo_pil_lpass_clk>,
  3096. + <&clock_rpm clk_scm_ce1_clk>;
  3097. + clock-names = "xo", "scm_ce1_clk";
  3098. + qcom,proxy-clock-names = "xo", "scm_ce1_clk";
  3099. + qcom,scm_ce1_clk-freq = <85710000>;
  3100. +
  3101. + qcom,pas-id = <1>;
  3102. + qcom,proxy-timeout-ms = <10000>;
  3103. + qcom,smem-id = <423>;
  3104. + qcom,sysmon-id = <1>;
  3105. + qcom,ssctl-instance-id = <0x14>;
  3106. + qcom,firmware-name = "adsp";
  3107. +
  3108. + /* GPIO inputs from lpass */
  3109. + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
  3110. + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
  3111. + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
  3112. + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
  3113. +
  3114. + /* GPIO output to lpass */
  3115. + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
  3116. +
  3117. + linux,contiguous-region = <&peripheral_mem>;
  3118. + };
  3119. +
  3120. +/* #ifdef VENDOR_EDIT // add by xcb for ramoops 2015-03-31 */
  3121. + ramoops {
  3122. + compatible = "ramoops";
  3123. + /*reg = <0x05800000 0x00100000>;*/
  3124. + linux,contiguous-region = <&ramoops_mem>;
  3125. + };
  3126. +/* #endif VENDOR_EDIT */
  3127. +
  3128. +
  3129. + clock_rpm: qcom,rpmcc@fc401880 {
  3130. + compatible = "qcom,rpmcc-8994";
  3131. + reg = <0xfc401880 0x4>;
  3132. + reg-names = "cc_base";
  3133. + #clock-cells = <1>;
  3134. + };
  3135. +
  3136. + clock_gcc: qcom,gcc@fc400000 {
  3137. + compatible = "qcom,gcc-8994";
  3138. + reg = <0xfc400000 0x2000>;
  3139. + reg-names = "cc_base";
  3140. + vdd_dig-supply = <&pm8994_s1_corner>;
  3141. + clock-names = "xo", "xo_a_clk";
  3142. + clocks = <&clock_rpm clk_cxo_clk_src>,
  3143. + <&clock_rpm clk_cxo_clk_src_ao>;
  3144. + #clock-cells = <1>;
  3145. + };
  3146. +
  3147. + clock_mmss: qcom,mmsscc@fd8c0000 {
  3148. + compatible = "qcom,mmsscc-8994";
  3149. + reg = <0xfd8c0000 0x5200>;
  3150. + reg-names = "cc_base";
  3151. + vdd_dig-supply = <&pm8994_s1_corner>;
  3152. + mmpll4_dig-supply = <&pm8994_s1_corner>;
  3153. + mmpll4_analog-supply = <&pm8994_l12>;
  3154. + clock-names = "xo", "gpll0", "mmssnoc_ahb",
  3155. + "oxili_gfx3d_clk", "pclk0_src", "pclk1_src",
  3156. + "byte0_src", "byte1_src", "extpclk_src";
  3157. + clocks = <&clock_rpm clk_cxo_clk_src>,
  3158. + <&clock_gcc clk_gpll0_out_mmsscc>,
  3159. + <&clock_rpm clk_mmssnoc_ahb_clk>,
  3160. + <&clock_rpm clk_oxili_gfx3d_clk_src>,
  3161. + <&mdss_dsi0_pll clk_mdss_pixel_clk_mux>,
  3162. + <&mdss_dsi0_pll clk_mdss_pixel_clk_mux>,
  3163. + <&mdss_dsi0_pll clk_mdss_byte_clk_mux>,
  3164. + <&mdss_dsi0_pll clk_mdss_byte_clk_mux>,
  3165. + <&mdss_hdmi_pll clk_hdmi_20nm_vco_clk>;
  3166. + #clock-cells = <1>;
  3167. + };
  3168. +
  3169. + clock_debug: qcom,cc-debug@fc401880 {
  3170. + compatible = "qcom,cc-debug-8994";
  3171. + reg = <0xfc401880 0x4>;
  3172. + reg-names = "cc_base";
  3173. + clock-names = "debug_mmss_clk", "debug_rpm_clk",
  3174. + "debug_cpu_clk";
  3175. + clocks = <&clock_mmss clk_mmss_debug_mux>,
  3176. + <&clock_rpm clk_rpm_debug_mux>,
  3177. + <&clock_cpu clk_cpu_debug_mux>;
  3178. + #clock-cells = <1>;
  3179. + };
  3180. +
  3181. + cci_cache: qcom,cci {
  3182. + compatible = "devfreq-simple-dev";
  3183. + clock-names = "devfreq_clk";
  3184. + clocks = <&clock_cpu clk_cci_clk>;
  3185. + governor = "cpufreq";
  3186. + freq-tbl-khz =
  3187. + < 150000 >,
  3188. + < 200000 >,
  3189. + < 249600 >,
  3190. + < 300000 >,
  3191. + < 384000 >,
  3192. + < 499200 >,
  3193. + < 600000 >;
  3194. + };
  3195. +
  3196. + cpubw: qcom,cpubw {
  3197. + compatible = "qcom,devbw";
  3198. + governor = "cpufreq";
  3199. + qcom,src-dst-ports = <1 512>;
  3200. + qcom,active-only;
  3201. + qcom,bw-tbl =
  3202. + < 1525 /* 200 MHz */ >,
  3203. + < 2288 /* 300 MHz */ >,
  3204. + < 3509 /* 460 MHz */ >,
  3205. + < 4066 /* 533 MHz */ >,
  3206. + < 5126 /* 672 MHz */ >,
  3207. + < 5928 /* 777 MHz */ >,
  3208. + < 7904 /* 1036 MHz */ >,
  3209. + < 9887 /* 1296 MHz */ >,
  3210. + < 11863 /* 1555 MHz */ >;
  3211. + };
  3212. +
  3213. + qcom,cpu-bwmon {
  3214. + compatible = "qcom,bimc-bwmon";
  3215. + reg = <0xfc388000 0x300>, <0xfc381000 0x200>;
  3216. + reg-names = "base", "global_base";
  3217. + interrupts = <0 183 4>;
  3218. + qcom,mport = <0>;
  3219. + qcom,target-dev = <&cpubw>;
  3220. + };
  3221. +
  3222. + mincpubw: qcom,mincpubw {
  3223. + compatible = "qcom,devbw";
  3224. + governor = "powersave";
  3225. + qcom,src-dst-ports = <1 512>;
  3226. + qcom,active-only;
  3227. + qcom,bw-tbl =
  3228. + < 1525 /* 200 MHz */ >,
  3229. + < 2288 /* 300 MHz */ >,
  3230. + < 3509 /* 460 MHz */ >,
  3231. + < 4066 /* 533 MHz */ >,
  3232. + < 5126 /* 672 MHz */ >,
  3233. + < 5928 /* 777 MHz */ >,
  3234. + < 7904 /* 1036 MHz */ >,
  3235. + < 9887 /* 1296 MHz */ >,
  3236. + < 11863 /* 1555 MHz */ >;
  3237. + };
  3238. +
  3239. + devfreq_cpufreq: devfreq-cpufreq {
  3240. + cpubw-cpufreq {
  3241. + target-dev = <&cpubw>;
  3242. + cpu-to-dev-map-0 =
  3243. + < 199200 1525 >,
  3244. + < 302400 1525 >,
  3245. + < 384000 1525 >,
  3246. + < 600000 1525 >,
  3247. + < 691200 2288 >,
  3248. + < 768000 3562 >,
  3249. + < 844800 4066 >,
  3250. + < 921600 5126 >,
  3251. + < 940800 6072 >;
  3252. + cpu-to-dev-map-4 =
  3253. + < 199200 1525 >,
  3254. + < 302400 1525 >,
  3255. + < 384000 1525 >,
  3256. + < 600000 2288 >,
  3257. + < 691200 3562 >,
  3258. + < 768000 4066 >,
  3259. + < 844800 5126 >,
  3260. + < 921600 6072 >;
  3261. + };
  3262. +
  3263. + mincpubw-cpufreq {
  3264. + target-dev = <&mincpubw>;
  3265. + cpu-to-dev-map-0 =
  3266. + < 199200 1525 >,
  3267. + < 302400 1525 >,
  3268. + < 384000 2288 >,
  3269. + < 600000 3509 >,
  3270. + < 691200 4066 >,
  3271. + < 768000 5126 >,
  3272. + < 844800 5928 >,
  3273. + < 921600 5928 >,
  3274. + < 940800 5928 >;
  3275. + cpu-to-dev-map-4 =
  3276. + < 199200 1525 >,
  3277. + < 302400 1525 >,
  3278. + < 384000 2288 >,
  3279. + < 600000 3509 >,
  3280. + < 691200 4066 >,
  3281. + < 768000 5126 >,
  3282. + < 844800 5928 >,
  3283. + < 921600 5928 >;
  3284. + };
  3285. +
  3286. + cci-cpufreq {
  3287. + target-dev = <&cci_cache>;
  3288. + cpu-to-dev-map-0 =
  3289. + < 199200 150000 >,
  3290. + < 302400 200000 >,
  3291. + < 384000 249600 >,
  3292. + < 600000 300000 >,
  3293. + < 691200 384000 >,
  3294. + < 768000 384000 >,
  3295. + < 844800 499200 >,
  3296. + < 921600 600000 >,
  3297. + < 940800 600000 >;
  3298. + cpu-to-dev-map-4 =
  3299. + < 199200 150000 >,
  3300. + < 302400 200000 >,
  3301. + < 384000 249600 >,
  3302. + < 600000 300000 >,
  3303. + < 691200 384000 >,
  3304. + < 768000 499200 >,
  3305. + < 844800 600000 >,
  3306. + < 921600 600000 >;
  3307. + };
  3308. + };
  3309. +
  3310. + msm_cpufreq: qcom,msm-cpufreq {
  3311. + compatible = "qcom,msm-cpufreq";
  3312. + clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
  3313. + "cpu3_clk", "cpu4_clk", "cpu5_clk",
  3314. + "cpu6_clk", "cpu7_clk";
  3315. + clocks = <&clock_cpu clk_cci_clk>,
  3316. + <&clock_cpu clk_a53_clk>,
  3317. + <&clock_cpu clk_a53_clk>,
  3318. + <&clock_cpu clk_a53_clk>,
  3319. + <&clock_cpu clk_a53_clk>,
  3320. + <&clock_cpu clk_a57_clk>,
  3321. + <&clock_cpu clk_a57_clk>,
  3322. + <&clock_cpu clk_a57_clk>,
  3323. + <&clock_cpu clk_a57_clk>;
  3324. +
  3325. + qcom,governor-per-policy;
  3326. +
  3327. + qcom,cpufreq-table-0 =
  3328. + < 199200 >,
  3329. + < 302400 >,
  3330. + < 384000 >,
  3331. + < 600000 >,
  3332. + < 691200 >,
  3333. + < 768000 >,
  3334. + < 844800 >,
  3335. + < 921600 >,
  3336. + < 940800 >;
  3337. +
  3338. + qcom,cpufreq-table-4 =
  3339. + < 199200 >,
  3340. + < 302400 >,
  3341. + < 384000 >,
  3342. + < 600000 >,
  3343. + < 691200 >,
  3344. + < 768000 >,
  3345. + < 844800 >,
  3346. + < 921600 >;
  3347. + };
  3348. +
  3349. + clock_cpu: qcom,cpu-clock-8994@f9015000 {
  3350. + compatible = "qcom,cpu-clock-8994";
  3351. + reg = <0xf9015000 0x1000>,
  3352. + <0xf9016000 0x1000>,
  3353. + <0xf9011000 0x1000>,
  3354. + <0xf900d000 0x1000>,
  3355. + <0xf900f000 0x1000>,
  3356. + <0xf9112000 0x1000>,
  3357. + <0xfc4b80b0 0x8>;
  3358. + reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux", "efuse";
  3359. + vdd-a53-supply = <&apc0_vreg_corner>;
  3360. + vdd-a57-supply = <&apc1_vreg_corner>;
  3361. + vdd-cci-supply = <&apc0_vreg_corner>;
  3362. + vdd-dig-supply = <&pm8994_s1_corner_ao>;
  3363. + qcom,a53-speedbin0-v0 =
  3364. + < 0 0>,
  3365. + < 199200000 1>,
  3366. + < 302400000 2>,
  3367. + < 384000000 3>,
  3368. + < 600000000 4>,
  3369. + < 691200000 5>,
  3370. + < 768000000 6>,
  3371. + < 844800000 7>,
  3372. + < 921600000 8>,
  3373. + < 940800000 9>;
  3374. + qcom,a57-speedbin0-v0 =
  3375. + < 0 0>,
  3376. + < 199200000 1>,
  3377. + < 302400000 2>,
  3378. + < 384000000 3>,
  3379. + < 600000000 4>,
  3380. + < 691200000 5>,
  3381. + < 768000000 6>,
  3382. + < 844800000 7>,
  3383. + < 921600000 8>;
  3384. + qcom,cci-speedbin0-v0 =
  3385. + < 0 0>,
  3386. + < 150000000 1>,
  3387. + < 200000000 2>,
  3388. + < 249600000 3>,
  3389. + < 300000000 4>,
  3390. + < 384000000 4>,
  3391. + < 499200000 7>,
  3392. + < 600000000 9>;
  3393. + clock-names = "xo_ao", "aux_clk";
  3394. + clocks = <&clock_rpm clk_cxo_clk_src_ao>,
  3395. + <&clock_gcc clk_gpll0_ao>;
  3396. + #clock-cells = <1>;
  3397. + };
  3398. +
  3399. + ocmem: qcom,ocmem@fdd00000 {
  3400. + compatible = "qcom,msm-ocmem";
  3401. + reg = <0xfdd00000 0x2000>,
  3402. + <0xfdd02000 0x2000>,
  3403. + <0xfe039000 0x400>,
  3404. + <0xfec00000 0x200000>;
  3405. + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  3406. + interrupts = <0 76 0 0 77 0>;
  3407. + interrupt-names = "ocmem_irq", "dm_irq";
  3408. + qcom,ocmem-num-regions = <0x4>;
  3409. + qcom,ocmem-num-macros = <0x20>;
  3410. + qcom,resource-type = <0x706d636f>;
  3411. + #address-cells = <1>;
  3412. + #size-cells = <1>;
  3413. + ranges = <0x0 0xfec00000 0x200000>;
  3414. + clocks = <&clock_rpm clk_ocmemgx_core_clk>,
  3415. + <&clock_mmss clk_ocmemcx_ocmemnoc_clk>;
  3416. + clock-names = "core_clk", "iface_clk";
  3417. +
  3418. + partition@0 {
  3419. + reg = <0x0 0x180000>;
  3420. + qcom,ocmem-part-name = "graphics";
  3421. + qcom,ocmem-part-min = <0x80000>;
  3422. + };
  3423. +
  3424. + partition@100000 {
  3425. + reg = <0x180000 0x80000>;
  3426. + qcom,ocmem-part-name = "video";
  3427. + qcom,ocmem-part-min = <0x55000>;
  3428. + };
  3429. +
  3430. + };
  3431. +
  3432. + msm_vidc: qcom,vidc@fdc00000 {
  3433. + compatible = "qcom,msm-vidc";
  3434. + reg = <0xfdc00000 0xff000>;
  3435. + interrupts = <0 44 0>;
  3436. + qcom,hfi = "venus";
  3437. + qcom,reg-presets = <0x800D8 0x707>,
  3438. + <0xe0020 0x55555556>,
  3439. + <0xe0024 0x55555556>,
  3440. + <0x80124 0x3>;
  3441. + qcom,qdss-presets = <0xfc325000 0x1000>,
  3442. + <0xfc326000 0x1000>,
  3443. + <0xfc321000 0x1000>,
  3444. + <0xfc322000 0x1000>,
  3445. + <0xfc323000 0x1000>,
  3446. + <0xfc302000 0x1000>,
  3447. + <0xfa180000 0x1000>,
  3448. + <0xfa181000 0x1000>;
  3449. + qcom,ocmem-size = <524288>; /* 512 * 1024*/
  3450. + qcom,max-hw-load = <1281600>; /* Full 4k @ 30 + 1080p @ 30 */
  3451. + clock-names = "core_clk", "core0_clk", "core1_clk", "core2_clk",
  3452. + "iface_clk", "bus_clk", "mem_clk";
  3453. + venus-supply = <&gdsc_venus>;
  3454. + venus-core0-supply = <&gdsc_venus_core0>;
  3455. + venus-core1-supply = <&gdsc_venus_core1>;
  3456. + venus-core2-supply = <&gdsc_venus_core2>;
  3457. + qcom,clock-configs = <0x3 0x0 0x0 0x0 0x0 0x0 0x0>;
  3458. + qcom,sw-power-collapse;
  3459. + clocks = <&clock_mmss clk_venus0_vcodec0_clk>,
  3460. + <&clock_mmss clk_venus0_core0_vcodec_clk>,
  3461. + <&clock_mmss clk_venus0_core1_vcodec_clk>,
  3462. + <&clock_mmss clk_venus0_core2_vcodec_clk>,
  3463. + <&clock_mmss clk_venus0_ahb_clk>,
  3464. + <&clock_mmss clk_venus0_axi_clk>,
  3465. + <&clock_mmss clk_venus0_ocmemnoc_clk>;
  3466. + qcom,load-freq-tbl =
  3467. + <979200 465000000 0x0c000000>,
  3468. + <979200 465000000 0x01000414>,
  3469. + <979200 465000000 0x030fcfff>,
  3470. + <979200 465000000 0x04000000>,
  3471. + <783360 465000000 0x0c000000>,
  3472. + <783360 465000000 0x01000414>,
  3473. + <783360 465000000 0x030fcfff>,
  3474. + <783360 465000000 0x04000000>,
  3475. + <489600 240000000 0x0c000000>,
  3476. + <489600 240000000 0x01000414>,
  3477. + <489600 240000000 0x030fcfff>,
  3478. + <489600 240000000 0x04000000>,
  3479. + <244800 133330000 0x0c000000>,
  3480. + <244800 133330000 0x01000414>,
  3481. + <244800 133330000 0x030fcfff>,
  3482. + <244800 133330000 0x04000000>;
  3483. + qcom,vidc-iommu-domains {
  3484. + qcom,domain-ns {
  3485. + qcom,vidc-domain-phandle = <&venus_domain_ns>;
  3486. + qcom,vidc-partition-buffer-types = <0x7ff>,
  3487. + <0x800>;
  3488. + };
  3489. + qcom,domain-sec-bs {
  3490. + qcom,vidc-domain-phandle = <&venus_domain_sec_bitstream>;
  3491. + qcom,vidc-partition-buffer-types = <0x241>;
  3492. + };
  3493. + qcom,domain-sec-px {
  3494. + qcom,vidc-domain-phandle = <&venus_domain_sec_pixel>;
  3495. + qcom,vidc-partition-buffer-types = <0x106>;
  3496. + };
  3497. + qcom,domain-sec-np {
  3498. + qcom,vidc-domain-phandle = <&venus_domain_sec_non_pixel>;
  3499. + qcom,vidc-partition-buffer-types = <0x480>;
  3500. + };
  3501. + };
  3502. + qcom,msm-bus-clients {
  3503. + qcom,msm-bus-client@0 {
  3504. + qcom,msm-bus,name = "venc-core1-ddr";
  3505. + qcom,msm-bus,num-cases = <11>;
  3506. + qcom,msm-bus,num-paths = <1>;
  3507. + qcom,msm-bus,vectors-KBps =
  3508. + <63 512 0 0>,
  3509. + <63 512 66800 0>,
  3510. + <63 512 201100 0>,
  3511. + <63 512 201100 0>,
  3512. + <63 512 458300 0>,
  3513. + <63 512 458300 0>,
  3514. + <63 512 889200 0>,
  3515. + <63 512 889200 0>,
  3516. + <63 512 2108700 0>,
  3517. + <63 512 2243700 0>,
  3518. + <63 512 2615000 0>;
  3519. + qcom,bus-configs = <0x1000414>;
  3520. + };
  3521. +
  3522. + qcom,msm-bus-client@1 {
  3523. + qcom,msm-bus,name = "vdec-core0-ddr";
  3524. + qcom,msm-bus,num-cases = <11>;
  3525. + qcom,msm-bus,num-paths = <1>;
  3526. + qcom,msm-bus,vectors-KBps =
  3527. + <63 512 0 0>,
  3528. + <63 512 151600 0>,
  3529. + <63 512 393600 0>,
  3530. + <63 512 393600 0>,
  3531. + <63 512 749100 0>,
  3532. + <63 512 749100 0>,
  3533. + <63 512 1460700 0>,
  3534. + <63 512 1460700 0>,
  3535. + <63 512 2390500 0>,
  3536. + <63 512 2542300 0>,
  3537. + <63 512 2959800 0>;
  3538. + qcom,bus-configs = <0xc000000>;
  3539. + };
  3540. +
  3541. + qcom,msm-bus-client@2 {
  3542. + qcom,msm-bus,name = "vdec-core1-ddr";
  3543. + qcom,msm-bus,num-cases = <11>;
  3544. + qcom,msm-bus,num-paths = <1>;
  3545. + qcom,msm-bus,vectors-KBps =
  3546. + <63 512 0 0>,
  3547. + <63 512 113900 0>,
  3548. + <63 512 296700 0>,
  3549. + <63 512 296700 0>,
  3550. + <63 512 571400 0>,
  3551. + <63 512 571400 0>,
  3552. + <63 512 1088500 0>,
  3553. + <63 512 1088500 0>,
  3554. + <63 512 1811000 0>,
  3555. + <63 512 1962000 0>,
  3556. + <63 512 2242900 0>;
  3557. + qcom,bus-configs = <0x30fcfff>;
  3558. + };
  3559. +
  3560. + qcom,msm-bus-client@3 {
  3561. + qcom,msm-bus,name = "venc-core2-ddr";
  3562. + qcom,msm-bus,num-cases = <11>;
  3563. + qcom,msm-bus,num-paths = <1>;
  3564. + qcom,msm-bus,vectors-KBps =
  3565. + <63 512 0 0>,
  3566. + <63 512 89000 0>,
  3567. + <63 512 270000 0>,
  3568. + <63 512 270000 0>,
  3569. + <63 512 759000 0>,
  3570. + <63 512 759000 0>,
  3571. + <63 512 1050000 0>,
  3572. + <63 512 1050000 0>,
  3573. + <63 512 3077000 0>,
  3574. + <63 512 3811000 0>,
  3575. + <63 512 3812000 0>;
  3576. + qcom,bus-configs = <0x04000000>;
  3577. + };
  3578. + qcom,msm-bus-client@4 {
  3579. + qcom,msm-bus,name = "venc-core1-ocmem";
  3580. + qcom,msm-bus,num-cases = <11>;
  3581. + qcom,msm-bus,num-paths = <1>;
  3582. + qcom,msm-bus,vectors-KBps =
  3583. + <68 604 0 0>,
  3584. + <68 604 69000 2384000>,
  3585. + <68 604 207000 2384000>,
  3586. + <68 604 207000 2384000>,
  3587. + <68 604 470000 2384000>,
  3588. + <68 604 470000 2384000>,
  3589. + <68 604 940000 3632000>,
  3590. + <68 604 940000 3632000>,
  3591. + <68 604 1787000 3632000>,
  3592. + <68 604 1906000 3632000>,
  3593. + <68 604 2234000 3632000>;
  3594. + qcom,bus-configs = <0x10000414>;
  3595. + };
  3596. + qcom,msm-bus-client@5 {
  3597. + qcom,msm-bus,name = "venc-core2-ocmem";
  3598. + qcom,msm-bus,num-cases = <11>;
  3599. + qcom,msm-bus,num-paths = <1>;
  3600. + qcom,msm-bus,vectors-KBps =
  3601. + <68 604 0 0>,
  3602. + <68 604 71000 2384000>,
  3603. + <68 604 214000 2384000>,
  3604. + <68 604 214000 2384000>,
  3605. + <68 604 564000 2384000>,
  3606. + <68 604 564000 2384000>,
  3607. + <68 604 1003000 3632000>,
  3608. + <68 604 1003000 3632000>,
  3609. + <68 604 2040000 3632000>,
  3610. + <68 604 2349000 3632000>,
  3611. + <68 604 2551000 3632000>;
  3612. + qcom,bus-configs = <0x04000000>;
  3613. + };
  3614. +
  3615. + qcom,msm-bus-client@6 {
  3616. + qcom,msm-bus,name = "vdec-core0-ocmem";
  3617. + qcom,msm-bus,num-cases = <11>;
  3618. + qcom,msm-bus,num-paths = <1>;
  3619. + qcom,msm-bus,vectors-KBps =
  3620. + <68 604 0 0>,
  3621. + <68 604 79000 2384000>,
  3622. + <68 604 201000 2384000>,
  3623. + <68 604 201000 2384000>,
  3624. + <68 604 367000 2384000>,
  3625. + <68 604 367000 2384000>,
  3626. + <68 604 735000 3632000>,
  3627. + <68 604 735000 3632000>,
  3628. + <68 604 1175000 3632000>,
  3629. + <68 604 1254000 3632000>,
  3630. + <68 604 1469000 3632000>;
  3631. + qcom,bus-configs = <0xc000000>;
  3632. + };
  3633. +
  3634. + qcom,msm-bus-client@7 {
  3635. + qcom,msm-bus,name = "vdec-core1-ocmem";
  3636. + qcom,msm-bus,num-cases = <11>;
  3637. + qcom,msm-bus,num-paths = <1>;
  3638. + qcom,msm-bus,vectors-KBps =
  3639. + <68 604 0 0>,
  3640. + <68 604 88000 2384000>,
  3641. + <68 604 228000 2384000>,
  3642. + <68 604 228000 2384000>,
  3643. + <68 604 432000 2384000>,
  3644. + <68 604 432000 2384000>,
  3645. + <68 604 865000 3632000>,
  3646. + <68 604 865000 3632000>,
  3647. + <68 604 1374000 3632000>,
  3648. + <68 604 1465000 3632000>,
  3649. + <68 604 1717000 3632000>;
  3650. + qcom,bus-configs = <0x30fcfff>;
  3651. + };
  3652. +
  3653. + qcom,msm-bus-client@8 {
  3654. + qcom,msm-bus,name = "venc-ddr-lp";
  3655. + qcom,msm-bus,num-cases = <11>;
  3656. + qcom,msm-bus,num-paths = <1>;
  3657. + qcom,msm-bus,vectors-KBps =
  3658. + <63 512 0 0>,
  3659. + <63 512 66800 0>,
  3660. + <63 512 201100 0>,
  3661. + <63 512 201100 0>,
  3662. + <63 512 458300 0>,
  3663. + <63 512 458300 0>,
  3664. + <63 512 889200 0>,
  3665. + <63 512 889200 0>,
  3666. + <63 512 1218000 0>,
  3667. + <63 512 1218000 0>,
  3668. + <63 512 1218000 0>;
  3669. + qcom,bus-low-power;
  3670. + qcom,bus-configs = <0x0000004>;
  3671. + };
  3672. +
  3673. + qcom,msm-bus-client@9 {
  3674. + qcom,msm-bus,name = "venus-arm9-ddr";
  3675. + qcom,msm-bus,num-cases = <2>;
  3676. + qcom,msm-bus,num-paths = <1>;
  3677. + qcom,msm-bus,vectors-KBps =
  3678. + <63 512 0 0>,
  3679. + <63 512 1000 1000>;
  3680. + qcom,bus-configs = <0x00000000>;
  3681. + qcom,bus-passive;
  3682. + };
  3683. + };
  3684. + };
  3685. +
  3686. + i2c_1: i2c@f9923000 {
  3687. + compatible = "qcom,i2c-msm-v2";
  3688. + #address-cells = <1>;
  3689. + #size-cells = <0>;
  3690. + reg-names = "qup_phys_addr";
  3691. + reg = <0xf9923000 0x1000>;
  3692. + interrupt-names = "qup_irq";
  3693. + interrupts = <0 95 0>;
  3694. + qcom,clk-freq-out = <400000>;
  3695. + qcom,clk-freq-in = <19200000>;
  3696. + clock-names = "iface_clk", "core_clk";
  3697. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  3698. + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
  3699. +
  3700. + pinctrl-names = "i2c_active", "i2c_sleep";
  3701. + pinctrl-0 = <&i2c_1_active>;
  3702. + pinctrl-1 = <&i2c_1_sleep>;
  3703. + qcom,noise-rjct-scl = <0>;
  3704. + qcom,noise-rjct-sda = <0>;
  3705. + qcom,master-id = <86>;
  3706. + dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
  3707. + <&dma_blsp1 11 32 0x20000020 0x20>;
  3708. + dma-names = "tx", "rx";
  3709. + status = "disabled";
  3710. + };
  3711. +
  3712. + dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */
  3713. + #dma-cells = <4>;
  3714. + compatible = "qcom,sps-dma";
  3715. + reg = <0xf9904000 0x19000>;
  3716. + interrupts = <0 238 0>;
  3717. + qcom,summing-threshold = <10>;
  3718. + };
  3719. +
  3720. + dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */
  3721. + #dma-cells = <4>;
  3722. + compatible = "qcom,sps-dma";
  3723. + reg = <0xf9944000 0x19000>;
  3724. + interrupts = <0 239 0>;
  3725. + qcom,summing-threshold = <10>;
  3726. + };
  3727. +
  3728. +
  3729. + i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */
  3730. + compatible = "qcom,i2c-msm-v2";
  3731. + #address-cells = <1>;
  3732. + #size-cells = <0>;
  3733. + reg-names = "qup_phys_addr";
  3734. + reg = <0xf9924000 0x1000>;
  3735. + interrupt-names = "qup_irq";
  3736. + interrupts = <0 96 0>;
  3737. + qcom,clk-freq-out = <400000>;
  3738. + qcom,clk-freq-in = <19200000>;
  3739. + clock-names = "iface_clk", "core_clk";
  3740. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  3741. + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
  3742. +
  3743. + pinctrl-names = "i2c_active", "i2c_sleep";
  3744. + pinctrl-0 = <&i2c_2_active>;
  3745. + pinctrl-1 = <&i2c_2_sleep>;
  3746. + qcom,noise-rjct-scl = <0>;
  3747. + qcom,noise-rjct-sda = <0>;
  3748. +
  3749. + /* #ifdef VENDOR_EDIT */
  3750. + //add by yangrujin@bsp for dma has some issue causing i2c fail
  3751. + //qcom,disable-dma;
  3752. + /* #endif //VENDOR_EDIT */
  3753. +
  3754. +
  3755. + dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
  3756. + <&dma_blsp1 15 32 0x20000020 0x20>;
  3757. + dma-names = "tx", "rx";
  3758. + qcom,master-id = <86>;
  3759. + };
  3760. +
  3761. + i2c_5: i2c_11: i2c@f9967000 { /* BLSP2 QUP5 */
  3762. + compatible = "qcom,i2c-msm-v2";
  3763. + #address-cells = <1>;
  3764. + #size-cells = <0>;
  3765. + reg-names = "qup_phys_addr";
  3766. + reg = <0xf9967000 0x1000>;
  3767. + interrupt-names = "qup_irq";
  3768. + interrupts = <0 105 0>;
  3769. + qcom,clk-freq-out = <100000>;
  3770. + qcom,clk-freq-in = <19200000>;
  3771. + clock-names = "iface_clk", "core_clk";
  3772. + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
  3773. + <&clock_gcc clk_gcc_blsp2_qup5_i2c_apps_clk>;
  3774. +
  3775. + pinctrl-names = "i2c_active", "i2c_sleep";
  3776. + pinctrl-0 = <&i2c_5_active>;
  3777. + pinctrl-1 = <&i2c_5_sleep>;
  3778. + qcom,noise-rjct-scl = <0>;
  3779. + qcom,noise-rjct-sda = <0>;
  3780. + //#ifndef VENDOR_EDIT
  3781. + /*zhiguang.su@MultiMedia.AudioDrv , 2015/4/13, dma mode will cause I2C fail*/
  3782. + qcom,disable-dma;
  3783. + //#endif
  3784. + dmas = <&dma_blsp2 20 64 0x20000020 0x20>,
  3785. + <&dma_blsp2 21 32 0x20000020 0x20>;
  3786. + dma-names = "tx", "rx";
  3787. + qcom,master-id = <84>;
  3788. + };
  3789. +
  3790. + i2c_6: i2c@f9928000 { /* BLSP1 QUP6 */
  3791. + compatible = "qcom,i2c-msm-v2";
  3792. + #address-cells = <1>;
  3793. + #size-cells = <0>;
  3794. + status = "disabled";
  3795. + reg-names = "qup_phys_addr";
  3796. + reg = <0xf9928000 0x1000>;
  3797. + interrupt-names = "qup_irq";
  3798. + interrupts = <0 100 0>;
  3799. + qcom,clk-freq-out = <400000>;
  3800. + qcom,clk-freq-in = <19200000>;
  3801. + clock-names = "iface_clk", "core_clk";
  3802. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  3803. + <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;
  3804. +
  3805. + pinctrl-names = "i2c_active", "i2c_sleep";
  3806. + pinctrl-0 = <&i2c_6_active>;
  3807. + pinctrl-1 = <&i2c_6_sleep>;
  3808. + qcom,noise-rjct-scl = <0>;
  3809. + qcom,noise-rjct-sda = <0>;
  3810. + dmas = <&dma_blsp1 22 64 0x20000020 0x20>,
  3811. + <&dma_blsp1 23 32 0x20000020 0x20>;
  3812. + dma-names = "tx", "rx";
  3813. + qcom,master-id = <86>;
  3814. + };
  3815. +
  3816. + sound {
  3817. + compatible = "qcom,msm8994-asoc-snd";
  3818. + qcom,model = "msm8994-tomtom-snd-card";
  3819. + reg = <0xfe034000 0x4>,
  3820. + <0xfe035000 0x4>,
  3821. + <0xfe036000 0x4>,
  3822. + <0xfe037000 0x4>;
  3823. + reg-names = "lpaif_pri_mode_muxsel",
  3824. + "lpaif_sec_mode_muxsel",
  3825. + "lpaif_tert_mode_muxsel",
  3826. + "lpaif_quat_mode_muxsel";
  3827. +
  3828. + qcom,audio-routing =
  3829. + "AIF4 VI", "MCLK",
  3830. + "RX_BIAS", "MCLK",
  3831. + "LDO_H", "MCLK",
  3832. + "MADINPUT", "MCLK";
  3833. + //#ifndef VENDOR_EDIT
  3834. + /*zhiguang.su@MultiMedia.AudioDrv , 2015/3/19, delete unsed mic*/
  3835. + //"AMIC1", "MIC BIAS1 Internal1",
  3836. + //"MIC BIAS1 Internal1", "Handset Mic",
  3837. + //"AMIC2", "MIC BIAS2 External",
  3838. + //"MIC BIAS2 External", "Headset Mic",
  3839. + //"AMIC3", "MIC BIAS2 External",
  3840. + //"MIC BIAS2 External", "ANCRight Headset Mic",
  3841. + //"AMIC4", "MIC BIAS2 External",
  3842. + //"MIC BIAS2 External", "ANCLeft Headset Mic",
  3843. + //"DMIC1", "MIC BIAS1 External",
  3844. + //"MIC BIAS1 External", "Digital Mic1",
  3845. + //"DMIC2", "MIC BIAS1 External",
  3846. + //"MIC BIAS1 External", "Digital Mic2",
  3847. + //"DMIC3", "MIC BIAS3 External",
  3848. + //"MIC BIAS3 External", "Digital Mic3",
  3849. + //"DMIC4", "MIC BIAS3 External",
  3850. + //"MIC BIAS3 External", "Digital Mic4",
  3851. + //"DMIC5", "MIC BIAS4 External",
  3852. + //"MIC BIAS4 External", "Digital Mic5",
  3853. + //"DMIC6", "MIC BIAS4 External",
  3854. + //"MIC BIAS4 External", "Digital Mic6";
  3855. + //#endif
  3856. +
  3857. + clock-names = "osr_clk";
  3858. + clocks = <&clock_rpm clk_div_clk1>;
  3859. + qcom,cdc-mclk-gpios = <&pm8994_gpios 15 0>;
  3860. + qcom,tomtom-mclk-clk-freq = <9600000>;
  3861. + pinctrl-names = "sleep",
  3862. + "auxpcm-active",
  3863. + "mi2s-active",
  3864. + //#ifdef VENDOR_EDIT
  3865. + /*zhiguang.su@MultiMedia.AudioDrv,changed for quat i2s */
  3866. + "active",
  3867. + "quat_mi2s_active",
  3868. + "quat_aux_active";
  3869. + //#endif
  3870. +//#ifdef VENDOR_EDIT
  3871. +//pinctrl-0 = <&pri_mi2s_sleep>, <&pri_mi2s_sd0_sleep>,
  3872. +// <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  3873. +//pinctrl-1 = <&pri_mi2s_sleep>, <&pri_mi2s_sd0_sleep>,
  3874. +// <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  3875. +//pinctrl-2 = <&pri_mi2s_active>, <&pri_mi2s_sd0_active>,
  3876. +// <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  3877. +//pinctrl-3 = <&pri_mi2s_active>, <&pri_mi2s_sd0_active>,
  3878. +// <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  3879. +//#endif
  3880. +
  3881. +//#ifdef VENDOR_EDIT
  3882. +/*zhiguang.su@MultiMedia.AudioDrv,2015-4-8,remove unused pri-i2s for conflict pins with BSP module.*/
  3883. + pinctrl-0 = <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  3884. + pinctrl-1 = <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  3885. + pinctrl-2 = <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  3886. + pinctrl-3 = <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  3887. +//#endif
  3888. +//#ifdef VENDOR_EDIT
  3889. +/*zhiguang.su@MultiMedia.AudioDrv changed for quat i2s */
  3890. + pinctrl-4 = <&quat_mi2s_active>, <&quat_mi2s_mclk_active>, <&quat_mi2s_sd0_active> , <&quat_mi2s_sd1_active>;
  3891. + pinctrl-5 = <&quat_mi2s_active>, <&quat_mi2s_mclk_active>, <&quat_mi2s_sd0_active> , <&quat_mi2s_sd1_active> , <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  3892. +//#endif
  3893. + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
  3894. + <&loopback>, <&compress>, <&hostless>,
  3895. + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>;
  3896. + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2",
  3897. + "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback",
  3898. + "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe",
  3899. + "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm",
  3900. + "msm-compr-dsp";
  3901. +//#ifdef VENDOR_EDIT
  3902. +/*zhiguang.su@MultiMedia.AudioDrv changed for quat i2s*/
  3903. + asoc-cpu = <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_hdmi>, <&dai_mi2s>,<&qua_mi2s>,
  3904. + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
  3905. + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
  3906. + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, <&bt_sco_rx>,
  3907. + <&bt_sco_tx>, <&int_fm_rx>, <&int_fm_tx>, <&afe_pcm_rx>,
  3908. + <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>,
  3909. + <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>,
  3910. + <&incall_music2_rx>;
  3911. + asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
  3912. + "msm-dai-q6-hdmi.8", "msm-dai-q6-mi2s.0","msm-dai-q6-mi2s.3",
  3913. + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385",
  3914. + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387",
  3915. + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389",
  3916. + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391",
  3917. + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393",
  3918. + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.12288",
  3919. + "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292",
  3920. + "msm-dai-q6-dev.12293", "msm-dai-q6-dev.224",
  3921. + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
  3922. + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
  3923. + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
  3924. + "msm-dai-q6-dev.32770";
  3925. +//#endif
  3926. + asoc-codec = <&stub_codec>;
  3927. + asoc-codec-names = "msm-stub-codec.1";
  3928. + };
  3929. +
  3930. + qcom,msm-adsp-loader {
  3931. + compatible = "qcom,adsp-loader";
  3932. + qcom,adsp-state = <0>;
  3933. + };
  3934. +
  3935. + qcom,msm-audio-ion {
  3936. + compatible = "qcom,msm-audio-ion";
  3937. + };
  3938. +
  3939. + pcm0: qcom,msm-pcm {
  3940. + compatible = "qcom,msm-pcm-dsp";
  3941. + qcom,msm-pcm-dsp-id = <0>;
  3942. + };
  3943. +
  3944. + qcom,msm-pcm-lpa {
  3945. + compatible = "qcom,msm-pcm-lpa";
  3946. + };
  3947. +
  3948. + pcm2: qcom,msm-ultra-low-latency {
  3949. + compatible = "qcom,msm-pcm-dsp";
  3950. + qcom,msm-pcm-dsp-id = <2>;
  3951. + qcom,msm-pcm-low-latency;
  3952. + qcom,latency-level = "ultra";
  3953. + };
  3954. +
  3955. + pcm1: qcom,msm-pcm-low-latency {
  3956. + compatible = "qcom,msm-pcm-dsp";
  3957. + qcom,msm-pcm-dsp-id = <1>;
  3958. + qcom,msm-pcm-low-latency;
  3959. + qcom,latency-level = "regular";
  3960. + };
  3961. +
  3962. + routing: qcom,msm-pcm-routing {
  3963. + compatible = "qcom,msm-pcm-routing";
  3964. + };
  3965. +
  3966. + compr: qcom,msm-compr-dsp {
  3967. + compatible = "qcom,msm-compr-dsp";
  3968. + };
  3969. +
  3970. + compress: qcom,msm-compress-dsp {
  3971. + compatible = "qcom,msm-compress-dsp";
  3972. + };
  3973. +
  3974. + voip: qcom,msm-voip-dsp {
  3975. + compatible = "qcom,msm-voip-dsp";
  3976. + };
  3977. +
  3978. + voice: qcom,msm-pcm-voice {
  3979. + compatible = "qcom,msm-pcm-voice";
  3980. + qcom,destroy-cvd;
  3981. + };
  3982. +
  3983. + stub_codec: qcom,msm-stub-codec {
  3984. + compatible = "qcom,msm-stub-codec";
  3985. + };
  3986. +
  3987. + qcom,msm-dai-fe {
  3988. + compatible = "qcom,msm-dai-fe";
  3989. + };
  3990. +
  3991. + afe: qcom,msm-pcm-afe {
  3992. + compatible = "qcom,msm-pcm-afe";
  3993. + };
  3994. +
  3995. + dai_hdmi: qcom,msm-dai-q6-hdmi {
  3996. + compatible = "qcom,msm-dai-q6-hdmi";
  3997. + qcom,msm-dai-q6-dev-id = <8>;
  3998. + };
  3999. +
  4000. + lsm: qcom,msm-lsm-client {
  4001. + compatible = "qcom,msm-lsm-client";
  4002. + };
  4003. +
  4004. + loopback: qcom,msm-pcm-loopback {
  4005. + compatible = "qcom,msm-pcm-loopback";
  4006. + };
  4007. +
  4008. + qcom,msm-voice-svc {
  4009. + compatible = "qcom,msm-voice-svc";
  4010. + };
  4011. +
  4012. + cpe: qcom,msm-cpe-lsm {
  4013. + compatible = "qcom,msm-cpe-lsm";
  4014. + };
  4015. +
  4016. + qcom,msm-dai-q6 {
  4017. + compatible = "qcom,msm-dai-q6";
  4018. + sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
  4019. + compatible = "qcom,msm-dai-q6-dev";
  4020. + qcom,msm-dai-q6-dev-id = <16384>;
  4021. + };
  4022. +
  4023. + sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
  4024. + compatible = "qcom,msm-dai-q6-dev";
  4025. + qcom,msm-dai-q6-dev-id = <16385>;
  4026. + };
  4027. +
  4028. + sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
  4029. + compatible = "qcom,msm-dai-q6-dev";
  4030. + qcom,msm-dai-q6-dev-id = <16386>;
  4031. + };
  4032. +
  4033. + sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
  4034. + compatible = "qcom,msm-dai-q6-dev";
  4035. + qcom,msm-dai-q6-dev-id = <16387>;
  4036. + };
  4037. +
  4038. + sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
  4039. + compatible = "qcom,msm-dai-q6-dev";
  4040. + qcom,msm-dai-q6-dev-id = <16388>;
  4041. + };
  4042. +
  4043. + sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
  4044. + compatible = "qcom,msm-dai-q6-dev";
  4045. + qcom,msm-dai-q6-dev-id = <16389>;
  4046. + };
  4047. +
  4048. + sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
  4049. + compatible = "qcom,msm-dai-q6-dev";
  4050. + qcom,msm-dai-q6-dev-id = <16390>;
  4051. + };
  4052. +
  4053. + sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
  4054. + compatible = "qcom,msm-dai-q6-dev";
  4055. + qcom,msm-dai-q6-dev-id = <16391>;
  4056. + };
  4057. +
  4058. + sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
  4059. + compatible = "qcom,msm-dai-q6-dev";
  4060. + qcom,msm-dai-q6-dev-id = <16392>;
  4061. + };
  4062. +
  4063. + sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
  4064. + compatible = "qcom,msm-dai-q6-dev";
  4065. + qcom,msm-dai-q6-dev-id = <16393>;
  4066. + };
  4067. +
  4068. + sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
  4069. + compatible = "qcom,msm-dai-q6-dev";
  4070. + qcom,msm-dai-q6-dev-id = <16395>;
  4071. + };
  4072. +
  4073. + bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
  4074. + compatible = "qcom,msm-dai-q6-dev";
  4075. + qcom,msm-dai-q6-dev-id = <12288>;
  4076. + };
  4077. +
  4078. + bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
  4079. + compatible = "qcom,msm-dai-q6-dev";
  4080. + qcom,msm-dai-q6-dev-id = <12289>;
  4081. + };
  4082. +
  4083. + int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
  4084. + compatible = "qcom,msm-dai-q6-dev";
  4085. + qcom,msm-dai-q6-dev-id = <12292>;
  4086. + };
  4087. +
  4088. + int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
  4089. + compatible = "qcom,msm-dai-q6-dev";
  4090. + qcom,msm-dai-q6-dev-id = <12293>;
  4091. + };
  4092. +
  4093. + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
  4094. + compatible = "qcom,msm-dai-q6-dev";
  4095. + qcom,msm-dai-q6-dev-id = <224>;
  4096. + };
  4097. +
  4098. + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
  4099. + compatible = "qcom,msm-dai-q6-dev";
  4100. + qcom,msm-dai-q6-dev-id = <225>;
  4101. + };
  4102. +
  4103. + afe_proxy_rx: com,msm-dai-q6-afe-proxy-rx {
  4104. + compatible = "qcom,msm-dai-q6-dev";
  4105. + qcom,msm-dai-q6-dev-id = <241>;
  4106. + };
  4107. +
  4108. + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
  4109. + compatible = "qcom,msm-dai-q6-dev";
  4110. + qcom,msm-dai-q6-dev-id = <240>;
  4111. + };
  4112. +
  4113. + incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
  4114. + compatible = "qcom,msm-dai-q6-dev";
  4115. + qcom,msm-dai-q6-dev-id = <32771>;
  4116. + };
  4117. +
  4118. + incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
  4119. + compatible = "qcom,msm-dai-q6-dev";
  4120. + qcom,msm-dai-q6-dev-id = <32772>;
  4121. + };
  4122. +
  4123. + incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
  4124. + compatible = "qcom,msm-dai-q6-dev";
  4125. + qcom,msm-dai-q6-dev-id = <32773>;
  4126. + };
  4127. +
  4128. + incall_music2_rx: qcom,msm-dai-q6-incall-music-2-rx {
  4129. + compatible = "qcom,msm-dai-q6-dev";
  4130. + qcom,msm-dai-q6-dev-id = <32770>;
  4131. + };
  4132. + };
  4133. +
  4134. + dai_pri_auxpcm: qcom,msm-pri-auxpcm {
  4135. + compatible = "qcom,msm-auxpcm-dev";
  4136. + qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  4137. + qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  4138. + qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  4139. + qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  4140. + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
  4141. + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
  4142. + qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  4143. + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  4144. + qcom,msm-auxpcm-interface = "primary";
  4145. + };
  4146. +
  4147. + dai_sec_auxpcm: qcom,msm-sec-auxpcm {
  4148. + compatible = "qcom,msm-auxpcm-dev";
  4149. + qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  4150. + qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  4151. + qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  4152. + qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  4153. + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
  4154. + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
  4155. + qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  4156. + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  4157. + qcom,msm-auxpcm-interface = "secondary";
  4158. + };
  4159. +
  4160. + qcom,msm-dai-mi2s {
  4161. + compatible = "qcom,msm-dai-mi2s";
  4162. + dai_mi2s: qcom,msm-dai-q6-mi2s-prim {
  4163. + compatible = "qcom,msm-dai-q6-mi2s";
  4164. + qcom,msm-dai-q6-mi2s-dev-id = <0>;
  4165. +//#ifdef VENDOR_EDIT
  4166. +/*zhiguang.su@MultiMedia.AudioDrv ,changed for quat i2s*/
  4167. +
  4168. + qcom,msm-mi2s-rx-lines = <1>;
  4169. + qcom,msm-mi2s-tx-lines = <2>;
  4170. + };
  4171. +
  4172. + qua_mi2s: qcom,msm-dai-q6-mi2s-quat {
  4173. + compatible = "qcom,msm-dai-q6-mi2s";
  4174. + qcom,msm-dai-q6-mi2s-dev-id = <3>;
  4175. + qcom,msm-mi2s-rx-lines = <1>;
  4176. + qcom,msm-mi2s-tx-lines = <2>;
  4177. + };
  4178. +//#endif
  4179. + };
  4180. +
  4181. + hostless: qcom,msm-pcm-hostless {
  4182. + compatible = "qcom,msm-pcm-hostless";
  4183. + };
  4184. +
  4185. + tsens: tsens@fc4a8000 {
  4186. + compatible = "qcom,msm8994-tsens";
  4187. + reg = <0xfc4a8000 0x2000>,
  4188. + <0xfc4bc000 0x1000>;
  4189. + reg-names = "tsens_physical", "tsens_eeprom_physical";
  4190. + interrupts = <0 184 0>;
  4191. + interrupt-names = "tsens-upper-lower";
  4192. + qcom,sensors = <16>;
  4193. + qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200>;
  4194. + };
  4195. +
  4196. + qcom_tzlog: tz-log@fe87f720 {
  4197. + compatible = "qcom,tz-log";
  4198. + reg = <0xfe87f720 0x2000>;
  4199. + };
  4200. +
  4201. + qcom_crypto1fde: qcrypto1fde@fd440000 {
  4202. + compatible = "qcom,qcrypto";
  4203. + reg = <0xfd440000 0x20000>,
  4204. + <0xfd444000 0x9000>;
  4205. + reg-names = "crypto-base","crypto-bam-base";
  4206. + interrupts = <0 236 0>;
  4207. + qcom,bam-pipe-pair = <2>;
  4208. + qcom,ce-hw-instance = <1>;
  4209. + qcom,ce-device = <0>;
  4210. + qcom,clk-mgmt-sus-res;
  4211. + qcom,msm-bus,name = "qcrypto-noc";
  4212. + qcom,msm-bus,num-cases = <2>;
  4213. + qcom,msm-bus,num-paths = <1>;
  4214. + qcom,msm-bus,vectors-KBps =
  4215. + <55 512 0 0>,
  4216. + <55 512 393600 393600>;
  4217. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  4218. + clocks = <&clock_rpm clk_qcrypto_ce2_clk>,
  4219. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  4220. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  4221. + qcom,support-core-clk-only;
  4222. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  4223. + qcom,use-sw-aes-xts-algo;
  4224. + qcom,use-sw-aes-ccm-algo;
  4225. + qcom,use-sw-ahash-algo;
  4226. + qcom,ce-opp-freq = <171430000>;
  4227. + };
  4228. +
  4229. + qcom_crypto2fde: qcrypto2fde@0xfd3c0000 {
  4230. + compatible = "qcom,qcrypto";
  4231. + reg = <0xfd3c0000 0x20000>,
  4232. + <0xfd3c4000 0x9000>;
  4233. + reg-names = "crypto-base","crypto-bam-base";
  4234. + interrupts = <0 297 0>;
  4235. + qcom,bam-pipe-pair = <2>;
  4236. + qcom,ce-hw-instance = <2>;
  4237. + qcom,ce-device = <0>;
  4238. + qcom,clk-mgmt-sus-res;
  4239. + qcom,msm-bus,name = "qcrypto-noc";
  4240. + qcom,msm-bus,num-cases = <2>;
  4241. + qcom,msm-bus,num-paths = <1>;
  4242. + qcom,msm-bus,vectors-KBps =
  4243. + <55 512 0 0>,
  4244. + <55 512 393600 393600>;
  4245. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  4246. + clocks = <&clock_rpm clk_qcrypto_ce3_clk>,
  4247. + <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
  4248. + <&clock_rpm clk_gcc_ce3_axi_m_clk>;
  4249. + qcom,support-core-clk-only;
  4250. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  4251. + qcom,use-sw-aes-xts-algo;
  4252. + qcom,use-sw-aes-ccm-algo;
  4253. + qcom,use-sw-ahash-algo;
  4254. + qcom,ce-opp-freq = <171430000>;
  4255. + };
  4256. +
  4257. + qcom_crypto1pfe: qcrypto1pfe@fd440000 {
  4258. + compatible = "qcom,qcrypto";
  4259. + reg = <0xfd440000 0x20000>,
  4260. + <0xfd444000 0x9000>;
  4261. + reg-names = "crypto-base","crypto-bam-base";
  4262. + interrupts = <0 236 0>;
  4263. + qcom,bam-pipe-pair = <0>;
  4264. + qcom,ce-hw-instance = <1>;
  4265. + qcom,ce-device = <1>;
  4266. + qcom,clk-mgmt-sus-res;
  4267. + qcom,msm-bus,name = "qcrypto-noc";
  4268. + qcom,msm-bus,num-cases = <2>;
  4269. + qcom,msm-bus,num-paths = <1>;
  4270. + qcom,msm-bus,vectors-KBps =
  4271. + <55 512 0 0>,
  4272. + <55 512 393600 393600>;
  4273. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  4274. + clocks = <&clock_rpm clk_qcrypto_ce2_clk>,
  4275. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  4276. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  4277. + qcom,support-core-clk-only;
  4278. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  4279. + qcom,use-sw-aes-xts-algo;
  4280. + qcom,use-sw-aes-ccm-algo;
  4281. + qcom,use-sw-ahash-algo;
  4282. + qcom,ce-opp-freq = <171430000>;
  4283. + };
  4284. +
  4285. + qcom_crypto2pfe: qcrypto2pfe@0xfd3c0000 {
  4286. + compatible = "qcom,qcrypto";
  4287. + reg = <0xfd3c0000 0x20000>,
  4288. + <0xfd3c4000 0x9000>;
  4289. + reg-names = "crypto-base","crypto-bam-base";
  4290. + interrupts = <0 297 0>;
  4291. + qcom,bam-pipe-pair = <0>;
  4292. + qcom,ce-hw-instance = <2>;
  4293. + qcom,ce-device = <1>;
  4294. + qcom,clk-mgmt-sus-res;
  4295. + qcom,msm-bus,name = "qcrypto-noc";
  4296. + qcom,msm-bus,num-cases = <2>;
  4297. + qcom,msm-bus,num-paths = <1>;
  4298. + qcom,msm-bus,vectors-KBps =
  4299. + <55 512 0 0>,
  4300. + <55 512 393600 393600>;
  4301. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  4302. + clocks = <&clock_rpm clk_qcrypto_ce3_clk>,
  4303. + <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
  4304. + <&clock_rpm clk_gcc_ce3_axi_m_clk>;
  4305. + qcom,support-core-clk-only;
  4306. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  4307. + qcom,use-sw-aes-xts-algo;
  4308. + qcom,use-sw-aes-ccm-algo;
  4309. + qcom,use-sw-ahash-algo;
  4310. + qcom,ce-opp-freq = <171430000>;
  4311. + };
  4312. +
  4313. + qcom_cedev: qcedev@fd440000 {
  4314. + compatible = "qcom,qcedev";
  4315. + reg = <0xfd440000 0x20000>,
  4316. + <0xfd444000 0x9000>;
  4317. + reg-names = "crypto-base","crypto-bam-base";
  4318. + interrupts = <0 236 0>;
  4319. + qcom,bam-pipe-pair = <1>;
  4320. + qcom,ce-hw-instance = <0>;
  4321. + qcom,ce-device = <0>;
  4322. + qcom,msm-bus,name = "qcedev-noc";
  4323. + qcom,msm-bus,num-cases = <2>;
  4324. + qcom,msm-bus,num-paths = <1>;
  4325. + qcom,msm-bus,vectors-KBps =
  4326. + <55 512 0 0>,
  4327. + <55 512 393600 393600>;
  4328. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  4329. + clocks = <&clock_rpm clk_qcedev_ce2_clk>,
  4330. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  4331. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  4332. + qcom,support-core-clk-only;
  4333. + qcom,ce-opp-freq = <171430000>;
  4334. + };
  4335. +
  4336. + qcom,qseecom@6500000{
  4337. + compatible = "qcom,qseecom";
  4338. + reg = <0x0E900000 0x1900000>;//reg = <0x6500000 0x500000>; ----> <0x0E700000 0x700000>; ----> <0x0E900000 0x1900000>; /*VENDOR_EDIT changhua add more memory for fpc1150 and alipay in TZ*/
  4339. + reg-names = "secapp-region";
  4340. + qcom,disk-encrypt-pipe-pair = <2>;
  4341. + qcom,file-encrypt-pipe-pair = <0>;
  4342. + qcom,support-multiple-ce-hw-instance;
  4343. + qcom,hlos-num-ce-hw-instances = <2>;
  4344. + qcom,hlos-ce-hw-instance = <1 2>;
  4345. + qcom,qsee-ce-hw-instance = <0>;
  4346. + qcom,msm-bus,name = "qseecom-noc";
  4347. + qcom,msm-bus,num-cases = <4>;
  4348. + qcom,msm-bus,num-paths = <1>;
  4349. + qcom,support-fde;
  4350. + qcom,support-pfe;
  4351. + qcom,no-clock-support;
  4352. + qcom,msm-bus,vectors-KBps =
  4353. + <55 512 0 0>,
  4354. + <55 512 0 0>,
  4355. + <55 512 120000 1200000>,
  4356. + <55 512 393600 3936000>;
  4357. + clock-names = "core_clk", "ufs_core_clk_src", "ufs_core_clk",
  4358. + "ufs_bus_clk", "ufs_iface_clk";
  4359. + clocks = <&clock_rpm clk_qseecom_ce1_clk>,
  4360. + <&clock_gcc clk_ufs_axi_clk_src>,
  4361. + <&clock_gcc clk_gcc_ufs_axi_clk>,
  4362. + <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
  4363. + <&clock_gcc clk_gcc_ufs_ahb_clk>;
  4364. + qcom,ce-opp-freq = <171430000>;
  4365. + };
  4366. +
  4367. + qcom,sensor-information {
  4368. + compatible = "qcom,sensor-information";
  4369. + sensor_information0: qcom,sensor-information@0 {
  4370. + qcom,sensor-type = "tsens";
  4371. + qcom,sensor-name = "tsens_tz_sensor0";
  4372. + };
  4373. +
  4374. + sensor_information1: qcom,sensor-information@1 {
  4375. + qcom,sensor-type = "tsens";
  4376. + qcom,sensor-name = "tsens_tz_sensor1";
  4377. + };
  4378. +
  4379. + sensor_information2: qcom,sensor-information@2 {
  4380. + qcom,sensor-type = "tsens";
  4381. + qcom,sensor-name = "tsens_tz_sensor2";
  4382. + qcom,alias-name = "pop_mem";
  4383. + };
  4384. +
  4385. + sensor_information3: qcom,sensor-information@3 {
  4386. + qcom,sensor-type = "tsens";
  4387. + qcom,sensor-name = "tsens_tz_sensor3";
  4388. + };
  4389. +
  4390. + sensor_information4: qcom,sensor-information@4 {
  4391. + qcom,sensor-type = "tsens";
  4392. + qcom,sensor-name = "tsens_tz_sensor4";
  4393. + };
  4394. +
  4395. + sensor_information5: qcom,sensor-information@5 {
  4396. + qcom,sensor-type = "tsens";
  4397. + qcom,sensor-name = "tsens_tz_sensor5";
  4398. + };
  4399. +
  4400. + sensor_information6: qcom,sensor-information@6 {
  4401. + qcom,sensor-type = "tsens";
  4402. + qcom,sensor-name = "tsens_tz_sensor6";
  4403. + qcom,alias-name = "cpu7";
  4404. + };
  4405. +
  4406. + sensor_information7: qcom,sensor-information@7 {
  4407. + qcom,sensor-type = "tsens";
  4408. + qcom,sensor-name = "tsens_tz_sensor7";
  4409. + qcom,alias-name = "cpu0";
  4410. + };
  4411. +
  4412. + sensor_information8: qcom,sensor-information@8 {
  4413. + qcom,sensor-type = "tsens";
  4414. + qcom,sensor-name = "tsens_tz_sensor8";
  4415. + qcom,alias-name = "cpu1";
  4416. + };
  4417. +
  4418. + sensor_information9: qcom,sensor-information@9 {
  4419. + qcom,sensor-type = "tsens";
  4420. + qcom,sensor-name = "tsens_tz_sensor9";
  4421. + qcom,alias-name = "cpu2";
  4422. + };
  4423. +
  4424. + sensor_information10: qcom,sensor-information@10 {
  4425. + qcom,sensor-type = "tsens";
  4426. + qcom,sensor-name = "tsens_tz_sensor10";
  4427. + qcom,alias-name = "cpu3";
  4428. + };
  4429. +
  4430. + sensor_information11: qcom,sensor-information@11 {
  4431. + qcom,sensor-type = "tsens";
  4432. + qcom,sensor-name = "tsens_tz_sensor11";
  4433. + };
  4434. +
  4435. + sensor_information12: qcom,sensor-information@12 {
  4436. + qcom,sensor-type = "tsens";
  4437. + qcom,sensor-name = "tsens_tz_sensor12";
  4438. + qcom,alias-name = "gpu";
  4439. + };
  4440. +
  4441. + sensor_information13: qcom,sensor-information@13 {
  4442. + qcom,sensor-type = "tsens";
  4443. + qcom,sensor-name = "tsens_tz_sensor13";
  4444. + qcom,alias-name = "cpu4";
  4445. + };
  4446. +
  4447. + sensor_information14: qcom,sensor-information@14 {
  4448. + qcom,sensor-type = "tsens";
  4449. + qcom,sensor-name = "tsens_tz_sensor14";
  4450. + qcom,alias-name = "cpu5";
  4451. + };
  4452. +
  4453. + sensor_information15: qcom,sensor-information@15 {
  4454. + qcom,sensor-type = "tsens";
  4455. + qcom,sensor-name = "tsens_tz_sensor15";
  4456. + qcom,alias-name = "cpu6";
  4457. + };
  4458. +
  4459. + sensor_information16: qcom,sensor-information@16 {
  4460. + qcom,sensor-type = "alarm";
  4461. + qcom,sensor-name = "pm8994_tz";
  4462. + qcom,scaling-factor = <1000>;
  4463. + };
  4464. +
  4465. + sensor_information17: qcom,sensor-information@17 {
  4466. + qcom,sensor-type = "adc";
  4467. + qcom,sensor-name = "msm_therm";
  4468. + };
  4469. +
  4470. + sensor_information18: qcom,sensor-information@18 {
  4471. + qcom,sensor-type = "adc";
  4472. + qcom,sensor-name = "emmc_therm";
  4473. + };
  4474. +
  4475. + sensor_information19: qcom,sensor-information@19 {
  4476. + qcom,sensor-type = "adc";
  4477. + qcom,sensor-name = "pa_therm0";
  4478. + };
  4479. +
  4480. + sensor_information20: qcom,sensor-information@20 {
  4481. + qcom,sensor-type = "adc";
  4482. + qcom,sensor-name = "pa_therm1";
  4483. + };
  4484. +
  4485. + sensor_information21: qcom,sensor-information@21 {
  4486. + qcom,sensor-type = "adc";
  4487. + qcom,sensor-name = "quiet_therm";
  4488. + };
  4489. +
  4490. + sensor_information22: qcom,sensor-information@22 {
  4491. + qcom,sensor-type = "llm";
  4492. + qcom,sensor-name = "LLM_IA57";
  4493. + };
  4494. +
  4495. + sensor_information23: qcom,sensor-information-23 {
  4496. + qcom,sensor-type = "adc";
  4497. + qcom,sensor-name = "battery";
  4498. + };
  4499. + };
  4500. +
  4501. + qcom,msm-thermal {
  4502. + compatible = "qcom,msm-thermal";
  4503. + qcom,sensor-id = <7>;
  4504. + qcom,poll-ms = <250>;
  4505. + qcom,limit-temp = <60>;
  4506. + qcom,temp-hysteresis = <10>;
  4507. + qcom,therm-reset-temp = <115>;
  4508. + qcom,freq-step = <2>;
  4509. + qcom,freq-control-mask = <0xff>;
  4510. + qcom,core-limit-temp = <80>;
  4511. + qcom,core-temp-hysteresis = <10>;
  4512. + qcom,core-control-mask = <0xfe>;
  4513. + qcom,hotplug-temp = <105>;
  4514. + qcom,hotplug-temp-hysteresis = <40>;
  4515. + qcom,cpu-sensors = "tsens_tz_sensor7", "tsens_tz_sensor8",
  4516. + "tsens_tz_sensor9", "tsens_tz_sensor10",
  4517. + "tsens_tz_sensor13", "tsens_tz_sensor14",
  4518. + "tsens_tz_sensor15", "tsens_tz_sensor6";
  4519. + qcom,freq-mitigation-temp = <95>;
  4520. + qcom,freq-mitigation-temp-hysteresis = <10>;
  4521. + qcom,freq-mitigation-value = <960000>;
  4522. + qcom,freq-mitigation-control-mask = <0xF0>;
  4523. + qcom,online-hotplug-core;
  4524. + qcom,synchronous-cluster-id = <0 1>;
  4525. + qcom,mx-restriction-temp = <5>;
  4526. + qcom,mx-restriction-temp-hysteresis = <10>;
  4527. + qcom,mx-retention-min = <3>;
  4528. + vdd-mx-supply = <&pm8994_s2_corner>;
  4529. +
  4530. + qcom,vdd-restriction-temp = <5>;
  4531. + qcom,vdd-restriction-temp-hysteresis = <10>;
  4532. +
  4533. + vdd-dig-supply = <&pm8994_s1_floor_corner>;
  4534. + vdd-gfx-supply = <&pmi8994_s2_floor_corner>;
  4535. +
  4536. + qcom,vdd-dig-rstr{
  4537. + qcom,vdd-rstr-reg = "vdd-dig";
  4538. + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  4539. + qcom,min-level = <1>; /* No Request */
  4540. + };
  4541. +
  4542. + qcom,vdd-gfx-rstr{
  4543. + qcom,vdd-rstr-reg = "vdd-gfx";
  4544. + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  4545. + qcom,min-level = <1>; /* No Request */
  4546. + };
  4547. +
  4548. + msm_thermal_freq: qcom,vdd-apps-rstr{
  4549. + qcom,vdd-rstr-reg = "vdd-apps";
  4550. + qcom,levels = <302400 600000 600000>;
  4551. + qcom,freq-req;
  4552. + };
  4553. + };
  4554. +
  4555. + qcom,bcl {
  4556. + compatible = "qcom,bcl";
  4557. + qcom,bcl-enable;
  4558. + qcom,bcl-framework-interface;
  4559. + qcom,bcl-freq-control-list = <&CPU6 &CPU7>;
  4560. + qcom,bcl-hotplug-list = <&CPU6 &CPU7>;
  4561. + qcom,bcl-soc-hotplug-list = <&CPU6 &CPU7>;
  4562. + qcom,ibat-monitor {
  4563. + qcom,low-threshold-uamp = <3400000>;
  4564. + qcom,high-threshold-uamp = <4200000>;
  4565. + qcom,mitigation-freq-khz = <768000>;
  4566. + qcom,vph-high-threshold-uv = <3500000>;
  4567. + qcom,vph-low-threshold-uv = <3300000>;
  4568. + qcom,soc-low-threshold = <20>;
  4569. + qcom,thermal-handle = <&msm_thermal_freq>;
  4570. + };
  4571. + };
  4572. +
  4573. + cnss: qcom,cnss@06300000 {
  4574. + compatible = "qcom,cnss";
  4575. + reg = <0x06300000 0x200000>;
  4576. + reg-names = "ramdump";
  4577. + wlan-en-gpio = <&msm_gpio 113 0>;
  4578. + vdd-wlan-supply = <&bt_vreg>;
  4579. + vdd-wlan-io-supply = <&pm8994_s4>;
  4580. + vdd-wlan-xtal-supply = <&pm8994_l30>;
  4581. + qcom,notify-modem-status;
  4582. + pinctrl-names = "default";
  4583. + pinctrl-0 = <&cnss_default>;
  4584. + qcom,wlan-rc-num = <1>;
  4585. + qcom,wlan-uart-access;
  4586. +
  4587. + qcom,msm-bus,name = "msm-cnss";
  4588. + qcom,msm-bus,num-cases = <4>;
  4589. + qcom,msm-bus,num-paths = <1>;
  4590. + qcom,msm-bus,vectors-KBps =
  4591. + <100 512 0 0>, /* No vote */
  4592. + <100 512 6250 200000>, /* 50 Mbps */
  4593. + <100 512 25000 200000>, /* 200 Mbps */
  4594. + <100 512 100000 200000>; /* 800 Mbps */
  4595. + };
  4596. +
  4597. + audio_heap {
  4598. + compatible = "qcom,msm-shared-memory";
  4599. + qcom,proc-id = <1>;
  4600. + linux,contiguous-region = <&audio_mem>;
  4601. + };
  4602. +
  4603. + adsp_heap {
  4604. + compatible = "qcom,msm-shared-memory";
  4605. + qcom,proc-id = <1>;
  4606. + linux,contiguous-region = <&adsp_mem>;
  4607. + };
  4608. +
  4609. + qcom,msm-core@fc4b8000 {
  4610. + compatible = "qcom,apss-core-ea";
  4611. + reg = <0xfc4b8000 0x1000>;
  4612. + qcom,low-hyst-temp = <10>;
  4613. + qcom,high-hyst-temp = <5>;
  4614. + qcom,polling-interval = <50>;
  4615. +
  4616. + qcom,core-mapping {
  4617. + qcom,cpu0-chars {
  4618. + qcom,sensor = <&sensor_information7>;
  4619. + qcom,cpu-name = <&CPU0>;
  4620. + };
  4621. +
  4622. + qcom,cpu1-chars {
  4623. + qcom,sensor = <&sensor_information8>;
  4624. + qcom,cpu-name = <&CPU1>;
  4625. + };
  4626. +
  4627. + qcom,cpu2-chars {
  4628. + qcom,sensor = <&sensor_information9>;
  4629. + qcom,cpu-name = <&CPU2>;
  4630. + };
  4631. +
  4632. + qcom,cpu3-chars {
  4633. + qcom,sensor = <&sensor_information10>;
  4634. + qcom,cpu-name = <&CPU3>;
  4635. + };
  4636. +
  4637. + qcom,cpu4-chars {
  4638. + qcom,sensor = <&sensor_information13>;
  4639. + qcom,cpu-name = <&CPU4>;
  4640. + };
  4641. +
  4642. + qcom,cpu5-chars {
  4643. + qcom,sensor = <&sensor_information14>;
  4644. + qcom,cpu-name = <&CPU5>;
  4645. + };
  4646. +
  4647. + qcom,cpu6-chars {
  4648. + qcom,sensor = <&sensor_information15>;
  4649. + qcom,cpu-name = <&CPU6>;
  4650. + };
  4651. +
  4652. + qcom,cpu7-chars {
  4653. + qcom,sensor = <&sensor_information6>;
  4654. + qcom,cpu-name = <&CPU7>;
  4655. + };
  4656. + };
  4657. + };
  4658. +
  4659. + qcom,system-health-monitor {
  4660. + compatible = "qcom,system-health-monitor";
  4661. +
  4662. + qcom,system-health-monitor-modem {
  4663. + qcom,subsys-name = "msm_mpss";
  4664. + qcom,ssrestart-string = "modem";
  4665. + };
  4666. + };
  4667. +
  4668. + cpuss_dump {
  4669. + compatible = "qcom,cpuss-dump";
  4670. + qcom,itlb_dump100 {
  4671. + qcom,dump-node = <&L1_itlb_100>;
  4672. + qcom,dump-id = <0x24>;
  4673. + };
  4674. + qcom,itlb_dump101 {
  4675. + qcom,dump-node = <&L1_itlb_101>;
  4676. + qcom,dump-id = <0x25>;
  4677. + };
  4678. + qcom,itlb_dump102 {
  4679. + qcom,dump-node = <&L1_itlb_102>;
  4680. + qcom,dump-id = <0x26>;
  4681. + };
  4682. + qcom,itlb_dump103 {
  4683. + qcom,dump-node = <&L1_itlb_103>;
  4684. + qcom,dump-id = <0x27>;
  4685. + };
  4686. + qcom,dtlb_dump100 {
  4687. + qcom,dump-node = <&L1_dtlb_100>;
  4688. + qcom,dump-id = <0x44>;
  4689. + };
  4690. + qcom,dtlb_dump101 {
  4691. + qcom,dump-node = <&L1_dtlb_101>;
  4692. + qcom,dump-id = <0x45>;
  4693. + };
  4694. + qcom,dtlb_dump102 {
  4695. + qcom,dump-node = <&L1_dtlb_102>;
  4696. + qcom,dump-id = <0x46>;
  4697. + };
  4698. + qcom,dtlb_dump103 {
  4699. + qcom,dump-node = <&L1_dtlb_103>;
  4700. + qcom,dump-id = <0x47>;
  4701. + };
  4702. + qcom,l2_tlb_dump0 {
  4703. + qcom,dump-node = <&L2_tlb_0>;
  4704. + qcom,dump-id = <0x120>;
  4705. + };
  4706. + qcom,l2_tlb_dump100 {
  4707. + qcom,dump-node = <&L2_tlb_1>;
  4708. + qcom,dump-id = <0x121>;
  4709. + };
  4710. + qcom,l2_dump0 {
  4711. + qcom,dump-node = <&L2_0>; /* L2 cache dump for A53 cluster */
  4712. + qcom,dump-id = <0xC0>;
  4713. + };
  4714. + qcom,l2_dump1 {
  4715. + qcom,dump-node = <&L2_1>; /* L2 cache dumo for A57 cluster */
  4716. + qcom,dump-id = <0xC1>;
  4717. + };
  4718. + qcom,l1_i_cache0 {
  4719. + qcom,dump-node = <&L1_I_0>;
  4720. + qcom,dump-id = <0x60>;
  4721. + };
  4722. + qcom,l1_i_cache1 {
  4723. + qcom,dump-node = <&L1_I_1>;
  4724. + qcom,dump-id = <0x61>;
  4725. + };
  4726. + qcom,l1_i_cache2 {
  4727. + qcom,dump-node = <&L1_I_2>;
  4728. + qcom,dump-id = <0x62>;
  4729. + };
  4730. + qcom,l1_i_cache3 {
  4731. + qcom,dump-node = <&L1_I_3>;
  4732. + qcom,dump-id = <0x63>;
  4733. + };
  4734. + qcom,l1_i_cache100 {
  4735. + qcom,dump-node = <&L1_I_100>;
  4736. + qcom,dump-id = <0x64>;
  4737. + };
  4738. + qcom,l1_i_cache101 {
  4739. + qcom,dump-node = <&L1_I_101>;
  4740. + qcom,dump-id = <0x65>;
  4741. + };
  4742. + qcom,l1_i_cache102 {
  4743. + qcom,dump-node = <&L1_I_102>;
  4744. + qcom,dump-id = <0x66>;
  4745. + };
  4746. + qcom,l1_i_cache103 {
  4747. + qcom,dump-node = <&L1_I_103>;
  4748. + qcom,dump-id = <0x67>;
  4749. + };
  4750. + qcom,l1_d_cache0 {
  4751. + qcom,dump-node = <&L1_D_0>;
  4752. + qcom,dump-id = <0x80>;
  4753. + };
  4754. + qcom,l1_d_cache1 {
  4755. + qcom,dump-node = <&L1_D_1>;
  4756. + qcom,dump-id = <0x81>;
  4757. + };
  4758. + qcom,l1_d_cache2 {
  4759. + qcom,dump-node = <&L1_D_2>;
  4760. + qcom,dump-id = <0x82>;
  4761. + };
  4762. + qcom,l1_d_cache3 {
  4763. + qcom,dump-node = <&L1_D_3>;
  4764. + qcom,dump-id = <0x83>;
  4765. + };
  4766. + qcom,l1_d_cache100 {
  4767. + qcom,dump-node = <&L1_D_100>;
  4768. + qcom,dump-id = <0x84>;
  4769. + };
  4770. + qcom,l1_d_cache101 {
  4771. + qcom,dump-node = <&L1_D_101>;
  4772. + qcom,dump-id = <0x85>;
  4773. + };
  4774. + qcom,l1_d_cache102 {
  4775. + qcom,dump-node = <&L1_D_102>;
  4776. + qcom,dump-id = <0x86>;
  4777. + };
  4778. + qcom,l1_d_cache103 {
  4779. + qcom,dump-node = <&L1_D_103>;
  4780. + qcom,dump-id = <0x87>;
  4781. + };
  4782. + };
  4783. +
  4784. + qcom,avtimer@fe09c000 {
  4785. + compatible = "qcom,avtimer";
  4786. + reg = <0xFE09C00C 0x4>,
  4787. + <0xFE09C010 0x4>;
  4788. + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
  4789. + qcom,clk_div = <27>;
  4790. + };
  4791. +
  4792. + cci@f9100000 {
  4793. + compatible = "arm,cci-400";
  4794. + #address-cells = <1>;
  4795. + #size-cells = <1>;
  4796. + reg = <0xf9100000 0x1000>;
  4797. + ranges = <0x0 0xf9100000 0x10000>;
  4798. + hw-version = <8>;
  4799. +
  4800. + pmu@a000 {
  4801. + compatible = "arm,cci-400-pmu";
  4802. + reg = <0x9000 0x5000>;
  4803. + interrupts = <0 344 0>,
  4804. + <0 344 0>,
  4805. + <0 344 0>,
  4806. + <0 344 0>,
  4807. + <0 344 0>;
  4808. + };
  4809. +
  4810. + };
  4811. +};
  4812. +
  4813. +&gdsc_usb30 {
  4814. + reg = <0xfc4003c4 0x4>;
  4815. + status = "ok";
  4816. +};
  4817. +
  4818. +&gdsc_pcie_0 {
  4819. + status = "ok";
  4820. +};
  4821. +
  4822. +&gdsc_pcie_1 {
  4823. + status = "ok";
  4824. +};
  4825. +
  4826. +&gdsc_ufs {
  4827. + status = "ok";
  4828. +};
  4829. +
  4830. +&gdsc_venus {
  4831. + clock-names = "ocmem_clk", "bus_clk", "core_clk";
  4832. + clocks = <&clock_mmss clk_venus0_ocmemnoc_clk>,
  4833. + <&clock_mmss clk_venus0_axi_clk>,
  4834. + <&clock_mmss clk_venus0_vcodec0_clk>;
  4835. + status = "ok";
  4836. +};
  4837. +
  4838. +&gdsc_venus_core0 {
  4839. + qcom,support-hw-trigger;
  4840. + clock-names = "core0_clk";
  4841. + clocks = <&clock_mmss clk_venus0_core0_vcodec_clk>;
  4842. + status = "ok";
  4843. +};
  4844. +
  4845. +&gdsc_venus_core1 {
  4846. + qcom,support-hw-trigger;
  4847. + clock-names = "core1_clk";
  4848. + clocks = <&clock_mmss clk_venus0_core1_vcodec_clk>;
  4849. + status = "ok";
  4850. +};
  4851. +
  4852. +&gdsc_venus_core2 {
  4853. + qcom,support-hw-trigger;
  4854. + clock-names = "core2_clk";
  4855. + clocks = <&clock_mmss clk_venus0_core2_vcodec_clk>;
  4856. + status = "ok";
  4857. +};
  4858. +
  4859. +&gdsc_mdss {
  4860. + clock-names = "bus_clk", "core_clk";
  4861. + clocks = <&clock_mmss clk_mdss_axi_clk>,
  4862. + <&clock_mmss clk_mdss_mdp_clk>;
  4863. + status = "ok";
  4864. +};
  4865. +
  4866. +&gdsc_camss_top {
  4867. + clock-names = "csi0_clk", "csi1_clk", "bus_clk";
  4868. + clocks = <&clock_mmss clk_camss_csi_vfe0_clk>,
  4869. + <&clock_mmss clk_camss_csi_vfe1_clk>,
  4870. + <&clock_mmss clk_camss_micro_ahb_clk>;
  4871. + status = "ok";
  4872. +};
  4873. +
  4874. +&gdsc_jpeg {
  4875. + clock-names = "bus_clk", "core0_clk", "core1_clk", "core2_clk";
  4876. + clocks = <&clock_mmss clk_camss_jpeg_jpeg_axi_clk>,
  4877. + <&clock_mmss clk_camss_jpeg_jpeg0_clk>,
  4878. + <&clock_mmss clk_camss_jpeg_jpeg1_clk>,
  4879. + <&clock_mmss clk_camss_jpeg_jpeg2_clk>;
  4880. + parent-supply = <&gdsc_camss_top>;
  4881. + status = "ok";
  4882. +};
  4883. +
  4884. +&gdsc_vfe {
  4885. + clock-names = "bus_clk";
  4886. + clocks = <&clock_mmss clk_camss_vfe_vfe_axi_clk>;
  4887. + parent-supply = <&gdsc_camss_top>;
  4888. + status = "ok";
  4889. +};
  4890. +
  4891. +&gdsc_cpp {
  4892. + clock-names = "bus_clk", "core_clk";
  4893. + clocks = <&clock_mmss clk_camss_vfe_cpp_axi_clk>,
  4894. + <&clock_mmss clk_camss_vfe_cpp_clk>;
  4895. + parent-supply = <&gdsc_camss_top>;
  4896. + status = "ok";
  4897. +};
  4898. +
  4899. +&gdsc_fd {
  4900. + clock-names = "bus_clk", "core_clk";
  4901. + clocks = <&clock_mmss clk_fd_axi_clk>,
  4902. + <&clock_mmss clk_fd_core_clk>;
  4903. + status = "ok";
  4904. +};
  4905. +
  4906. +&gdsc_oxili_cx {
  4907. + status = "ok";
  4908. +};
  4909. +
  4910. +&gdsc_oxili_gx {
  4911. + clock-names = "core_clk";
  4912. + clocks = <&clock_mmss clk_oxili_gfx3d_clk>;
  4913. + status = "ok";
  4914. + parent-supply = <&pmi8994_s2_corner>;
  4915. +};
  4916. +
  4917. +#include "msm-pm8994-rpm-regulator.dtsi"
  4918. +#include "msm-pm8994.dtsi"
  4919. +#include "msm-pmi8994.dtsi"
  4920. +#include "msm8994-regulator.dtsi"
  4921. +#include "msm8994-ion.dtsi"
  4922. +#include "msm8994-iommu.dtsi"
  4923. +#include "msm8994-iommu-domains.dtsi"
  4924. +#include "msm8994-camera.dtsi"
  4925. +#include "msm8994-gpu.dtsi"
  4926. +#include "dsi-panel-sim-video.dtsi"
  4927. +#include "dsi-panel-sim-dualmipi0-video.dtsi"
  4928. +#include "dsi-panel-sim-dualmipi1-video.dtsi"
  4929. +#include "dsi-panel-sim-cmd.dtsi"
  4930. +#include "dsi-panel-sim-dualmipi0-cmd.dtsi"
  4931. +#include "dsi-panel-sim-dualmipi1-cmd.dtsi"
  4932. diff --git a/arch/arm64/boot/dts/14049_HW_11/dsi-panel-jd35695-1080p-cmd.dtsi b/arch/arm64/boot/dts/14049_HW_11/dsi-panel-jd35695-1080p-cmd.dtsi
  4933. new file mode 100755
  4934. index 0000000..b92a212
  4935. --- /dev/null
  4936. +++ b/arch/arm64/boot/dts/14049_HW_11/dsi-panel-jd35695-1080p-cmd.dtsi
  4937. @@ -0,0 +1,212 @@
  4938. +/************************************************************
  4939. + * Copyright (c) 2013-2013 OPPO Mobile communication Corp.ltd.,
  4940. + * VENDOR_EDIT
  4941. + * Description: device tree for jdi cmd panel.
  4942. + * Version : 1.0
  4943. + * Date : 2013-12-12
  4944. + * Author : yangxinqin
  4945. + *
  4946. + * This program is free software; you can redistribute it and/or modify
  4947. + * it under the terms of the GNU General Public License version 2 and
  4948. + * only version 2 as published by the Free Software Foundation.
  4949. + *
  4950. + * This program is distributed in the hope that it will be useful,
  4951. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  4952. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  4953. + * GNU General Public License for more details.
  4954. + */
  4955. +
  4956. +/*---------------------------------------------------------------------------
  4957. + * This file is autogenerated file using gcdb parser. Please do not edit it.
  4958. + * Update input XML file to add a new entry or update variable in this file
  4959. + * VERSION = "1.0"
  4960. + *---------------------------------------------------------------------------*/
  4961. +&mdss_mdp {
  4962. +dsi_jd35695_1080_cmd: qcom,mdss_dsi_jd35695_1080p_cmd {
  4963. + compatible = "qcom,mdss-dsi-panel";
  4964. + status = "ok";
  4965. + qcom,cont-splash-enabled;
  4966. + qcom,mdss-dsi-panel-name = "jd35695 1080p cmd mode dsi panel";
  4967. + qcom,mdss-dsi-panel-manufacture = "JDI";
  4968. + qcom,mdss-dsi-panel-version = "JD35695";
  4969. + qcom,mdss-dsi-backlight-version= "PMI8994";
  4970. + qcom,mdss-dsi-backlight-manufacture = "Qualcomm";
  4971. + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
  4972. + qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  4973. + qcom,mdss-dsi-panel-destination = "display_1";
  4974. + qcom,mdss-dsi-panel-framerate = <60>;
  4975. + qcom,mdss-dsi-virtual-channel-id = <0>;
  4976. + qcom,mdss-dsi-stream = <0>;
  4977. + qcom,mdss-dsi-panel-width = <1080>;
  4978. + qcom,mdss-dsi-panel-height = <1920>;
  4979. + qcom,mdss-dsi-h-front-porch = <100>;
  4980. + qcom,mdss-dsi-h-back-porch = <82>;
  4981. + qcom,mdss-dsi-h-pulse-width = <8>;
  4982. + qcom,mdss-dsi-h-sync-skew = <0>;
  4983. + qcom,mdss-dsi-v-back-porch = <7>;
  4984. + qcom,mdss-dsi-v-front-porch = <3>;
  4985. + qcom,mdss-dsi-v-pulse-width = <2>;
  4986. + qcom,mdss-dsi-h-left-border = <0>;
  4987. + qcom,mdss-dsi-h-right-border = <0>;
  4988. + qcom,mdss-dsi-v-top-border = <0>;
  4989. + qcom,mdss-dsi-v-bottom-border = <0>;
  4990. + qcom,mdss-dsi-bpp = <24>;
  4991. + qcom,mdss-dsi-underflow-color = <0x0000ff>;
  4992. + qcom,mdss-dsi-border-color = <0>;
  4993. + qcom,mdss-dsi-on-command = [
  4994. + 15 01 00 00 00 00 02 FF 10
  4995. + 15 01 00 00 00 00 02 35 00
  4996. + 39 01 00 00 00 00 05 2a 00 00 04 37
  4997. + 39 01 00 00 00 00 05 2b 00 00 07 7f
  4998. +
  4999. + 29 01 00 00 00 00 03 44 05 00
  5000. + 15 01 00 00 00 00 02 FF E0
  5001. + 15 01 00 00 00 00 02 B5 86
  5002. + 15 01 00 00 00 00 02 B6 77
  5003. + 15 01 00 00 00 00 02 B8 AD
  5004. + 15 01 00 00 00 00 02 FB 01
  5005. + 15 01 00 00 00 00 02 FF 10
  5006. +
  5007. + 15 01 00 00 00 00 02 36 03 //add for lcd rotater 180
  5008. + 15 01 00 00 00 00 02 FF 23
  5009. + 15 01 00 00 00 00 02 08 03
  5010. + 15 01 00 00 00 00 02 FF 10
  5011. + 15 01 00 00 00 00 02 51 FF
  5012. + 15 01 00 00 00 00 02 53 2C
  5013. + 15 01 00 00 00 00 02 55 02
  5014. +
  5015. + 15 01 00 00 00 00 02 FF 23
  5016. + 15 01 00 00 00 00 02 FB 01
  5017. + 15 01 00 00 00 00 02 05 24
  5018. + 15 01 00 00 00 00 02 01 84
  5019. + 15 01 00 00 00 00 02 FF 10
  5020. +
  5021. + 05 01 00 00 64 00 02 11 00
  5022. + 05 01 00 00 11 00 02 29 00
  5023. +
  5024. + ];
  5025. + qcom,mdss-dsi-off-command = [
  5026. + 15 01 00 00 00 00 02 FF 10
  5027. + 15 01 00 00 00 00 02 53 00
  5028. + 05 01 00 00 11 00 02 28 00
  5029. + 05 01 00 00 32 00 02 10 00];
  5030. +
  5031. + qcom,mdss-dsi-color-test-on-command=
  5032. + [
  5033. + 05 01 00 00 32 00 02 28 00
  5034. + 05 01 00 00 32 00 02 10 00
  5035. + 15 01 00 00 00 00 02 FF 24
  5036. + 15 01 00 00 00 00 02 EC 01
  5037. + 15 01 00 00 00 00 02 FF 20
  5038. + 15 01 00 00 00 00 02 67 4D];
  5039. +
  5040. +
  5041. + qcom,mdss-dsi-color-test-off-command =
  5042. + [
  5043. + 15 01 00 00 00 00 02 FF 24
  5044. + 15 01 00 00 00 00 02 EC 00
  5045. + 15 01 00 00 00 00 02 FF 10
  5046. + 15 01 00 00 00 00 02 35 00
  5047. + 29 01 00 00 00 00 03 44 05 00
  5048. + 15 01 00 00 00 00 02 FF 10
  5049. + 05 01 00 00 78 00 02 11 00
  5050. + 05 01 00 00 32 00 02 29 00];
  5051. +
  5052. + qcom,mdss-dsi-cabc-off-command = [15 01 00 00 10 00 02 55 00
  5053. + 05 01 00 00 10 00 02 29 00];
  5054. + qcom,mdss-dsi-cabc-ui-command = [15 01 00 00 10 00 02 55 01
  5055. + 05 01 00 00 10 00 02 29 00];
  5056. + qcom,mdss-dsi-cabc-still-image-command = [15 01 00 00 10 00 02 55 02
  5057. + 05 01 00 00 10 00 02 29 00];
  5058. + qcom,mdss-dsi-cabc-video-command = [15 01 00 00 10 00 02 55 03
  5059. + 05 01 00 00 10 00 02 29 00];
  5060. +
  5061. + qcom,mdss-dsi-on-command_shoushi = [
  5062. +
  5063. + 15 01 00 00 00 00 02 36 03 //add for lcd rotater 180
  5064. + 15 01 00 00 00 00 02 FF 23
  5065. + 15 01 00 00 00 00 02 08 03
  5066. + 15 01 00 00 00 00 02 FF 10
  5067. + 15 01 00 00 00 00 02 51 FF
  5068. + 15 01 00 00 00 00 02 53 2C
  5069. + 15 01 00 00 00 00 02 55 02
  5070. +
  5071. + 15 01 00 00 00 00 02 FF 23
  5072. + 15 01 00 00 00 00 02 FB 01
  5073. + 15 01 00 00 00 00 02 05 24
  5074. + 15 01 00 00 00 00 02 01 84
  5075. + 15 01 00 00 00 00 02 FF 10
  5076. + 05 01 00 00 78 00 02 11 00
  5077. + 05 01 00 00 60 00 02 29 00
  5078. +
  5079. + ];
  5080. +
  5081. + qcom,mdss-dsi-color-test-on-command-state = "dsi_lp_mode";
  5082. + qcom,mdss-dsi-color-test-off-command-state = "dsi_lp_mode";
  5083. +
  5084. + qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  5085. + qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  5086. + qcom,mdss-dsi-h-sync-pulse = <1>;
  5087. + qcom,mdss-dsi-traffic-mode = "burst_mode";
  5088. + qcom,mdss-dsi-lane-map = "lane_map_0123";
  5089. + qcom,mdss-dsi-bllp-eof-power-mode;
  5090. + qcom,mdss-dsi-bllp-power-mode;
  5091. + qcom,mdss-dsi-lane-0-state;
  5092. + qcom,mdss-dsi-lane-1-state;
  5093. + qcom,mdss-dsi-lane-2-state;
  5094. + qcom,mdss-dsi-lane-3-state;
  5095. + qcom,mdss-dsi-panel-timings = [E7 43 37 00 60 6C 39 45 5b 03 04 00];
  5096. +
  5097. +
  5098. +
  5099. + qcom,mdss-dsi-t-clk-post = <0x20>;
  5100. + qcom,mdss-dsi-t-clk-pre = <0x3e>;
  5101. + qcom,mdss-dsi-dma-trigger = "trigger_sw";
  5102. + qcom,mdss-dsi-mdp-trigger = "none";
  5103. + qcom,mdss-dsi-te-pin-select = <1>;
  5104. + qcom,mdss-dsi-wr-mem-start = <0x2c>;
  5105. + qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  5106. + qcom,mdss-dsi-te-dcs-command = <1>;
  5107. + qcom,mdss-dsi-te-check-enable;
  5108. + qcom,mdss-dsi-te-using-te-pin;
  5109. +
  5110. +
  5111. +
  5112. +
  5113. + qcom,mdss-dsi-bl-min-level = <1>;
  5114. + qcom,mdss-dsi-bl-max-level = <4095>;/*guozhiming@oem.cn modify 2015-03-24*/
  5115. + qcom,mdss-dsi-lp11-init;
  5116. + //qcom,mdss-dsi-init-delay-us=<50000>;
  5117. + /**************************************************************************/
  5118. + // qcom,esd-check-enabled;
  5119. + // qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08];
  5120. + // qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
  5121. + // qcom,mdss-dsi-panel-status-check-mode = "reg_read_jd35695";
  5122. + // qcom,mdss-dsi-panel-status-read-length = <8>;
  5123. + // qcom,mdss-dsi-panel-max-error-count = <2>;
  5124. + // qcom,mdss-dsi-panel-status-value = <0x9c 0x00 0x00 0x02 0x40 0x80 0x00 0x00>;
  5125. + /******************************************************************************/
  5126. + // qcom,mdss-dsi-dma-trigger = "trigger_sw";
  5127. + // qcom,mdss-dsi-mdp-trigger = "trigger_sw";
  5128. +
  5129. +
  5130. +
  5131. + // qcom,mdss-tear-check-frame-rate=<6000>;
  5132. + //qcom,mdss-tear-check-sync-cfg-height = <1932>; /* Height + VBP + VFP + VSW */
  5133. + //qcom,mdss-tear-check-sync-init-val= <1920>; /* Height */
  5134. + //qcom,mdss-tear-check-sync-threshold-start = <4>;
  5135. + //qcom,mdss-tear-check-sync-threshold-continue = <4>;
  5136. + //qcom,mdss-tear-check-start-pos= <1920>; /* Height */
  5137. + //qcom,mdss-tear-check-rd-ptr-trigger-intr= <1921>; /* Height + 1 */
  5138. +
  5139. +
  5140. + qcom,mdss-pan-physical-width-dimension = <70>;
  5141. + qcom,mdss-pan-physical-height-dimension = <127>;
  5142. +
  5143. + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  5144. + qcom,mdss-dsi-reset-sequence = <1 11>, <0 2>, <1 12>;
  5145. +
  5146. + };
  5147. +};
  5148. +
  5149. +
  5150. diff --git a/arch/arm64/boot/dts/14049_HW_11/msm8994.dtsi b/arch/arm64/boot/dts/14049_HW_11/msm8994.dtsi
  5151. new file mode 100644
  5152. index 0000000..21dadf8
  5153. --- /dev/null
  5154. +++ b/arch/arm64/boot/dts/14049_HW_11/msm8994.dtsi
  5155. @@ -0,0 +1,3812 @@
  5156. +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  5157. + *
  5158. + * This program is free software; you can redistribute it and/or modify
  5159. + * it under the terms of the GNU General Public License version 2 and
  5160. + * only version 2 as published by the Free Software Foundation.
  5161. + *
  5162. + * This program is distributed in the hope that it will be useful,
  5163. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  5164. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  5165. + * GNU General Public License for more details.
  5166. + */
  5167. +
  5168. +/memreserve/ 0x00000000 0x00001000;
  5169. +/memreserve/ 0xac1c0000 0x00001000;
  5170. +
  5171. +#include "skeleton64.dtsi"
  5172. +#include <dt-bindings/clock/msm-clocks-8994.h>
  5173. +
  5174. +/ {
  5175. + model = "Qualcomm Technologies, Inc. MSM 8994";
  5176. + compatible = "qcom,msm8994";
  5177. + qcom,msm-id = <207 0x0>;
  5178. + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  5179. + interrupt-parent = <&intc>;
  5180. +
  5181. + chosen {
  5182. + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1";
  5183. + };
  5184. +
  5185. + aliases {
  5186. + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  5187. + /*do not enable sdhc2 and sdhc3
  5188. + sdhc2 = &sdhc_2;
  5189. + sdhc3 = &sdhc_3;
  5190. + */
  5191. + i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
  5192. + i2c1 = &i2c_1;
  5193. + i2c2 = &i2c_2;
  5194. + i2c5 = &i2c_5;
  5195. + spi0 = &spi_0;
  5196. + /*#ifdef VENDOR_EDIT modify for fpc1021 fingerprints*/
  5197. + spi12 = &spi_12;
  5198. + /*#end VENDOR_EDIT*/
  5199. + qup2 = &i2c_2;
  5200. + };
  5201. +
  5202. + cpus {
  5203. + #address-cells = <1>;
  5204. + #size-cells = <0>;
  5205. + cpu-map {
  5206. + cluster0 {
  5207. + core0 {
  5208. + cpu = <&CPU0>;
  5209. + };
  5210. + core1 {
  5211. + cpu = <&CPU1>;
  5212. + };
  5213. + core2 {
  5214. + cpu = <&CPU2>;
  5215. + };
  5216. + core3 {
  5217. + cpu = <&CPU3>;
  5218. + };
  5219. + };
  5220. +
  5221. + cluster1 {
  5222. + core0 {
  5223. + cpu = <&CPU4>;
  5224. + };
  5225. + core1 {
  5226. + cpu = <&CPU5>;
  5227. + };
  5228. + core2 {
  5229. + cpu = <&CPU6>;
  5230. + };
  5231. + core3 {
  5232. + cpu = <&CPU7>;
  5233. + };
  5234. + };
  5235. + };
  5236. +
  5237. + CPU0: cpu@0 {
  5238. + device_type = "cpu";
  5239. + compatible = "arm,cortex-a53";
  5240. + reg = <0x0>;
  5241. + enable-method = "qcom,8994-arm-cortex-acc";
  5242. + qcom,acc = <&acc0>;
  5243. + qcom,ldo = <&ldo0>;
  5244. + next-level-cache = <&L2_0>;
  5245. + L2_0: l2-cache {
  5246. + compatible = "arm,arch-cache";
  5247. + cache-level = <2>;
  5248. + power-domain = <&l2ccc_0>;
  5249. + qcom,dump-size = <0x0>; /* A53 L2 dump not supported */
  5250. + L2_tlb_0: l2-tlb {
  5251. + qcom,dump-size = <0x4000>;
  5252. + };
  5253. + };
  5254. + L1_I_0: l1-icache {
  5255. + compatible = "arm,arch-cache";
  5256. + qcom,dump-size = <0x9040>;
  5257. + };
  5258. + L1_D_0: l1-dcache {
  5259. + compatible = "arm,arch-cache";
  5260. + qcom,dump-size = <0x9040>;
  5261. + };
  5262. + };
  5263. +
  5264. + CPU1: cpu@1 {
  5265. + device_type = "cpu";
  5266. + compatible = "arm,cortex-a53";
  5267. + reg = <0x1>;
  5268. + enable-method = "qcom,8994-arm-cortex-acc";
  5269. + qcom,acc = <&acc1>;
  5270. + qcom,ldo = <&ldo1>;
  5271. + next-level-cache = <&L2_0>;
  5272. + L1_I_1: l1-icache {
  5273. + compatible = "arm,arch-cache";
  5274. + qcom,dump-size = <0x9040>;
  5275. + };
  5276. + L1_D_1: l1-dcache {
  5277. + compatible = "arm,arch-cache";
  5278. + qcom,dump-size = <0x9040>;
  5279. + };
  5280. + };
  5281. +
  5282. + CPU2: cpu@2 {
  5283. + device_type = "cpu";
  5284. + compatible = "arm,cortex-a53";
  5285. + reg = <0x2>;
  5286. + enable-method = "qcom,8994-arm-cortex-acc";
  5287. + qcom,acc = <&acc2>;
  5288. + qcom,ldo = <&ldo2>;
  5289. + next-level-cache = <&L2_0>;
  5290. + L1_I_2: l1-icache {
  5291. + compatible = "arm,arch-cache";
  5292. + qcom,dump-size = <0x9040>;
  5293. + };
  5294. + L1_D_2: l1-dcache {
  5295. + compatible = "arm,arch-cache";
  5296. + qcom,dump-size = <0x9040>;
  5297. + };
  5298. + };
  5299. +
  5300. + CPU3: cpu@3 {
  5301. + device_type = "cpu";
  5302. + compatible = "arm,cortex-a53";
  5303. + reg = <0x3>;
  5304. + enable-method = "qcom,8994-arm-cortex-acc";
  5305. + qcom,acc = <&acc3>;
  5306. + qcom,ldo = <&ldo3>;
  5307. + next-level-cache = <&L2_0>;
  5308. + L1_I_3: l1-icache {
  5309. + compatible = "arm,arch-cache";
  5310. + qcom,dump-size = <0x9040>;
  5311. + };
  5312. + L1_D_3: l1-dcache {
  5313. + compatible = "arm,arch-cache";
  5314. + qcom,dump-size = <0x9040>;
  5315. + };
  5316. + };
  5317. +
  5318. + CPU4: cpu@100 {
  5319. + device_type = "cpu";
  5320. + compatible = "arm,cortex-a57";
  5321. + reg = <0x100>;
  5322. + enable-method = "qcom,8994-arm-cortex-acc";
  5323. + qcom,acc = <&acc4>;
  5324. + qcom,ldo = <&ldo4>;
  5325. + next-level-cache = <&L2_1>;
  5326. + L2_1: l2-cache {
  5327. + compatible = "arm,arch-cache";
  5328. + cache-level = <2>;
  5329. + qcom,dump-size = <0x280040>; /*A57 Cluster L2 size is 1MB */
  5330. + power-domain = <&l2ccc_1>;
  5331. + L2_tlb_1: l2-tlb {
  5332. + qcom,dump-size = <0x4000>;
  5333. + };
  5334. + };
  5335. + L1_itlb_100: l1-itlb {
  5336. + qcom,dump-size = <0x400>;
  5337. + };
  5338. + L1_dtlb_100: l1-dtlb {
  5339. + qcom,dump-size = <0x400>;
  5340. + };
  5341. + L1_I_100: l1-icache {
  5342. + compatible = "arm,arch-cache";
  5343. + qcom,dump-size = <0xd840>;
  5344. + };
  5345. + L1_D_100: l1-dcache {
  5346. + compatible = "arm,arch-cache";
  5347. + qcom,dump-size = <0x9040>;
  5348. + };
  5349. + };
  5350. +
  5351. + CPU5: cpu@101 {
  5352. + device_type = "cpu";
  5353. + compatible = "arm,cortex-a57";
  5354. + reg = <0x101>;
  5355. + enable-method = "qcom,8994-arm-cortex-acc";
  5356. + qcom,acc = <&acc5>;
  5357. + qcom,ldo = <&ldo5>;
  5358. + next-level-cache = <&L2_1>;
  5359. + L1_itlb_101: l1-itlb {
  5360. + qcom,dump-size = <0x400>;
  5361. + };
  5362. + L1_dtlb_101: l1-dtlb {
  5363. + qcom,dump-size = <0x400>;
  5364. + };
  5365. + L1_I_101: l1-icache {
  5366. + compatible = "arm,arch-cache";
  5367. + qcom,dump-size = <0xd840>;
  5368. + };
  5369. + L1_D_101: l1-dcache {
  5370. + compatible = "arm,arch-cache";
  5371. + qcom,dump-size = <0x9040>;
  5372. + };
  5373. + };
  5374. +
  5375. + CPU6: cpu@102 {
  5376. + device_type = "cpu";
  5377. + compatible = "arm,cortex-a57";
  5378. + reg = <0x102>;
  5379. + enable-method = "qcom,8994-arm-cortex-acc";
  5380. + qcom,acc = <&acc6>;
  5381. + qcom,ldo = <&ldo6>;
  5382. + next-level-cache = <&L2_1>;
  5383. + L1_itlb_102: l1-itlb {
  5384. + qcom,dump-size = <0x400>;
  5385. + };
  5386. + L1_dtlb_102: l1-dtlb {
  5387. + qcom,dump-size = <0x400>;
  5388. + };
  5389. + L1_I_102: l1-icache {
  5390. + compatible = "arm,arch-cache";
  5391. + qcom,dump-size = <0xd840>;
  5392. + };
  5393. + L1_D_102: l1-dcache {
  5394. + compatible = "arm,arch-cache";
  5395. + qcom,dump-size = <0x9040>;
  5396. + };
  5397. + };
  5398. +
  5399. + CPU7: cpu@103 {
  5400. + device_type = "cpu";
  5401. + compatible = "arm,cortex-a57";
  5402. + reg = <0x103>;
  5403. + enable-method = "qcom,8994-arm-cortex-acc";
  5404. + qcom,acc = <&acc7>;
  5405. + qcom,ldo = <&ldo7>;
  5406. + next-level-cache = <&L2_1>;
  5407. + L1_itlb_103: l1-itlb {
  5408. + qcom,dump-size = <0x400>;
  5409. + };
  5410. + L1_dtlb_103: l1-dtlb {
  5411. + qcom,dump-size = <0x400>;
  5412. + };
  5413. + L1_I_103: l1-icache {
  5414. + compatible = "arm,arch-cache";
  5415. + qcom,dump-size = <0xd840>;
  5416. + };
  5417. + L1_D_103: l1-dcache {
  5418. + compatible = "arm,arch-cache";
  5419. + qcom,dump-size = <0x9040>;
  5420. + };
  5421. + };
  5422. + };
  5423. +
  5424. + soc: soc { };
  5425. +
  5426. + memory {
  5427. + #address-cells = <2>;
  5428. + #size-cells = <2>;
  5429. +
  5430. + secure_mem: secure_region@0 {
  5431. + linux,reserve-contiguous-region;
  5432. + reg = <0 0 0 0x12c00000>;
  5433. + label = "secure_mem";
  5434. + };
  5435. +
  5436. + adsp_mem: adsp_region@0 {
  5437. + linux,reserve-contiguous-region;
  5438. + reg = <0 0 0 0x3F00000>;
  5439. + label = "adsp_mem";
  5440. + };
  5441. +
  5442. + qsecom_mem: qsecom_region@0 {
  5443. + linux,reserve-contiguous-region;
  5444. reg = <0 0 0 0x1800000>;
  5445. + label = "qseecom_mem";
  5446. + };
  5447. +
  5448. + audio_mem: audio_region@0 {
  5449. + linux,reserve-contiguous-region;
  5450. + linux,reserve-region;
  5451. + reg = <0 0 0 0x614000>;
  5452. + label = "audio_mem";
  5453. + };
  5454. +
  5455. + removed_regions: removed_regions@0 {
  5456. + linux,reserve-contiguous-region;
  5457. + linux,reserve-region;
  5458. + linux,remove-completely;
  5459. + reg = <0 0x06300000 0 0xD00000>;
  5460. + label = "memory_hole";
  5461. + };
  5462. + /*#ifdef VENDOR_EDIT*/
  5463. + nvbackup_regions: nvbackup_regions@0 {
  5464. + linux,reserve-contiguous-region;
  5465. + oem,reserve-region;
  5466. + reg = <0 0x06200000 0 0x100000>;
  5467. + label = "memory_nvbackup";
  5468. + };
  5469. + /*#endif VENDOR_EDIT*/
  5470. + dfps_data_mem: dfps_data_mem@0 {
  5471. + linux,reserve-contiguous-region;
  5472. + linux,reserve-region;
  5473. + reg = <0 0x03400000 0 0x1000>;
  5474. + label = "dfps_data_mem";
  5475. + };
  5476. + cont_splash_mem: cont_splash_mem@0 {
  5477. + linux,reserve-contiguous-region;
  5478. + linux,reserve-region;
  5479. + reg = <0 0x03401000 0 0x2200000>;
  5480. + label = "cont_splash_mem";
  5481. + };
  5482. +
  5483. + peripheral_mem: peripheral_region@0 {
  5484. + linux,reserve-contiguous-region;
  5485. + linux,reserve-region;
  5486. + linux,remove-completely;
  5487. + reg = <0 0x0ca00000 0 0x1f00000>;
  5488. + label = "peripheral_mem";
  5489. + };
  5490. +/*#ifdef VENDOR_EDIT //changhua.li add for enlarge TZ APP memory to 25M*/
  5491. + tzapp_mem: tzapp_region@0 {
  5492. +
  5493. + linux,reserve-contiguous-region;
  5494. +
  5495. + linux,reserve-region;
  5496. +
  5497. + linux,remove-completely;
  5498. +
  5499. + reg = <0 0x0E900000 0 0x1900000>;
  5500. +
  5501. + label = "tzapp_mem";
  5502. +
  5503. + };
  5504. +/*#endif VENDOR_EDIT*/
  5505. +
  5506. +
  5507. + modem_mem: modem_region@0 {
  5508. + linux,reserve-contiguous-region;
  5509. + linux,reserve-region;
  5510. + linux,remove-completely;
  5511. + reg = <0 0x07000000 0 0x5a00000>;
  5512. + label = "modem_mem";
  5513. + };
  5514. +
  5515. +/* #ifdef VENDOR_EDIT // add by xcb for ramoops 2015-03-31 */
  5516. + ramoops_mem: ramoops_region@0 {
  5517. + linux,reserve-contiguous-region;
  5518. + oem,reserve-region;//modify by jiachenghui for ramoops reserve region
  5519. + //linux,remove-completely;//del by jiachenghui for ramoops reserve region
  5520. + reg = <0 0xac000000 0 0x00100000>;//modify from 0x05800000 to 0xac000000 by jiachenghui for ramoops reserve region
  5521. + label = "ramoops_mem";
  5522. + };
  5523. +/* #endif VENDOR_EDIT */
  5524. +
  5525. + param_mem: param_region@0 {
  5526. + linux,reserve-contiguous-region;
  5527. + oem,reserve-region;
  5528. + //linux,remove-completely;
  5529. + reg = <0 0xac200000 0 0x00100000>;
  5530. + label = "param_mem";
  5531. + };
  5532. + mtp_regions: mtp_regions@0 {
  5533. + linux,reserve-contiguous-region;
  5534. + oem,reserve-region;
  5535. + reg = <0 0xAC400000 0 0x00100000>;
  5536. + label = "memory_mtp";
  5537. + };
  5538. + };
  5539. +};
  5540. +
  5541. +#include "msm-gdsc.dtsi"
  5542. +#include "msm8994-smp2p.dtsi"
  5543. +#include "msm8994-ipcrouter.dtsi"
  5544. +#include "msm8994-mdss.dtsi"
  5545. +#include "msm8994-mdss-pll.dtsi"
  5546. +#include "msm8994-bus.dtsi"
  5547. +
  5548. +&soc {
  5549. + #address-cells = <1>;
  5550. + #size-cells = <1>;
  5551. + ranges = <0 0 0 0xffffffff>;
  5552. + compatible = "simple-bus";
  5553. +
  5554. + cpuss@fd4a8000 {
  5555. + compatible = "qcom,cpuss-8994";
  5556. + reg = <0xfd4a8000 0x4>;
  5557. + };
  5558. +
  5559. + acc0:clock-controller@f908b004 {
  5560. + compatible = "qcom,arm-cortex-acc";
  5561. + reg = <0xf9070000 0x1000>,
  5562. + <0xf908b000 0x1000>,
  5563. + <0xf900b000 0x1000>;
  5564. + };
  5565. +
  5566. + acc1:clock-controller@f909b004 {
  5567. + compatible = "qcom,arm-cortex-acc";
  5568. + reg = <0xf9071000 0x1000>,
  5569. + <0xf909b000 0x1000>,
  5570. + <0xf900b000 0x1000>;
  5571. + };
  5572. +
  5573. + acc2:clock-controller@f90ab004 {
  5574. + compatible = "qcom,arm-cortex-acc";
  5575. + reg = <0xf9072000 0x1000>,
  5576. + <0xf90ab000 0x1000>,
  5577. + <0xf900b000 0x1000>;
  5578. + };
  5579. +
  5580. + acc3:clock-controller@f90bb004 {
  5581. + compatible = "qcom,arm-cortex-acc";
  5582. + reg = <0xf9073000 0x1000>,
  5583. + <0xf90bb000 0x1000>,
  5584. + <0xf900b000 0x1000>;
  5585. + };
  5586. +
  5587. + acc4:clock-controller@f90cb004 {
  5588. + compatible = "qcom,arm-cortex-acc";
  5589. + reg = <0xf9074000 0x1000>,
  5590. + <0xf90cb000 0x1000>,
  5591. + <0xf900b000 0x1000>;
  5592. + };
  5593. +
  5594. + acc5:clock-controller@f90db004 {
  5595. + compatible = "qcom,arm-cortex-acc";
  5596. + reg = <0xf9075000 0x1000>,
  5597. + <0xf90db000 0x1000>,
  5598. + <0xf900b000 0x1000>;
  5599. + };
  5600. +
  5601. + acc6:clock-controller@f90eb004 {
  5602. + compatible = "qcom,arm-cortex-acc";
  5603. + reg = <0xf9076000 0x1000>,
  5604. + <0xf90eb000 0x1000>,
  5605. + <0xf900b000 0x1000>;
  5606. + };
  5607. +
  5608. + acc7:clock-controller@f90fb004 {
  5609. + compatible = "qcom,arm-cortex-acc";
  5610. + reg = <0xf9077000 0x1000>,
  5611. + <0xf90fb000 0x1000>,
  5612. + <0xf900b000 0x1000>;
  5613. + };
  5614. +
  5615. + ldo0:ldo-vref@f9070000 {
  5616. + compatible = "qcom,8994-cpu-ldo-vref";
  5617. + reg = <0xf9070000 0x30>;
  5618. + qcom,ldo-vref-ret = <0x2a>;
  5619. + };
  5620. +
  5621. + ldo1:ldo-vref@f9071000 {
  5622. + compatible = "qcom,8994-cpu-ldo-vref";
  5623. + reg = <0xf9071000 0x30>;
  5624. + qcom,ldo-vref-ret = <0x2a>;
  5625. + };
  5626. +
  5627. + ldo2:ldo-vref@f9072000 {
  5628. + compatible = "qcom,8994-cpu-ldo-vref";
  5629. + reg = <0xf9072000 0x30>;
  5630. + qcom,ldo-vref-ret = <0x2a>;
  5631. + };
  5632. +
  5633. + ldo3:ldo-vref@f9073000 {
  5634. + compatible = "qcom,8994-cpu-ldo-vref";
  5635. + reg = <0xf9073000 0x30>;
  5636. + qcom,ldo-vref-ret = <0x2a>;
  5637. + };
  5638. +
  5639. + ldo4:ldo-vref@f9074000 {
  5640. + compatible = "qcom,8994-cpu-ldo-vref";
  5641. + reg = <0xf9074000 0x30>;
  5642. + qcom,ldo-vref-ret = <0x3e>;
  5643. + };
  5644. +
  5645. + ldo5:ldo-vref@f9075000 {
  5646. + compatible = "qcom,8994-cpu-ldo-vref";
  5647. + reg = <0xf9075000 0x30>;
  5648. + qcom,ldo-vref-ret = <0x3e>;
  5649. + };
  5650. +
  5651. + ldo6:ldo-vref@f9076000 {
  5652. + compatible = "qcom,8994-cpu-ldo-vref";
  5653. + reg = <0xf9076000 0x30>;
  5654. + qcom,ldo-vref-ret = <0x3e>;
  5655. + };
  5656. +
  5657. + ldo7:ldo-vref@f9077000 {
  5658. + compatible = "qcom,8994-cpu-ldo-vref";
  5659. + reg = <0xf9077000 0x30>;
  5660. + qcom,ldo-vref-ret = <0x3e>;
  5661. + };
  5662. +
  5663. + l2ccc_0: clock-controller@f900d000 {
  5664. + compatible = "qcom,8994-l2ccc";
  5665. + reg = <0xf900d000 0x1000>,
  5666. + <0xf911210c 0x4>;
  5667. + qcom,vctl-node = <&cluster0_spm>;
  5668. + };
  5669. +
  5670. + l2ccc_1: clock-controller@f900f000 {
  5671. + compatible = "qcom,8994-l2ccc";
  5672. + reg = <0xf900f000 0x1000>,
  5673. + <0xf911210c 0x4>;
  5674. + qcom,vctl-node = <&cluster1_spm>;
  5675. + qcom,vctl-val = <0xb8>;
  5676. + };
  5677. +
  5678. + intc: interrupt-controller@f9000000 {
  5679. + compatible = "qcom,msm-qgic2";
  5680. + interrupt-controller;
  5681. + #interrupt-cells = <3>;
  5682. + reg = <0xf9000000 0x1000>,
  5683. + <0xf9002000 0x1000>;
  5684. + };
  5685. +
  5686. + timer {
  5687. + compatible = "arm,armv8-timer";
  5688. + interrupts = <1 2 0xff08>,
  5689. + <1 3 0xff08>,
  5690. + <1 4 0xff08>,
  5691. + <1 1 0xff08>;
  5692. + clock-frequency = <19200000>;
  5693. + };
  5694. +
  5695. + qcom,mpm2-sleep-counter@fc4a3000 {
  5696. + compatible = "qcom,mpm2-sleep-counter";
  5697. + reg = <0xfc4a3000 0x1000>;
  5698. + clock-frequency = <32768>;
  5699. + };
  5700. +
  5701. + timer@f9020000 {
  5702. + #address-cells = <1>;
  5703. + #size-cells = <1>;
  5704. + ranges;
  5705. + compatible = "arm,armv7-timer-mem";
  5706. + reg = <0xf9020000 0x1000>;
  5707. + clock-frequency = <19200000>;
  5708. +
  5709. + frame@f9021000 {
  5710. + frame-number = <0>;
  5711. + interrupts = <0 9 0x4>,
  5712. + <0 8 0x4>;
  5713. + reg = <0xf9021000 0x1000>,
  5714. + <0xf9022000 0x1000>;
  5715. + };
  5716. +
  5717. + frame@f9023000 {
  5718. + frame-number = <1>;
  5719. + interrupts = <0 10 0x4>;
  5720. + reg = <0xf9023000 0x1000>;
  5721. + status = "disabled";
  5722. + };
  5723. +
  5724. + frame@f9024000 {
  5725. + frame-number = <2>;
  5726. + interrupts = <0 11 0x4>;
  5727. + reg = <0xf9024000 0x1000>;
  5728. + status = "disabled";
  5729. + };
  5730. +
  5731. + frame@f9025000 {
  5732. + frame-number = <3>;
  5733. + interrupts = <0 12 0x4>;
  5734. + reg = <0xf9025000 0x1000>;
  5735. + status = "disabled";
  5736. + };
  5737. +
  5738. + frame@f9026000 {
  5739. + frame-number = <4>;
  5740. + interrupts = <0 13 0x4>;
  5741. + reg = <0xf9026000 0x1000>;
  5742. + status = "disabled";
  5743. + };
  5744. +
  5745. + frame@f9027000 {
  5746. + frame-number = <5>;
  5747. + interrupts = <0 14 0x4>;
  5748. + reg = <0xf9027000 0x1000>;
  5749. + status = "disabled";
  5750. + };
  5751. +
  5752. + frame@f9028000 {
  5753. + frame-number = <6>;
  5754. + interrupts = <0 15 0x4>;
  5755. + reg = <0xf9028000 0x1000>;
  5756. + status = "disabled";
  5757. + };
  5758. + };
  5759. +
  5760. + restart@fc4ab000 {
  5761. + compatible = "qcom,pshold";
  5762. + reg = <0xfc4ab000 0x4>;
  5763. + };
  5764. +
  5765. + blsp1_uart3: serial@f991f000 {
  5766. + compatible = "qcom,msm-lsuart-v14";
  5767. + reg = <0xf991f000 0x1000>;
  5768. + interrupts = <0 109 0>;
  5769. + status = "disabled";
  5770. + clock-names = "core_clk", "iface_clk";
  5771. + clocks = <&clock_gcc clk_gcc_blsp1_uart3_apps_clk>,
  5772. + <&clock_gcc clk_gcc_blsp1_ahb_clk>;
  5773. + };
  5774. +
  5775. + blsp1_uart2: serial@f991e000 {
  5776. + compatible = "qcom,msm-lsuart-v14";
  5777. + reg = <0xf991e000 0x1000>;
  5778. + interrupts = <0 108 0>;
  5779. + status = "disabled";
  5780. + clock-names = "core_clk", "iface_clk";
  5781. + clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
  5782. + <&clock_gcc clk_gcc_blsp1_ahb_clk>;
  5783. + };
  5784. +
  5785. + blsp2_uart2: uart@f995e000 { /* BLSP2 UART2 */
  5786. + compatible = "qcom,msm-hsuart-v14";
  5787. + reg = <0xf995e000 0x1000>,
  5788. + <0xf9944000 0x19000>;
  5789. + status = "disabled";
  5790. + reg-names = "core_mem", "bam_mem";
  5791. + interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
  5792. + #address-cells = <0>;
  5793. + interrupt-parent = <&blsp2_uart2>;
  5794. + interrupts = <0 1 2>;
  5795. + #interrupt-cells = <1>;
  5796. + interrupt-map-mask = <0xffffffff>;
  5797. + interrupt-map = <0 &intc 0 114 0
  5798. + 1 &intc 0 239 0
  5799. + 2 &msm_gpio 46 0>;
  5800. +
  5801. + qcom,inject-rx-on-wakeup;
  5802. + qcom,rx-char-to-inject = <0xFD>;
  5803. +
  5804. + qcom,bam-tx-ep-pipe-index = <2>;
  5805. + qcom,bam-rx-ep-pipe-index = <3>;
  5806. + qcom,master-id = <84>;
  5807. + clock-names = "core_clk", "iface_clk";
  5808. + clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
  5809. + <&clock_gcc clk_gcc_blsp2_ahb_clk>;
  5810. + pinctrl-names = "sleep", "default";
  5811. + pinctrl-0 = <&hsuart_sleep>;
  5812. + pinctrl-1 = <&hsuart_active>;
  5813. +
  5814. + qcom,msm-bus,name = "buart8";
  5815. + qcom,msm-bus,num-cases = <2>;
  5816. + qcom,msm-bus,num-paths = <1>;
  5817. + qcom,msm-bus,vectors-KBps =
  5818. + <84 512 0 0>,
  5819. + <84 512 500 800>;
  5820. + };
  5821. +
  5822. + qcom,sps@f9984000 {
  5823. + compatible = "qcom,msm_sps";
  5824. + reg-names = "bam_mem", "core_mem";
  5825. + reg = <0xf9984000 0x15000>,
  5826. + <0xf9999000 0xb000>;
  5827. + interrupts = <0 94 0>;
  5828. + qcom,pipe-attr-ee;
  5829. + clocks = <&clock_rpm clk_pnoc_sps_clk>,
  5830. + <&clock_gcc clk_gcc_bam_dma_ahb_clk>;
  5831. + clock-names = "dfab_clk", "dma_bam_pclk";
  5832. + };
  5833. +
  5834. + pcie0: qcom,pcie@fc520000 {
  5835. + compatible = "qcom,pci-msm";
  5836. + cell-index = <0>;
  5837. +
  5838. + reg = <0xfc520000 0x2000>,
  5839. + <0xfc526000 0x1000>,
  5840. + <0xff000000 0xf1d>,
  5841. + <0xff000f20 0xa8>,
  5842. + <0xff100000 0x100000>,
  5843. + <0xff200000 0x100000>,
  5844. + <0xff300000 0xd00000>;
  5845. +
  5846. + reg-names = "parf", "phy", "dm_core", "elbi",
  5847. + "conf", "io", "bars";
  5848. +
  5849. + #address-cells = <0>;
  5850. + interrupt-parent = <&pcie0>;
  5851. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
  5852. + #interrupt-cells = <1>;
  5853. + interrupt-map-mask = <0xffffffff>;
  5854. + interrupt-map = <0 &intc 0 243 0
  5855. + 1 &intc 0 244 0
  5856. + 2 &intc 0 245 0
  5857. + 3 &intc 0 247 0
  5858. + 4 &intc 0 248 0
  5859. + 5 &intc 0 249 0
  5860. + 6 &intc 0 250 0
  5861. + 7 &intc 0 251 0
  5862. + 8 &intc 0 252 0
  5863. + 9 &intc 0 253 0
  5864. + 10 &intc 0 254 0
  5865. + 11 &intc 0 255 0>;
  5866. +
  5867. + interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
  5868. + "int_pls_pme", "int_pme_legacy", "int_pls_err",
  5869. + "int_aer_legacy", "int_pls_link_up",
  5870. + "int_pls_link_down", "int_bridge_flush_n";
  5871. +
  5872. + pinctrl-names = "default";
  5873. + pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
  5874. +
  5875. + perst-gpio = <&msm_gpio 53 0>;
  5876. + wake-gpio = <&msm_gpio 55 0>;
  5877. +
  5878. + gdsc-vdd-supply = <&gdsc_pcie_0>;
  5879. + vreg-1.8-supply = <&pm8994_l12>;
  5880. + vreg-0.9-supply = <&pm8994_l28>;
  5881. +
  5882. + qcom,ep-latency = <10>;
  5883. +
  5884. + qcom,msi-gicm-addr = <0xf9006040>;
  5885. + qcom,msi-gicm-base = <0x180>;
  5886. +
  5887. + qcom,msm-bus,name = "pcie0";
  5888. + qcom,msm-bus,num-cases = <2>;
  5889. + qcom,msm-bus,num-paths = <1>;
  5890. + qcom,msm-bus,vectors-KBps =
  5891. + <45 512 0 0>,
  5892. + <45 512 500 800>;
  5893. +
  5894. + qcom,scm-dev-id = <11>;
  5895. +
  5896. + clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
  5897. + <&clock_rpm clk_ln_bb_clk>,
  5898. + <&clock_gcc clk_gcc_pcie_0_aux_clk>,
  5899. + <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
  5900. + <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
  5901. + <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
  5902. + <&clock_gcc clk_pcie_0_phy_ldo>,
  5903. + <&clock_gcc clk_gcc_pcie_phy_0_reset>;
  5904. +
  5905. + clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk",
  5906. + "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",
  5907. + "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_phy_reset";
  5908. +
  5909. + max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;
  5910. + };
  5911. +
  5912. + pcie1: qcom,pcie@fc528000 {
  5913. + compatible = "qcom,pci-msm";
  5914. + cell-index = <1>;
  5915. +
  5916. + reg = <0xfc528000 0x2000>,
  5917. + <0xfc52e000 0x1000>,
  5918. + <0xf8800000 0xf1d>,
  5919. + <0xf8800F20 0xa8>,
  5920. + <0xf8801000 0x7f000>,
  5921. + <0xf8880000 0x80000>,
  5922. + <0xf8900000 0x700000>;
  5923. +
  5924. + reg-names = "parf", "phy", "dm_core", "elbi",
  5925. + "conf", "io", "bars";
  5926. +
  5927. + #address-cells = <0>;
  5928. + interrupt-parent = <&pcie1>;
  5929. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
  5930. + #interrupt-cells = <1>;
  5931. + interrupt-map-mask = <0xffffffff>;
  5932. + interrupt-map = <0 &intc 0 271 0
  5933. + 1 &intc 0 272 0
  5934. + 2 &intc 0 273 0
  5935. + 3 &intc 0 274 0
  5936. + 4 &intc 0 275 0
  5937. + 5 &intc 0 276 0
  5938. + 6 &intc 0 277 0
  5939. + 7 &intc 0 278 0
  5940. + 8 &intc 0 279 0
  5941. + 9 &intc 0 280 0
  5942. + 10 &intc 0 281 0
  5943. + 11 &intc 0 282 0>;
  5944. +
  5945. + interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
  5946. + "int_pls_pme", "int_pme_legacy", "int_pls_err",
  5947. + "int_aer_legacy", "int_pls_link_up",
  5948. + "int_pls_link_down", "int_bridge_flush_n";
  5949. +
  5950. + pinctrl-names = "default", "sleep";
  5951. + pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
  5952. + pinctrl-1 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_sleep>;
  5953. +
  5954. + perst-gpio = <&msm_gpio 35 0>;
  5955. + wake-gpio = <&msm_gpio 37 0>;
  5956. +
  5957. + gdsc-vdd-supply = <&gdsc_pcie_1>;
  5958. + vreg-1.8-supply = <&pm8994_l12>;
  5959. + vreg-0.9-supply = <&pm8994_l28>;
  5960. +
  5961. + qcom,l1-supported;
  5962. + qcom,l1ss-supported;
  5963. + qcom,aux-clk-sync;
  5964. +
  5965. + qcom,ep-latency = <10>;
  5966. +
  5967. + qcom,msi-gicm-addr = <0xf9007040>;
  5968. + qcom,msi-gicm-base = <0x1a0>;
  5969. +
  5970. + qcom,ep-wakeirq;
  5971. +
  5972. + qcom,msm-bus,name = "pcie1";
  5973. + qcom,msm-bus,num-cases = <2>;
  5974. + qcom,msm-bus,num-paths = <1>;
  5975. + qcom,msm-bus,vectors-KBps =
  5976. + <100 512 0 0>,
  5977. + <100 512 500 800>;
  5978. +
  5979. + qcom,scm-dev-id = <12>;
  5980. +
  5981. + clocks = <&clock_gcc clk_gcc_pcie_1_pipe_clk>,
  5982. + <&clock_rpm clk_ln_bb_clk>,
  5983. + <&clock_gcc clk_gcc_pcie_1_aux_clk>,
  5984. + <&clock_gcc clk_gcc_pcie_1_cfg_ahb_clk>,
  5985. + <&clock_gcc clk_gcc_pcie_1_mstr_axi_clk>,
  5986. + <&clock_gcc clk_gcc_pcie_1_slv_axi_clk>,
  5987. + <&clock_gcc clk_pcie_1_phy_ldo>,
  5988. + <&clock_gcc clk_gcc_pcie_phy_1_reset>;
  5989. +
  5990. + clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk",
  5991. + "pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk",
  5992. + "pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_phy_reset";
  5993. +
  5994. + max-clock-frequency-hz = <125000000>, <0>, <1011000>, <0>, <0>, <0>, <0>, <0>;
  5995. + };
  5996. +
  5997. + ipa_hw: qcom,ipa@fd4c0000 {
  5998. + compatible = "qcom,ipa";
  5999. + reg = <0xfd4c0000 0x29000>,
  6000. + <0xfd4c4000 0x15820>;
  6001. + reg-names = "ipa-base", "bam-base";
  6002. + interrupts = <0 301 0>,
  6003. + <0 300 0>;
  6004. + interrupt-names = "ipa-irq", "bam-irq";
  6005. + qcom,ipa-hw-ver = <3>; /* IPA core version = IPAv2.0 */
  6006. + qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
  6007. + qcom,wan-rx-ring-size = <192>;
  6008. + qcom,ee = <2>;
  6009. + clock-names = "core_clk";
  6010. + clocks = <&clock_rpm clk_ipa_clk>;
  6011. + qcom,msm-bus,name = "ipa";
  6012. + qcom,msm-bus,num-cases = <3>;
  6013. + qcom,msm-bus,num-paths = <2>;
  6014. + qcom,msm-bus,vectors-KBps =
  6015. + <90 512 0 0>, <90 585 0 0>, /* No vote */
  6016. + <90 512 100000 800000>, <90 585 100000 800000>, /* SVS */
  6017. + <90 512 100000 1200000>, <90 585 100000 1200000>; /* PERF */
  6018. + qcom,bus-vector-names = "MIN", "SVS", "PERF";
  6019. +
  6020. + };
  6021. +
  6022. + qcom,rmnet-ipa {
  6023. + compatible = "qcom,rmnet-ipa";
  6024. + qcom,rmnet-ipa-ssr;
  6025. + qcom,ipa-loaduC;
  6026. + };
  6027. +
  6028. + qcom,ipc-spinlock@fd484000 {
  6029. + compatible = "qcom,ipc-spinlock-sfpb";
  6030. + reg = <0xfd484000 0x400>;
  6031. + qcom,num-locks = <8>;
  6032. + };
  6033. +
  6034. + qcom,smem@6a00000 {
  6035. + compatible = "qcom,smem";
  6036. + reg = <0x6a00000 0x200000>,
  6037. + <0xf900d008 0x4>,
  6038. + <0xfc428000 0x4000>;
  6039. + reg-names = "smem", "irq-reg-base", "aux-mem1";
  6040. + qcom,mpu-enabled;
  6041. +
  6042. + qcom,smd-modem {
  6043. + compatible = "qcom,smd";
  6044. + qcom,smd-edge = <0>;
  6045. + qcom,smd-irq-offset = <0x0>;
  6046. + qcom,smd-irq-bitmask = <0x1000>;
  6047. + interrupts = <0 25 1>;
  6048. + label = "modem";
  6049. + qcom,not-loadable;
  6050. + };
  6051. +
  6052. + qcom,smsm-modem {
  6053. + compatible = "qcom,smsm";
  6054. + qcom,smsm-edge = <0>;
  6055. + qcom,smsm-irq-offset = <0x0>;
  6056. + qcom,smsm-irq-bitmask = <0x2000>;
  6057. + interrupts = <0 26 1>;
  6058. + };
  6059. +
  6060. + qcom,smd-adsp {
  6061. + compatible = "qcom,smd";
  6062. + qcom,smd-edge = <1>;
  6063. + qcom,smd-irq-offset = <0x0>;
  6064. + qcom,smd-irq-bitmask = <0x100>;
  6065. + interrupts = <0 156 1>;
  6066. + label = "adsp";
  6067. + };
  6068. +
  6069. + qcom,smsm-adsp {
  6070. + compatible = "qcom,smsm";
  6071. + qcom,smsm-edge = <1>;
  6072. + qcom,smsm-irq-offset = <0x0>;
  6073. + qcom,smsm-irq-bitmask = <0x200>;
  6074. + interrupts = <0 157 1>;
  6075. + };
  6076. +
  6077. + qcom,smd-rpm {
  6078. + compatible = "qcom,smd";
  6079. + qcom,smd-edge = <15>;
  6080. + qcom,smd-irq-offset = <0x0>;
  6081. + qcom,smd-irq-bitmask = <0x1>;
  6082. + interrupts = <0 168 1>;
  6083. + label = "rpm";
  6084. + qcom,irq-no-suspend;
  6085. + qcom,not-loadable;
  6086. + };
  6087. + };
  6088. +
  6089. + qcom,msm-imem@fe87f000 {
  6090. + compatible = "qcom,msm-imem";
  6091. + reg = <0xfe87f000 0x1000>; /* Address and size of IMEM */
  6092. + ranges = <0x0 0xfe87f000 0x1000>;
  6093. + #address-cells = <1>;
  6094. + #size-cells = <1>;
  6095. +
  6096. + download_mode@0 {
  6097. + compatible = "qcom,msm-imem-download_mode";
  6098. + reg = <0x0 8>;
  6099. + };
  6100. +
  6101. + mem_dump_table@10 {
  6102. + compatible = "qcom,msm-imem-mem_dump_table";
  6103. + reg = <0x10 8>;
  6104. + };
  6105. +
  6106. + restart_reason@65c {
  6107. + compatible = "qcom,msm-imem-restart_reason";
  6108. + reg = <0x65c 4>;
  6109. + };
  6110. +
  6111. + boot_stats@6b0 {
  6112. + compatible = "qcom,msm-imem-boot_stats";
  6113. + reg = <0x6b0 32>;
  6114. + };
  6115. +
  6116. + pil@94c {
  6117. + compatible = "qcom,msm-imem-pil";
  6118. + reg = <0x94c 200>;
  6119. + };
  6120. +
  6121. + emergency_download_mode@fe0 {
  6122. + compatible = "qcom,msm-imem-emergency_download_mode";
  6123. + reg = <0xfe0 12>;
  6124. + };
  6125. + };
  6126. +
  6127. + qcom,wdt@f9017000 {
  6128. + compatible = "qcom,msm-watchdog";
  6129. + reg = <0xf9017000 0x1000>;
  6130. + reg-names = "wdt-base";
  6131. + interrupts = <0 3 0>, <0 4 0>;
  6132. +//liyunbing@BSP, 2015/05/21, WDT bark-time too short cause some task timeout
  6133. + #qcom,bark-time = <11000>;
  6134. + qcom,bark-time = <15000>;
  6135. + qcom,pet-time = <10000>;
  6136. + qcom,ipi-ping;
  6137. + };
  6138. +
  6139. + qcom,msm-rtb {
  6140. + compatible = "qcom,msm-rtb";
  6141. + qcom,rtb-size = <0x100000>;
  6142. + };
  6143. +
  6144. + jtag_fuse: jtagfuse@fc4be024 {
  6145. + compatible = "qcom,jtag-fuse";
  6146. + reg = <0xfc4be024 0x8>;
  6147. + reg-names = "fuse-base";
  6148. + };
  6149. +
  6150. + jtag_mm0: jtagmm@fb840000 {
  6151. + compatible = "qcom,jtagv8-mm";
  6152. + reg = <0xfb840000 0x1000>,
  6153. + <0xfb810000 0x1000>;
  6154. + reg-names = "etm-base","debug-base";
  6155. +
  6156. + clocks = <&clock_rpm clk_qdss_clk>,
  6157. + <&clock_rpm clk_qdss_a_clk>;
  6158. + clock-names = "core_clk", "core_a_clk";
  6159. +
  6160. + qcom,coresight-jtagmm-cpu = <&CPU0>;
  6161. + };
  6162. +
  6163. + jtag_mm1: jtagmm@fb940000 {
  6164. + compatible = "qcom,jtagv8-mm";
  6165. + reg = <0xfb940000 0x1000>,
  6166. + <0xfb910000 0x1000>;
  6167. + reg-names = "etm-base","debug-base";
  6168. +
  6169. + clocks = <&clock_rpm clk_qdss_clk>,
  6170. + <&clock_rpm clk_qdss_a_clk>;
  6171. + clock-names = "core_clk", "core_a_clk";
  6172. +
  6173. + qcom,coresight-jtagmm-cpu = <&CPU1>;
  6174. + };
  6175. +
  6176. + jtag_mm2: jtagmm@fba40000 {
  6177. + compatible = "qcom,jtagv8-mm";
  6178. + reg = <0xfba40000 0x1000>,
  6179. + <0xfba10000 0x1000>;
  6180. + reg-names = "etm-base","debug-base";
  6181. +
  6182. + clocks = <&clock_rpm clk_qdss_clk>,
  6183. + <&clock_rpm clk_qdss_a_clk>;
  6184. + clock-names = "core_clk", "core_a_clk";
  6185. +
  6186. + qcom,coresight-jtagmm-cpu = <&CPU2>;
  6187. + };
  6188. +
  6189. + jtag_mm3: jtagmm@fbb40000 {
  6190. + compatible = "qcom,jtagv8-mm";
  6191. + reg = <0xfbb40000 0x1000>,
  6192. + <0xfbb10000 0x1000>;
  6193. + reg-names = "etm-base","debug-base";
  6194. +
  6195. + clocks = <&clock_rpm clk_qdss_clk>,
  6196. + <&clock_rpm clk_qdss_a_clk>;
  6197. + clock-names = "core_clk", "core_a_clk";
  6198. +
  6199. + qcom,coresight-jtagmm-cpu = <&CPU3>;
  6200. + };
  6201. +
  6202. + jtag_mm4: jtagmm@fbc40000 {
  6203. + compatible = "qcom,jtagv8-mm";
  6204. + reg = <0xfbc40000 0x1000>,
  6205. + <0xfbc10000 0x1000>;
  6206. + reg-names = "etm-base","debug-base";
  6207. +
  6208. + clocks = <&clock_rpm clk_qdss_clk>,
  6209. + <&clock_rpm clk_qdss_a_clk>;
  6210. + clock-names = "core_clk", "core_a_clk";
  6211. +
  6212. + qcom,coresight-jtagmm-cpu = <&CPU4>;
  6213. + };
  6214. +
  6215. + jtag_mm5: jtagmm@fbd40000 {
  6216. + compatible = "qcom,jtagv8-mm";
  6217. + reg = <0xfbd40000 0x1000>,
  6218. + <0xfbd10000 0x1000>;
  6219. + reg-names = "etm-base","debug-base";
  6220. +
  6221. + clocks = <&clock_rpm clk_qdss_clk>,
  6222. + <&clock_rpm clk_qdss_a_clk>;
  6223. + clock-names = "core_clk", "core_a_clk";
  6224. +
  6225. + qcom,coresight-jtagmm-cpu = <&CPU5>;
  6226. + };
  6227. +
  6228. + jtag_mm6: jtagmm@fbe40000 {
  6229. + compatible = "qcom,jtagv8-mm";
  6230. + reg = <0xfbe40000 0x1000>,
  6231. + <0xfbe10000 0x1000>;
  6232. + reg-names = "etm-base","debug-base";
  6233. +
  6234. + clocks = <&clock_rpm clk_qdss_clk>,
  6235. + <&clock_rpm clk_qdss_a_clk>;
  6236. + clock-names = "core_clk", "core_a_clk";
  6237. +
  6238. + qcom,coresight-jtagmm-cpu = <&CPU6>;
  6239. + };
  6240. +
  6241. + jtag_mm7: jtagmm@fbf40000 {
  6242. + compatible = "qcom,jtagv8-mm";
  6243. + reg = <0xfbf40000 0x1000>,
  6244. + <0xfbf10000 0x1000>;
  6245. + reg-names = "etm-base","debug-base";
  6246. +
  6247. + clocks = <&clock_rpm clk_qdss_clk>,
  6248. + <&clock_rpm clk_qdss_a_clk>;
  6249. + clock-names = "core_clk", "core_a_clk";
  6250. +
  6251. + qcom,coresight-jtagmm-cpu = <&CPU7>;
  6252. + };
  6253. +
  6254. + rpm_bus: qcom,rpm-smd {
  6255. + compatible = "qcom,rpm-smd";
  6256. + rpm-channel-name = "rpm_requests";
  6257. + rpm-channel-type = <15>; /* SMD_APPS_RPM */
  6258. + };
  6259. +
  6260. + qcom,msm-rng@f9bff000 {
  6261. + compatible = "qcom,msm-rng";
  6262. + reg = <0xf9bff000 0x200>;
  6263. + qcom,msm-bus,name = "msm-rng-noc";
  6264. + qcom,msm-bus,num-cases = <2>;
  6265. + qcom,msm-bus,num-paths = <1>;
  6266. + qcom,msm-bus,vectors-KBps =
  6267. + <88 618 0 0>,
  6268. + <88 618 0 800>;
  6269. + qcom,msm-rng-iface-clk;
  6270. + clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
  6271. + clock-names = "iface_clk";
  6272. + };
  6273. +
  6274. + qcom,rmtfs_sharedmem@00000000 {
  6275. + compatible = "qcom,sharedmem-uio";
  6276. + reg = <0x00000000 0x00180000>;
  6277. + reg-names = "rmtfs";
  6278. + qcom,client-id = <0x00000001>;
  6279. + };
  6280. +
  6281. + qcom,dsp_sharedmem@00000000 {
  6282. + compatible = "qcom,sharedmem-uio";
  6283. + reg = <0x00000000 0x00010000>;
  6284. + reg-names = "rfsa_dsp";
  6285. + qcom,client-id = <0x011013ec>;
  6286. + linux,contiguous-region = <&adsp_mem>;
  6287. + };
  6288. +
  6289. + qcom,mdm_sharedmem@00000000 {
  6290. + compatible = "qcom,sharedmem-uio";
  6291. + reg = <0x00000000 0x00010000>;
  6292. + reg-names = "rfsa_mdm";
  6293. + qcom,client-id = <0x011013ed>;
  6294. + };
  6295. +
  6296. + qcom,sensors_sharedmem@00000000 {
  6297. + compatible = "qcom,sharedmem-uio";
  6298. + reg = <0x00000000 0x00010000>;
  6299. + reg-names = "rfsa_sensor";
  6300. + qcom,client-id = <0x011013ee>;
  6301. + linux,contiguous-region = <&adsp_mem>;
  6302. + };
  6303. +
  6304. + qcom,nvbackup_sharedmem@00000000 {
  6305. + compatible = "qcom,sharedmem-uio";
  6306. + reg = <0x06200000 0x001000000>;
  6307. + reg-names = "nvbackup";
  6308. + qcom,client-id = <0x00000001>;
  6309. + linux,contiguous-region = <&nvbackup_regions>;
  6310. + };
  6311. +
  6312. + sdhc_1: sdhci@f9824900 {
  6313. + compatible = "qcom,sdhci-msm";
  6314. + reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
  6315. + reg-names = "hc_mem", "core_mem";
  6316. +
  6317. + interrupts = <0 123 0>, <0 138 0>;
  6318. + interrupt-names = "hc_irq", "pwr_irq";
  6319. +
  6320. + qcom,bus-width = <8>;
  6321. + qcom,cpu-dma-latency-us = <301 70>;
  6322. + qcom,cpu-affinity = "affine_cores";
  6323. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  6324. + qcom,wakeup-on-idle;
  6325. +
  6326. + qcom,msm-bus,name = "sdhc1";
  6327. + qcom,msm-bus,num-cases = <9>;
  6328. + qcom,msm-bus,num-paths = <1>;
  6329. + qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
  6330. + <78 512 1600 3200>, /* 400 KB/s*/
  6331. + <78 512 80000 160000>, /* 20 MB/s */
  6332. + <78 512 100000 200000>, /* 25 MB/s */
  6333. + <78 512 200000 400000>, /* 50 MB/s */
  6334. + <78 512 400000 800000>, /* 100 MB/s */
  6335. + <78 512 400000 800000>, /* 200 MB/s */
  6336. + <78 512 400000 800000>, /* 400 MB/s */
  6337. + <78 512 2048000 4096000>; /* Max. bandwidth */
  6338. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  6339. + 100000000 200000000 400000000 4294967295>;
  6340. +
  6341. + clock-names = "iface_clk", "core_clk";
  6342. + clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
  6343. + <&clock_gcc clk_gcc_sdcc1_apps_clk>;
  6344. +
  6345. + status = "disabled";
  6346. + };
  6347. +
  6348. + sdhc_2: sdhci@f98a4900 {
  6349. + compatible = "qcom,sdhci-msm";
  6350. + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
  6351. + reg-names = "hc_mem", "core_mem";
  6352. +
  6353. + interrupts = <0 125 0>, <0 221 0>;
  6354. + interrupt-names = "hc_irq", "pwr_irq";
  6355. +
  6356. + clock-names = "iface_clk", "core_clk";
  6357. + clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
  6358. + <&clock_gcc clk_gcc_sdcc2_apps_clk>;
  6359. +
  6360. + qcom,bus-width = <4>;
  6361. + qcom,cpu-dma-latency-us = <301 70>;
  6362. + qcom,cpu-affinity = "affine_cores";
  6363. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  6364. + qcom,wakeup-on-idle;
  6365. +
  6366. + qcom,msm-bus,name = "sdhc2";
  6367. + qcom,msm-bus,num-cases = <8>;
  6368. + qcom,msm-bus,num-paths = <1>;
  6369. + qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
  6370. + <81 512 1600 3200>, /* 400 KB/s*/
  6371. + <81 512 80000 160000>, /* 20 MB/s */
  6372. + <81 512 100000 200000>, /* 25 MB/s */
  6373. + <81 512 200000 400000>, /* 50 MB/s */
  6374. + <81 512 400000 800000>, /* 100 MB/s */
  6375. + <81 512 800000 800000>, /* 200 MB/s */
  6376. + <81 512 2048000 4096000>; /* Max. bandwidth */
  6377. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  6378. + 100000000 200000000 4294967295>;
  6379. +
  6380. + status = "disabled";
  6381. + };
  6382. +
  6383. + sdhc_3: sdhci@f9864900 {
  6384. + compatible = "qcom,sdhci-msm";
  6385. + reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
  6386. + reg-names = "hc_mem", "core_mem";
  6387. +
  6388. + interrupts = <0 127 0>, <0 224 0>;
  6389. + interrupt-names = "hc_irq", "pwr_irq";
  6390. +
  6391. + clock-names = "iface_clk", "core_clk";
  6392. + clocks = <&clock_gcc clk_gcc_sdcc3_ahb_clk>,
  6393. + <&clock_gcc clk_gcc_sdcc3_apps_clk>;
  6394. +
  6395. + qcom,bus-width = <4>;
  6396. + qcom,cpu-dma-latency-us = <301 70>;
  6397. + qcom,cpu-affinity = "affine_cores";
  6398. + qcom,cpu-affinity-mask = <0x0f 0xf0>;
  6399. + qcom,wakeup-on-idle;
  6400. +
  6401. + qcom,msm-bus,name = "sdhc3";
  6402. + qcom,msm-bus,num-cases = <8>;
  6403. + qcom,msm-bus,num-paths = <1>;
  6404. + qcom,msm-bus,vectors-KBps = <79 512 0 0>, /* No vote */
  6405. + <79 512 1600 3200>, /* 400 KB/s*/
  6406. + <79 512 80000 160000>, /* 20 MB/s */
  6407. + <79 512 100000 200000>, /* 25 MB/s */
  6408. + <79 512 200000 400000>, /* 50 MB/s */
  6409. + <79 512 400000 800000>, /* 100 MB/s */
  6410. + <79 512 800000 800000>, /* 200 MB/s */
  6411. + <79 512 2048000 4096000>; /* Max. bandwidth */
  6412. + qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
  6413. + 100000000 200000000 4294967295>;
  6414. + qcom,dat1-mpm-int = <47>;
  6415. + status = "disabled";
  6416. + };
  6417. +
  6418. + ufs_ice: ufsice@fc5a0000 {
  6419. + compatible = "qcom,ice";
  6420. + reg = <0xfc5a0000 0x8000>;
  6421. + interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq";
  6422. + interrupts = <0 258 0>, <0 257 0>;
  6423. + status = "disabled";
  6424. + };
  6425. +
  6426. + ufsphy1: ufsphy@fc597000 {
  6427. + compatible = "qcom,ufs-phy-qmp-20nm";
  6428. + reg = <0xfc597000 0xda8>;
  6429. + reg-names = "phy_mem";
  6430. + #phy-cells = <0>;
  6431. + vdda-phy-supply = <&pm8994_l28>;
  6432. + vdda-pll-supply = <&pm8994_l12>;
  6433. + vdda-phy-max-microamp = <45000>;
  6434. + vdda-pll-max-microamp = <100>;
  6435. + vddp-ref-clk-supply = <&pm8994_l31>;
  6436. + vddp-ref-clk-max-microamp = <100>;
  6437. + vddp-ref-clk-always-on;
  6438. + clock-names = "ref_clk_src",
  6439. + "ref_clk",
  6440. + "tx_iface_clk",
  6441. + "rx_iface_clk";
  6442. + clocks = <&clock_rpm clk_ln_bb_clk>,
  6443. + <&clock_gcc clk_ufs_phy_ldo>,
  6444. + <&clock_gcc clk_gcc_ufs_tx_cfg_clk>,
  6445. + <&clock_gcc clk_gcc_ufs_rx_cfg_clk>;
  6446. + status = "disabled";
  6447. + };
  6448. +
  6449. + ufs1: ufshc@fc594000 {
  6450. + compatible = "qcom,ufshc";
  6451. + reg = <0xfc594000 0x2500>, <0xfd512074 0x4>;
  6452. + interrupts = <0 265 0>;
  6453. + phys = <&ufsphy1>;
  6454. + phy-names = "ufsphy";
  6455. + ufs-qcom-crypto = <&ufs_ice>;
  6456. + vdd-hba-supply = <&gdsc_ufs>;
  6457. + vdd-hba-fixed-regulator;
  6458. + vcc-supply = <&pm8994_l20>;
  6459. + vccq-supply = <&pm8994_l31>;
  6460. + vccq2-supply = <&pm8994_s4>;
  6461. + vcc-max-microamp = <750000>;
  6462. + vccq-max-microamp = <50000>;
  6463. + vccq2-max-microamp = <750000>;
  6464. +
  6465. + clock-names = "core_clk_src", "core_clk", "bus_clk", "iface_clk",
  6466. + "ref_clk", "rx_lane0_sync_clk", "tx_lane0_sync_clk",
  6467. + "rx_lane1_sync_clk", "tx_lane1_sync_clk";
  6468. + clocks =
  6469. + <&clock_gcc clk_ufs_axi_clk_src>,
  6470. + <&clock_gcc clk_gcc_ufs_axi_clk>,
  6471. + <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
  6472. + <&clock_gcc clk_gcc_ufs_ahb_clk>,
  6473. + <&clock_rpm clk_bb_clk1>,
  6474. + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>,
  6475. + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
  6476. + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>,
  6477. + <&clock_gcc clk_gcc_ufs_tx_symbol_1_clk>;
  6478. + qcom,msm-bus,name = "ufs1";
  6479. + qcom,msm-bus,num-cases = <22>;
  6480. + qcom,msm-bus,num-paths = <2>;
  6481. + qcom,msm-bus,vectors-KBps =
  6482. + <95 512 0 0>, <1 650 0 0>, /* No vote */
  6483. + <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
  6484. + <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
  6485. + <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
  6486. + <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
  6487. + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */
  6488. + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */
  6489. + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */
  6490. + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */
  6491. + <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
  6492. + <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
  6493. + <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */
  6494. + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */
  6495. + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */
  6496. + <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */
  6497. + <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
  6498. + <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
  6499. + <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */
  6500. + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */
  6501. + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */
  6502. + <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */
  6503. + <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
  6504. + qcom,bus-vector-names = "MIN",
  6505. + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
  6506. + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
  6507. + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
  6508. + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
  6509. + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
  6510. + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
  6511. + "MAX";
  6512. +
  6513. + qcom,cpu-affinity = "affine_cores";
  6514. + qcom,cpu-affinity-mask = <0xf>; /* little cluster */
  6515. + qcom,cpu-dma-latency-us = <301>;
  6516. +
  6517. + spm-level = <5>;
  6518. + status = "disabled";
  6519. + };
  6520. +
  6521. + spi_0: spi_epm: spi@f9923000 { /* BLSP1 QUP1 */
  6522. + compatible = "qcom,spi-qup-v2";
  6523. + #address-cells = <1>;
  6524. + #size-cells = <0>;
  6525. + reg-names = "spi_physical", "spi_bam_physical";
  6526. + reg = <0xf9923000 0x1000>,
  6527. + <0xf9904000 0x19000>;
  6528. + interrupt-names = "spi_irq", "spi_bam_irq";
  6529. + interrupts = <0 95 0>, <0 238 0>;
  6530. + spi-max-frequency = <19200000>;
  6531. +
  6532. + qcom,infinite-mode = <0>;
  6533. + qcom,use-bam;
  6534. + qcom,ver-reg-exists;
  6535. + qcom,bam-consumer-pipe-index = <12>;
  6536. + qcom,bam-producer-pipe-index = <13>;
  6537. + qcom,master-id = <86>;
  6538. + qcom,use-pinctrl;
  6539. + pinctrl-names = "spi_default", "spi_sleep";
  6540. + pinctrl-0 = <&spi_0_active &spi_0_cs1_active>;
  6541. + pinctrl-1 = <&spi_0_sleep &spi_0_cs1_sleep>;
  6542. +
  6543. + clock-names = "iface_clk", "core_clk";
  6544. +
  6545. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  6546. + <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
  6547. + };
  6548. +//#ifdef VENDOR_EDIT
  6549. +/* add for fpc1021 fingerprints */
  6550. + spi_12: spi@f9968000 {
  6551. + compatible = "qcom,spi-qup-v2";
  6552. + //cell-index = <12>; //changhua
  6553. + #address-cells = <1>;
  6554. + #size-cells = <0>;
  6555. + reg-names = "spi_physical"/*, "spi_bam_physical"*/;
  6556. +
  6557. + /*Add BAM physical address
  6558. + BLSP1: 0xf9904000
  6559. + BLSP2: 0xf9944000
  6560. + */
  6561. +
  6562. + reg = <0xf9968000 0x1000>/*,
  6563. + <0xf9944000 0x19000>*/;
  6564. +
  6565. + interrupt-names = "spi12_irq"/*, "spi_bam_irq"*/;
  6566. +
  6567. + /* Add BAM IRQ
  6568. + BLSP1: 238
  6569. + BLSP2: 239 ??271??? 239 is offset
  6570. + */
  6571. + interrupts = <0 106 0>/*, <0 239 0>*/;
  6572. +
  6573. + spi-max-frequency = <4800000>;
  6574. +
  6575. + /* //changhua
  6576. + qcom,gpio-mosi = <&msm_gpio 85 0>;
  6577. + qcom,gpio-miso = <&msm_gpio 86 0>;
  6578. + qcom,gpio-clk = <&msm_gpio 88 0>;
  6579. + qcom,gpio-cs0 = <&msm_gpio 87 0>;
  6580. + */
  6581. +
  6582. + clock-names = "iface_clk", "core_clk";
  6583. + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
  6584. + <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>;
  6585. +
  6586. + qcom,master-id = <86>;
  6587. + /*qcom,infinite-mode = <0>;
  6588. + qcom,use-bam;
  6589. + qcom,ver-reg-exists;
  6590. + qcom,bam-consumer-pipe-index = <22>;
  6591. + qcom,bam-producer-pipe-index = <23>;
  6592. + */
  6593. + /*lichanghua add for use pinctrl*/
  6594. + /* Assign runtime functions to pins */
  6595. +
  6596. + qcom,use-pinctrl;
  6597. + pinctrl-names = "spi_default", "spi_sleep";
  6598. + pinctrl-0 = <&spi_12_active &spi_12_cs0_active>;
  6599. + pinctrl-1 = <&spi_12_sleep &spi_12_cs0_sleep>;
  6600. +
  6601. + qcom,shared;
  6602. +
  6603. + /*lichanghua add for use pinctrl end*/
  6604. + };
  6605. +//#endif/*VENDOR_EDIT*/
  6606. +
  6607. + qcom,msm-ssc-sensors {
  6608. + compatible = "qcom,msm-ssc-sensors";
  6609. + };
  6610. +
  6611. + qcom,msm-pacman {
  6612. + compatible = "qcom,msm-pacman";
  6613. + };
  6614. +
  6615. + wcd9xxx_intc: wcd9xxx-irq {
  6616. + compatible = "qcom,wcd9xxx-irq";
  6617. + interrupt-controller;
  6618. + #interrupt-cells = <1>;
  6619. + interrupt-parent = <&msm_gpio>;
  6620. + interrupts = <72 0>;
  6621. + interrupt-names = "cdc-int";
  6622. + pinctrl-names = "default";
  6623. + pinctrl-0 = <&wcd_intr_default>;
  6624. + };
  6625. +
  6626. + tspp: msm_tspp@f99d8000 {
  6627. + compatible = "qcom,msm_tspp";
  6628. + reg = <0xf99d8000 0x1000>, /* MSM_TSIF0_PHYS */
  6629. + <0xf99d9000 0x1000>, /* MSM_TSIF1_PHYS */
  6630. + <0xf99da000 0x1000>, /* MSM_TSPP_PHYS */
  6631. + <0xf99c4000 0x11000>; /* MSM_TSPP_BAM_PHYS */
  6632. + reg-names = "MSM_TSIF0_PHYS",
  6633. + "MSM_TSIF1_PHYS",
  6634. + "MSM_TSPP_PHYS",
  6635. + "MSM_TSPP_BAM_PHYS";
  6636. + interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */
  6637. + <0 119 0>, /* TSIF0_IRQ */
  6638. + <0 120 0>, /* TSIF1_IRQ */
  6639. + <0 122 0>; /* TSIF_BAM_IRQ */
  6640. + interrupt-names = "TSIF_TSPP_IRQ",
  6641. + "TSIF0_IRQ",
  6642. + "TSIF1_IRQ",
  6643. + "TSIF_BAM_IRQ";
  6644. +
  6645. + clock-names = "iface_clk", "ref_clk";
  6646. + clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>,
  6647. + <&clock_gcc clk_gcc_tsif_ref_clk>;
  6648. +
  6649. + qcom,msm-bus,name = "tsif";
  6650. + qcom,msm-bus,num-cases = <2>;
  6651. + qcom,msm-bus,num-paths = <1>;
  6652. + qcom,msm-bus,vectors-KBps =
  6653. + <82 512 0 0>, /* No vote */
  6654. + <82 512 12288 24576>; /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
  6655. +
  6656. + pinctrl-names = "disabled",
  6657. + "tsif0-mode1", "tsif0-mode2",
  6658. + "tsif1-mode1", "tsif1-mode2",
  6659. + "dual-tsif-mode1", "dual-tsif-mode2";
  6660. +
  6661. + pinctrl-0 = <>; /* disabled */
  6662. + pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */
  6663. + pinctrl-2 = <&tsif0_signals_active
  6664. + &tsif0_sync_active>; /* tsif0-mode2 */
  6665. + pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */
  6666. + pinctrl-4 = <&tsif1_signals_active
  6667. + &tsif1_sync_active>; /* tsif1-mode2 */
  6668. + pinctrl-5 = <&tsif0_signals_active
  6669. + &tsif1_signals_active>; /* dual-tsif-mode1 */
  6670. + pinctrl-6 = <&tsif0_signals_active
  6671. + &tsif0_sync_active
  6672. + &tsif1_signals_active
  6673. + &tsif1_sync_active>; /* dual-tsif-mode2 */
  6674. + };
  6675. +
  6676. + slim_msm: slim@fe12f000 {
  6677. + cell-index = <1>;
  6678. + compatible = "qcom,slim-ngd";
  6679. + reg = <0xfe12f000 0x2C000>,
  6680. + <0xfe104000 0x20000>;
  6681. + reg-names = "slimbus_physical", "slimbus_bam_physical";
  6682. + interrupts = <0 163 0>, <0 164 0>;
  6683. + interrupt-names = "slimbus_irq", "slimbus_bam_irq";
  6684. + qcom,apps-ch-pipes = <0x60000000>;
  6685. + qcom,ea-pc = <0x110>;
  6686. +
  6687. + tomtom_codec {
  6688. + compatible = "qcom,tomtom-slim-pgd";
  6689. + elemental-addr = [00 01 30 01 17 02];
  6690. +
  6691. + interrupt-parent = <&wcd9xxx_intc>;
  6692. + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
  6693. + 17 18 19 20 21 22 23 24 25 26 27 28 29
  6694. + 30 31>;
  6695. +
  6696. + qcom,cdc-reset-gpio = <&msm_gpio 68 0>;
  6697. +
  6698. + cdc-vdd-buck-supply = <&pm8994_s5>;
  6699. + qcom,cdc-vdd-buck-voltage = <2150000 2150000>;
  6700. + qcom,cdc-vdd-buck-current = <650000>;
  6701. +
  6702. + cdc-vdd-tx-h-supply = <&pm8994_s4>;
  6703. + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
  6704. + qcom,cdc-vdd-tx-h-current = <25000>;
  6705. +
  6706. + cdc-vdd-rx-h-supply = <&pm8994_s4>;
  6707. + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
  6708. + qcom,cdc-vdd-rx-h-current = <25000>;
  6709. +
  6710. + cdc-vddpx-1-supply = <&pm8994_s4>;
  6711. + qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
  6712. + qcom,cdc-vddpx-1-current = <10000>;
  6713. +
  6714. + cdc-vdd-a-1p2v-supply = <&pm8994_l11>;
  6715. + qcom,cdc-vdd-a-1p2v-voltage = <1200000 1200000>;
  6716. + qcom,cdc-vdd-a-1p2v-current = <2000>;
  6717. +
  6718. + cdc-vddcx-1-supply = <&pm8994_l11>;
  6719. + qcom,cdc-vddcx-1-voltage = <1200000 1200000>;
  6720. + qcom,cdc-vddcx-1-current = <33000>;
  6721. +
  6722. + cdc-vddcx-2-supply = <&pm8994_l11>;
  6723. + qcom,cdc-vddcx-2-voltage = <1200000 1200000>;
  6724. + qcom,cdc-vddcx-2-current = <33000>;
  6725. +
  6726. + qcom,cdc-static-supplies = "cdc-vdd-buck",
  6727. + "cdc-vdd-tx-h",
  6728. + "cdc-vdd-rx-h",
  6729. + "cdc-vddpx-1",
  6730. + "cdc-vdd-a-1p2v",
  6731. + "cdc-vddcx-1",
  6732. + "cdc-vddcx-2";
  6733. +
  6734. + qcom,cdc-micbias-ldoh-v = <0x3>;
  6735. + qcom,cdc-micbias-cfilt1-mv = <1800>;
  6736. + //#ifdef VENDOR_EDIT
  6737. + /*wangdongdong@MultiMedia.AudioDrv , 2015/3/24, modify micbias voltage*/
  6738. + /*kangjirui@MultiMedia.AudioDrv , 2015/4/18, modify micbias voltage for headset button error*/
  6739. + qcom,cdc-micbias-cfilt2-mv = <2700>;
  6740. + //#endif /* VENDOR_EDIT */
  6741. + qcom,cdc-micbias-cfilt3-mv = <1800>;
  6742. + qcom,cdc-micbias1-cfilt-sel = <0x0>;
  6743. + qcom,cdc-micbias2-cfilt-sel = <0x1>;
  6744. + qcom,cdc-micbias3-cfilt-sel = <0x2>;
  6745. + qcom,cdc-micbias4-cfilt-sel = <0x2>;
  6746. + qcom,cdc-mclk-clk-rate = <9600000>;
  6747. + qcom,cdc-slim-ifd = "tomtom-slim-ifd";
  6748. + qcom,cdc-slim-ifd-elemental-addr = [00 00 30 01 17 02];
  6749. + qcom,cdc-dmic-sample-rate = <4800000>;
  6750. + qcom,cdc-mad-dmic-rate = <600000>;
  6751. + qcom,cdc-variant = "WCD9330";
  6752. + qcom,cdc-spkdrv-ocp-curr-limit-mA = <2625>;
  6753. + };
  6754. + };
  6755. +
  6756. + spmi_bus: qcom,spmi@fc4c0000 {
  6757. + compatible = "qcom,spmi-pmic-arb";
  6758. + reg-names = "core", "intr", "cnfg";
  6759. + reg = <0xfc4cf000 0x1000>,
  6760. + <0xfc4cb000 0x1000>,
  6761. + <0xfc4ca000 0x1000>;
  6762. + /* 190,ee0_krait_hlos_spmi_periph_irq */
  6763. + /* 187,channel_0_krait_hlos_trans_done_irq */
  6764. + interrupts = <0 190 0>, <0 187 0>;
  6765. + qcom,pmic-arb-channel = <0>;
  6766. + qcom,pmic-arb-ee = <0>;
  6767. + #interrupt-cells = <3>;
  6768. + interrupt-controller;
  6769. + #address-cells = <1>;
  6770. + #size-cells = <0>;
  6771. + cell-index = <0>;
  6772. + };
  6773. +
  6774. + usb3: ssusb@f9200000 {
  6775. + compatible = "qcom,dwc-usb3-msm";
  6776. + status = "disabled";
  6777. + reg = <0xf9200000 0xfc000>,
  6778. + <0xfd4ab000 0x4>;
  6779. + #address-cells = <1>;
  6780. + #size-cells = <1>;
  6781. + ranges;
  6782. +
  6783. + interrupt-parent = <&usb3>;
  6784. + interrupts = <0 1>;
  6785. + #interrupt-cells = <1>;
  6786. + interrupt-map-mask = <0x0 0xffffffff>;
  6787. + interrupt-map = <0x0 0 &intc 0 133 0
  6788. + 0x0 1 &intc 0 180 0
  6789. + 0x0 1 &spmi_bus 0x0 0x0 0x9 0x0>;
  6790. + interrupt-names = "hs_phy_irq", "pwr_event_irq", "pmic_id_irq";
  6791. +
  6792. + USB3_GDSC-supply = <&gdsc_usb30>;
  6793. + vdda33-supply = <&pm8994_l24>;
  6794. + vbus_dwc3-supply = <&smbcharger_charger_otg>;
  6795. + qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
  6796. + qcom,dwc-usb3-msm-qdss-tx-fifo-size = <8192>;
  6797. + qcom,usb-dbm = <&dbm_1p5>;
  6798. +
  6799. + qcom,msm-bus,name = "usb3";
  6800. + qcom,msm-bus,num-cases = <2>;
  6801. + qcom,msm-bus,num-paths = <1>;
  6802. + qcom,msm-bus,vectors-KBps =
  6803. + <61 512 0 0>,
  6804. + <61 512 240000 960000>;
  6805. +
  6806. + qcom,power-collapse-on-cable-disconnect;
  6807. + qcom,por-after-power-collapse;
  6808. +
  6809. + clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
  6810. + <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>,
  6811. + <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
  6812. + <&clock_gcc clk_gcc_usb30_sleep_clk>,
  6813. + <&clock_rpm clk_ln_bb_clk>,
  6814. + <&clock_rpm clk_cxo_dwc3_clk>;
  6815. + clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
  6816. + "ref_clk", "xo";
  6817. +
  6818. + dwc3@f9200000 {
  6819. + compatible = "synopsys,dwc3";
  6820. + reg = <0xf9200000 0xfc000>;
  6821. + interrupt-parent = <&intc>;
  6822. + interrupts = <0 131 0>;
  6823. + tx-fifo-resize;
  6824. + snps,usb3-u1u2-disable;
  6825. + usb-phy = <&hsphy0>, <&ssphy0>;
  6826. + };
  6827. + };
  6828. +
  6829. + hsphy0: hsphy@f92f8800 {
  6830. + compatible = "qcom,usb-hsphy";
  6831. + status = "disabled";
  6832. + reg = <0xf92f8800 0x3ff>,
  6833. + <0xf9b3a000 0x110>;
  6834. + reg-names = "core", "phy_csr";
  6835. + // #ifdef VENDOR_EDIT
  6836. + /*modify by jiachenghui from 0x00D191A4 to 0x00D191A7 for OTG 2015-04-22*/
  6837. + /*change HS DC voltage-level to 0x0011 by jiachenghui for OTG detect issue 2015-05-23*/
  6838. + qcom,hsphy-init = <0x00D187A7>;
  6839. + //#endif /*VENDOR_EDIT*/
  6840. + vdd-supply = <&pm8994_s2_corner>;
  6841. + vddcx-supply = <&pm8994_s1_corner>;
  6842. + vdda18-supply = <&pm8994_l6>;
  6843. + vdda33-supply = <&pm8994_l24>;
  6844. + qcom,vdd-voltage-level = <1 5 7>;
  6845. + qcom,ext-vbus-id;
  6846. + qcom,vbus-valid-override;
  6847. + qcom,set-pllbtune;
  6848. + qcom,sleep-clk-reset;
  6849. + qcom,vdda-force-on;
  6850. + clocks = <&clock_gcc clk_gcc_usb2_hs_phy_sleep_clk>;
  6851. + clock-names = "phy_sleep_clk";
  6852. + };
  6853. +
  6854. + ssphy0: ssphy@f9b38000 {
  6855. + compatible = "qcom,usb-ssphy-qmp";
  6856. + status = "disabled";
  6857. + reg = <0xf9b38000 0x800>,
  6858. + <0xf9b3e000 0x3ff>;
  6859. + reg-names = "qmp_phy_base",
  6860. + "qmp_ahb2phy_base";
  6861. + vdd-supply = <&pm8994_l28>;
  6862. + vdda18-supply = <&pm8994_l6>;
  6863. + qcom,vdd-voltage-level = <0 1000000 1000000>;
  6864. + qcom,vbus-valid-override;
  6865. + qcom,no-pipe-clk-switch;
  6866. +
  6867. + clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
  6868. + <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
  6869. + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
  6870. + <&clock_gcc clk_gcc_usb3_phy_reset>,
  6871. + <&clock_gcc clk_gcc_usb3phy_phy_reset>,
  6872. + <&clock_gcc clk_usb_ss_phy_ldo>;
  6873. + clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "phy_reset",
  6874. + "phy_phy_reset", "ldo_clk";
  6875. + };
  6876. +
  6877. + dbm_1p5: dbm@f92f8000 {
  6878. + compatible = "qcom,usb-dbm-1p5";
  6879. + reg = <0xf92f8000 0x1000>;
  6880. + qcom,reset-ep-after-lpm-resume;
  6881. + };
  6882. +
  6883. + qcom,usbbam@f9304000 {
  6884. + compatible = "qcom,usb-bam-msm";
  6885. + reg = <0xf9304000 0x9000>,
  6886. + <0xf92f880c 0x4>;
  6887. + reg-names = "ssusb", "qscratch_ram1_reg";
  6888. + interrupts = <0 132 0>;
  6889. + interrupt-names = "ssusb";
  6890. + clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
  6891. + <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>;
  6892. + clock-names = "mem_clk", "mem_iface_clk";
  6893. +
  6894. + qcom,usb-bam-fifo-baseaddr = <0xf9200000>;
  6895. + qcom,usb-bam-num-pipes = <16>;
  6896. + qcom,ignore-core-reset-ack;
  6897. + qcom,disable-clk-gating;
  6898. + qcom,usb-bam-override-threshold = <0x4001>;
  6899. + qcom,usb-bam-max-mbps-highspeed = <400>;
  6900. + qcom,usb-bam-max-mbps-superspeed = <3600>;
  6901. +
  6902. + qcom,pipe0 {
  6903. + label = "ssusb-ipa-out-0";
  6904. + qcom,usb-bam-mem-type = <2>;
  6905. + qcom,bam-type = <0>;
  6906. + qcom,dir = <0>;
  6907. + qcom,pipe-num = <0>;
  6908. + qcom,peer-bam = <2>;
  6909. + qcom,src-bam-physical-address = <0xf9304000>;
  6910. + qcom,src-bam-pipe-index = <1>;
  6911. + qcom,data-fifo-size = <0x8000>;
  6912. + qcom,descriptor-fifo-size = <0x2000>;
  6913. + qcom,reset-bam-on-connect;
  6914. + };
  6915. + qcom,pipe1 {
  6916. + label = "ssusb-ipa-in-0";
  6917. + qcom,usb-bam-mem-type = <2>;
  6918. + qcom,bam-type = <0>;
  6919. + qcom,dir = <1>;
  6920. + qcom,pipe-num = <0>;
  6921. + qcom,peer-bam = <2>;
  6922. + qcom,dst-bam-physical-address = <0xf9304000>;
  6923. + qcom,dst-bam-pipe-index = <0>;
  6924. + qcom,data-fifo-size = <0x8000>;
  6925. + qcom,descriptor-fifo-size = <0x2000>;
  6926. + qcom,reset-bam-on-connect;
  6927. + };
  6928. + qcom,pipe2 {
  6929. + label = "ssusb-qdss-in-0";
  6930. + qcom,usb-bam-mem-type = <1>;
  6931. + qcom,bam-type = <0>;
  6932. + qcom,dir = <1>;
  6933. + qcom,pipe-num = <0>;
  6934. + qcom,peer-bam = <1>;
  6935. + qcom,src-bam-physical-address = <0xfc37C000>;
  6936. + qcom,src-bam-pipe-index = <0>;
  6937. + qcom,dst-bam-physical-address = <0xf9304000>;
  6938. + qcom,dst-bam-pipe-index = <2>;
  6939. + qcom,data-fifo-offset = <0xf0000>;
  6940. + qcom,data-fifo-size = <0x1800>;
  6941. + qcom,descriptor-fifo-offset = <0xf4000>;
  6942. + qcom,descriptor-fifo-size = <0x1400>;
  6943. + qcom,reset-bam-on-connect;
  6944. + };
  6945. +
  6946. + /* USB BAM pipe (consumer) configuration for accelerated DPL */
  6947. + qcom,pipe3 {
  6948. + label = "ssusb-dpl-ipa-in-1";
  6949. + qcom,usb-bam-mem-type = <2>;
  6950. + qcom,bam-type = <0>;
  6951. + qcom,dir = <1>;
  6952. + qcom,pipe-num = <1>;
  6953. + qcom,peer-bam = <2>;
  6954. + qcom,dst-bam-physical-address = <0xf9304000>;
  6955. + qcom,dst-bam-pipe-index = <2>;
  6956. + qcom,data-fifo-size = <0x8000>;
  6957. + qcom,descriptor-fifo-size = <0x2000>;
  6958. + qcom,reset-bam-on-connect;
  6959. + };
  6960. + };
  6961. +
  6962. + usb_otg: usb@f9a55000 {
  6963. + compatible = "qcom,hsusb-otg";
  6964. + status = "disabled";
  6965. +
  6966. + reg = <0xf9a55000 0x400>;
  6967. + reg-names = "core";
  6968. + interrupts = <0 134 0 0 140 0>;
  6969. + interrupt-names = "core_irq", "async_irq";
  6970. +
  6971. + HSUSB_VDDCX-supply = <&pm8994_s2_corner>;
  6972. + HSUSB_1p8-supply = <&pm8994_l6>;
  6973. + HSUSB_3p3-supply = <&pm8994_l24>;
  6974. + qcom,vdd-voltage-level = <1 5 7>;
  6975. +
  6976. + clocks = <&clock_gcc clk_gcc_usb_hs_system_clk>,
  6977. + <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
  6978. + <&clock_gcc clk_gcc_usb2_hs_phy_sleep_clk>,
  6979. + <&clock_rpm clk_cxo_otg_clk>;
  6980. + clock-names = "core_clk", "iface_clk", "sleep_clk", "xo";
  6981. +
  6982. + qcom,hsusb-otg-phy-type = <2>;
  6983. + qcom,hsusb-otg-phy-init-seq = <0x63 0x81 0xffffffff>;
  6984. + qcom,hsusb-otg-mode = <1>;
  6985. + qcom,hsusb-otg-otg-control = <1>;
  6986. + };
  6987. +
  6988. + usb_ehci: ehci@f9a55000 {
  6989. + compatible = "qcom,ehci-host";
  6990. + status = "disabled";
  6991. + reg = <0xf9a55000 0x400>;
  6992. + interrupts = <0 134 0>, <0 140 0>;
  6993. + interrupt-names = "core_irq", "async_irq";
  6994. + hsusb_vdd_dig-supply = <&pm8994_s2_corner>;
  6995. + HSUSB_1p8-supply = <&pm8994_l6>;
  6996. + HSUSB_3p3-supply = <&pm8994_l24>;
  6997. + qcom,vdd-voltage-level = <1 2 3 5 7>;
  6998. + qcom,usb2-power-budget = <500>;
  6999. + usb-phy = <&qusb_phy>;
  7000. + qcom,pm-qos-latency = <30001>;
  7001. +
  7002. + qcom,msm-bus,name = "usb-hs";
  7003. + qcom,msm-bus,num-cases = <2>;
  7004. + qcom,msm-bus,num-paths = <1>;
  7005. + qcom,msm-bus,vectors-KBps =
  7006. + <87 512 0 0>,
  7007. + <87 512 40000 60000>;
  7008. +
  7009. + clocks = <&clock_gcc clk_gcc_usb_hs_system_clk>,
  7010. + <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
  7011. + <&clock_rpm clk_cxo_otg_clk>;
  7012. + clock-names = "core_clk", "iface_clk", "xo";
  7013. + };
  7014. +
  7015. + qusb_phy: qusb@f9b39000 {
  7016. + compatible = "qcom,qusb2phy";
  7017. + status = "disabled";
  7018. + reg = <0xf9b39000 0x17f>;
  7019. + reg-names = "qusb_phy_base";
  7020. + vdd-supply = <&pm8994_s2_corner>;
  7021. + vdda18-supply = <&pm8994_l6>;
  7022. + vdda33-supply = <&pm8994_l24>;
  7023. + qcom,vdd-voltage-level = <1 5 7>;
  7024. + qcom,qusb-tune = <0xa08391d5>;
  7025. + phy_type = "ulpi";
  7026. + clocks = <&clock_rpm clk_ln_bb_clk>,
  7027. + <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
  7028. + <&clock_gcc clk_gcc_qusb2_phy_reset>;
  7029. + clock-names = "ref_clk", "cfg_ahb_clk", "phy_reset";
  7030. + };
  7031. +
  7032. + android_usb@fe87f0c8 {
  7033. + compatible = "qcom,android-usb";
  7034. + reg = <0xfe87f0c8 0xc8>;
  7035. + qcom,pm-qos-latency = <61 637 1261>;
  7036. + /*add by jiachenghui for cdrom,20150528*/
  7037. + /*#ifdef VENDOR_EDIT*/
  7038. + qcom,android-usb-cdrom;
  7039. + /*#ifdef VENDOR_EDIT*/
  7040. + /*end add by jiachenghui for cdrom,20150528*/
  7041. + };
  7042. +
  7043. + qcom,venus@fdce0000 {
  7044. + compatible = "qcom,pil-tz-generic";
  7045. + reg = <0xfdce0000 0x4000>;
  7046. +
  7047. + vdd-supply = <&gdsc_venus>;
  7048. + qcom,proxy-reg-names = "vdd";
  7049. + clock-names = "core_clk", "iface_clk",
  7050. + "bus_clk", "mem_clk", "scm_ce1_clk";
  7051. + qcom,proxy-clock-names = "core_clk", "iface_clk",
  7052. + "bus_clk", "mem_clk", "scm_ce1_clk";
  7053. + qcom,scm_ce1_clk-freq = <85710000>;
  7054. +
  7055. + clocks = <&clock_mmss clk_venus0_vcodec0_clk>,
  7056. + <&clock_mmss clk_venus0_ahb_clk>,
  7057. + <&clock_mmss clk_venus0_axi_clk>,
  7058. + <&clock_mmss clk_venus0_ocmemnoc_clk>,
  7059. + <&clock_rpm clk_scm_ce1_clk>;
  7060. +
  7061. + qcom,msm-bus,name = "pil-venus";
  7062. + qcom,msm-bus,num-cases = <2>;
  7063. + qcom,msm-bus,num-paths = <1>;
  7064. + qcom,msm-bus,vectors-KBps =
  7065. + <63 512 0 0>,
  7066. + <63 512 0 304000>;
  7067. + qcom,pas-id = <9>;
  7068. + qcom,proxy-timeout-ms = <100>;
  7069. + qcom,firmware-name = "venus";
  7070. + linux,contiguous-region = <&peripheral_mem>;
  7071. + };
  7072. +
  7073. + qcom,mss@fc880000 {
  7074. + compatible = "qcom,pil-q6v55-mss";
  7075. + reg = <0xfc880000 0x100>,
  7076. + <0xfd485000 0x400>,
  7077. + <0xfc820000 0x020>,
  7078. + <0xfc401680 0x004>;
  7079. + reg-names = "qdsp6_base", "halt_base", "rmb_base",
  7080. + "restart_reg";
  7081. +
  7082. + clocks = <&clock_rpm clk_cxo_clk_src>,
  7083. + <&clock_rpm clk_mss_cfg_ahb_clk>,
  7084. + <&clock_rpm clk_pnoc_modem_clk>,
  7085. + <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
  7086. + <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
  7087. + <&clock_gcc clk_gpll0_out_msscc>;
  7088. + clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
  7089. + "mem_clk", "gpll0_mss_clk";
  7090. + qcom,proxy-clock-names = "xo", "pnoc_clk";
  7091. + qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
  7092. + "gpll0_mss_clk";
  7093. +
  7094. + interrupts = <0 24 1>;
  7095. + vdd_mss-supply = <&pm8994_s7>;
  7096. + vdd_cx-supply = <&pm8994_s1_corner>;
  7097. + vdd_mx-supply = <&pm8994_s2_corner>;
  7098. + vdd_mx-uV = <7>;
  7099. + vdd_pll-supply = <&pm8994_l12>;
  7100. + qcom,vdd_pll = <1800000>;
  7101. + qcom,firmware-name = "modem";
  7102. + qcom,pil-self-auth;
  7103. + qcom,mba-image-is-not-elf;
  7104. + qcom,sysmon-id = <0>;
  7105. + qcom,ssctl-instance-id = <0x12>;
  7106. + qcom,override-acc;
  7107. + qcom,ahb-clk-vote;
  7108. + qcom,pnoc-clk-vote;
  7109. +
  7110. + /* GPIO inputs from mss */
  7111. + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
  7112. + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
  7113. + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
  7114. + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
  7115. +
  7116. + /* GPIO output to mss */
  7117. + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
  7118. +
  7119. + linux,contiguous-region = <&modem_mem>;
  7120. + };
  7121. +
  7122. + qcom,lpass@fe200000 {
  7123. + compatible = "qcom,pil-tz-generic";
  7124. + reg = <0xfe200000 0x00100>;
  7125. + interrupts = <0 162 1>;
  7126. +
  7127. + vdd_cx-supply = <&pm8994_s1_corner>;
  7128. + qcom,proxy-reg-names = "vdd_cx";
  7129. + qcom,vdd_cx-uV-uA = <7 100000>;
  7130. +
  7131. + clocks = <&clock_rpm clk_cxo_pil_lpass_clk>,
  7132. + <&clock_rpm clk_scm_ce1_clk>;
  7133. + clock-names = "xo", "scm_ce1_clk";
  7134. + qcom,proxy-clock-names = "xo", "scm_ce1_clk";
  7135. + qcom,scm_ce1_clk-freq = <85710000>;
  7136. +
  7137. + qcom,pas-id = <1>;
  7138. + qcom,proxy-timeout-ms = <10000>;
  7139. + qcom,smem-id = <423>;
  7140. + qcom,sysmon-id = <1>;
  7141. + qcom,ssctl-instance-id = <0x14>;
  7142. + qcom,firmware-name = "adsp";
  7143. +
  7144. + /* GPIO inputs from lpass */
  7145. + qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
  7146. + qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
  7147. + qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
  7148. + qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
  7149. +
  7150. + /* GPIO output to lpass */
  7151. + qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
  7152. +
  7153. + linux,contiguous-region = <&peripheral_mem>;
  7154. + };
  7155. +
  7156. +/* #ifdef VENDOR_EDIT // add by xcb for ramoops 2015-03-31 */
  7157. + ramoops {
  7158. + compatible = "ramoops";
  7159. + /*reg = <0x05800000 0x00100000>;*/
  7160. + linux,contiguous-region = <&ramoops_mem>;
  7161. + };
  7162. +/* #endif VENDOR_EDIT */
  7163. +
  7164. +
  7165. + clock_rpm: qcom,rpmcc@fc401880 {
  7166. + compatible = "qcom,rpmcc-8994";
  7167. + reg = <0xfc401880 0x4>;
  7168. + reg-names = "cc_base";
  7169. + #clock-cells = <1>;
  7170. + };
  7171. +
  7172. + clock_gcc: qcom,gcc@fc400000 {
  7173. + compatible = "qcom,gcc-8994";
  7174. + reg = <0xfc400000 0x2000>;
  7175. + reg-names = "cc_base";
  7176. + vdd_dig-supply = <&pm8994_s1_corner>;
  7177. + clock-names = "xo", "xo_a_clk";
  7178. + clocks = <&clock_rpm clk_cxo_clk_src>,
  7179. + <&clock_rpm clk_cxo_clk_src_ao>;
  7180. + #clock-cells = <1>;
  7181. + };
  7182. +
  7183. + clock_mmss: qcom,mmsscc@fd8c0000 {
  7184. + compatible = "qcom,mmsscc-8994";
  7185. + reg = <0xfd8c0000 0x5200>;
  7186. + reg-names = "cc_base";
  7187. + vdd_dig-supply = <&pm8994_s1_corner>;
  7188. + mmpll4_dig-supply = <&pm8994_s1_corner>;
  7189. + mmpll4_analog-supply = <&pm8994_l12>;
  7190. + clock-names = "xo", "gpll0", "mmssnoc_ahb",
  7191. + "oxili_gfx3d_clk", "pclk0_src", "pclk1_src",
  7192. + "byte0_src", "byte1_src", "extpclk_src";
  7193. + clocks = <&clock_rpm clk_cxo_clk_src>,
  7194. + <&clock_gcc clk_gpll0_out_mmsscc>,
  7195. + <&clock_rpm clk_mmssnoc_ahb_clk>,
  7196. + <&clock_rpm clk_oxili_gfx3d_clk_src>,
  7197. + <&mdss_dsi0_pll clk_mdss_pixel_clk_mux>,
  7198. + <&mdss_dsi0_pll clk_mdss_pixel_clk_mux>,
  7199. + <&mdss_dsi0_pll clk_mdss_byte_clk_mux>,
  7200. + <&mdss_dsi0_pll clk_mdss_byte_clk_mux>,
  7201. + <&mdss_hdmi_pll clk_hdmi_20nm_vco_clk>;
  7202. + #clock-cells = <1>;
  7203. + };
  7204. +
  7205. + clock_debug: qcom,cc-debug@fc401880 {
  7206. + compatible = "qcom,cc-debug-8994";
  7207. + reg = <0xfc401880 0x4>;
  7208. + reg-names = "cc_base";
  7209. + clock-names = "debug_mmss_clk", "debug_rpm_clk",
  7210. + "debug_cpu_clk";
  7211. + clocks = <&clock_mmss clk_mmss_debug_mux>,
  7212. + <&clock_rpm clk_rpm_debug_mux>,
  7213. + <&clock_cpu clk_cpu_debug_mux>;
  7214. + #clock-cells = <1>;
  7215. + };
  7216. +
  7217. + cci_cache: qcom,cci {
  7218. + compatible = "devfreq-simple-dev";
  7219. + clock-names = "devfreq_clk";
  7220. + clocks = <&clock_cpu clk_cci_clk>;
  7221. + governor = "cpufreq";
  7222. + freq-tbl-khz =
  7223. + < 150000 >,
  7224. + < 200000 >,
  7225. + < 249600 >,
  7226. + < 300000 >,
  7227. + < 384000 >,
  7228. + < 499200 >,
  7229. + < 600000 >;
  7230. + };
  7231. +
  7232. + cpubw: qcom,cpubw {
  7233. + compatible = "qcom,devbw";
  7234. + governor = "cpufreq";
  7235. + qcom,src-dst-ports = <1 512>;
  7236. + qcom,active-only;
  7237. + qcom,bw-tbl =
  7238. + < 1525 /* 200 MHz */ >,
  7239. + < 2288 /* 300 MHz */ >,
  7240. + < 3509 /* 460 MHz */ >,
  7241. + < 4066 /* 533 MHz */ >,
  7242. + < 5126 /* 672 MHz */ >,
  7243. + < 5928 /* 777 MHz */ >,
  7244. + < 7904 /* 1036 MHz */ >,
  7245. + < 9887 /* 1296 MHz */ >,
  7246. + < 11863 /* 1555 MHz */ >;
  7247. + };
  7248. +
  7249. + qcom,cpu-bwmon {
  7250. + compatible = "qcom,bimc-bwmon";
  7251. + reg = <0xfc388000 0x300>, <0xfc381000 0x200>;
  7252. + reg-names = "base", "global_base";
  7253. + interrupts = <0 183 4>;
  7254. + qcom,mport = <0>;
  7255. + qcom,target-dev = <&cpubw>;
  7256. + };
  7257. +
  7258. + mincpubw: qcom,mincpubw {
  7259. + compatible = "qcom,devbw";
  7260. + governor = "powersave";
  7261. + qcom,src-dst-ports = <1 512>;
  7262. + qcom,active-only;
  7263. + qcom,bw-tbl =
  7264. + < 1525 /* 200 MHz */ >,
  7265. + < 2288 /* 300 MHz */ >,
  7266. + < 3509 /* 460 MHz */ >,
  7267. + < 4066 /* 533 MHz */ >,
  7268. + < 5126 /* 672 MHz */ >,
  7269. + < 5928 /* 777 MHz */ >,
  7270. + < 7904 /* 1036 MHz */ >,
  7271. + < 9887 /* 1296 MHz */ >,
  7272. + < 11863 /* 1555 MHz */ >;
  7273. + };
  7274. +
  7275. + devfreq_cpufreq: devfreq-cpufreq {
  7276. + cpubw-cpufreq {
  7277. + target-dev = <&cpubw>;
  7278. + cpu-to-dev-map-0 =
  7279. + < 199200 1525 >,
  7280. + < 302400 1525 >,
  7281. + < 384000 1525 >,
  7282. + < 600000 1525 >,
  7283. + < 691200 2288 >,
  7284. + < 768000 3562 >,
  7285. + < 844800 4066 >,
  7286. + < 921600 5126 >,
  7287. + < 940800 6072 >;
  7288. + cpu-to-dev-map-4 =
  7289. + < 199200 1525 >,
  7290. + < 302400 1525 >,
  7291. + < 384000 1525 >,
  7292. + < 600000 2288 >,
  7293. + < 691200 3562 >,
  7294. + < 768000 4066 >,
  7295. + < 844800 5126 >,
  7296. + < 921600 6072 >;
  7297. + };
  7298. +
  7299. + mincpubw-cpufreq {
  7300. + target-dev = <&mincpubw>;
  7301. + cpu-to-dev-map-0 =
  7302. + < 199200 1525 >,
  7303. + < 302400 1525 >,
  7304. + < 384000 2288 >,
  7305. + < 600000 3509 >,
  7306. + < 691200 4066 >,
  7307. + < 768000 5126 >,
  7308. + < 844800 5928 >,
  7309. + < 921600 5928 >,
  7310. + < 940800 5928 >;
  7311. + cpu-to-dev-map-4 =
  7312. + < 199200 1525 >,
  7313. + < 302400 1525 >,
  7314. + < 384000 2288 >,
  7315. + < 600000 3509 >,
  7316. + < 691200 4066 >,
  7317. + < 768000 5126 >,
  7318. + < 844800 5928 >,
  7319. + < 921600 5928 >;
  7320. + };
  7321. +
  7322. + cci-cpufreq {
  7323. + target-dev = <&cci_cache>;
  7324. + cpu-to-dev-map-0 =
  7325. + < 199200 150000 >,
  7326. + < 302400 200000 >,
  7327. + < 384000 249600 >,
  7328. + < 600000 300000 >,
  7329. + < 691200 384000 >,
  7330. + < 768000 384000 >,
  7331. + < 844800 499200 >,
  7332. + < 921600 600000 >,
  7333. + < 940800 600000 >;
  7334. + cpu-to-dev-map-4 =
  7335. + < 199200 150000 >,
  7336. + < 302400 200000 >,
  7337. + < 384000 249600 >,
  7338. + < 600000 300000 >,
  7339. + < 691200 384000 >,
  7340. + < 768000 499200 >,
  7341. + < 844800 600000 >,
  7342. + < 921600 600000 >;
  7343. + };
  7344. + };
  7345. +
  7346. + msm_cpufreq: qcom,msm-cpufreq {
  7347. + compatible = "qcom,msm-cpufreq";
  7348. + clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
  7349. + "cpu3_clk", "cpu4_clk", "cpu5_clk",
  7350. + "cpu6_clk", "cpu7_clk";
  7351. + clocks = <&clock_cpu clk_cci_clk>,
  7352. + <&clock_cpu clk_a53_clk>,
  7353. + <&clock_cpu clk_a53_clk>,
  7354. + <&clock_cpu clk_a53_clk>,
  7355. + <&clock_cpu clk_a53_clk>,
  7356. + <&clock_cpu clk_a57_clk>,
  7357. + <&clock_cpu clk_a57_clk>,
  7358. + <&clock_cpu clk_a57_clk>,
  7359. + <&clock_cpu clk_a57_clk>;
  7360. +
  7361. + qcom,governor-per-policy;
  7362. +
  7363. + qcom,cpufreq-table-0 =
  7364. + < 199200 >,
  7365. + < 302400 >,
  7366. + < 384000 >,
  7367. + < 600000 >,
  7368. + < 691200 >,
  7369. + < 768000 >,
  7370. + < 844800 >,
  7371. + < 921600 >,
  7372. + < 940800 >;
  7373. +
  7374. + qcom,cpufreq-table-4 =
  7375. + < 199200 >,
  7376. + < 302400 >,
  7377. + < 384000 >,
  7378. + < 600000 >,
  7379. + < 691200 >,
  7380. + < 768000 >,
  7381. + < 844800 >,
  7382. + < 921600 >;
  7383. + };
  7384. +
  7385. + clock_cpu: qcom,cpu-clock-8994@f9015000 {
  7386. + compatible = "qcom,cpu-clock-8994";
  7387. + reg = <0xf9015000 0x1000>,
  7388. + <0xf9016000 0x1000>,
  7389. + <0xf9011000 0x1000>,
  7390. + <0xf900d000 0x1000>,
  7391. + <0xf900f000 0x1000>,
  7392. + <0xf9112000 0x1000>,
  7393. + <0xfc4b80b0 0x8>;
  7394. + reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux", "efuse";
  7395. + vdd-a53-supply = <&apc0_vreg_corner>;
  7396. + vdd-a57-supply = <&apc1_vreg_corner>;
  7397. + vdd-cci-supply = <&apc0_vreg_corner>;
  7398. + vdd-dig-supply = <&pm8994_s1_corner_ao>;
  7399. + qcom,a53-speedbin0-v0 =
  7400. + < 0 0>,
  7401. + < 199200000 1>,
  7402. + < 302400000 2>,
  7403. + < 384000000 3>,
  7404. + < 600000000 4>,
  7405. + < 691200000 5>,
  7406. + < 768000000 6>,
  7407. + < 844800000 7>,
  7408. + < 921600000 8>,
  7409. + < 940800000 9>;
  7410. + qcom,a57-speedbin0-v0 =
  7411. + < 0 0>,
  7412. + < 199200000 1>,
  7413. + < 302400000 2>,
  7414. + < 384000000 3>,
  7415. + < 600000000 4>,
  7416. + < 691200000 5>,
  7417. + < 768000000 6>,
  7418. + < 844800000 7>,
  7419. + < 921600000 8>;
  7420. + qcom,cci-speedbin0-v0 =
  7421. + < 0 0>,
  7422. + < 150000000 1>,
  7423. + < 200000000 2>,
  7424. + < 249600000 3>,
  7425. + < 300000000 4>,
  7426. + < 384000000 4>,
  7427. + < 499200000 7>,
  7428. + < 600000000 9>;
  7429. + clock-names = "xo_ao", "aux_clk";
  7430. + clocks = <&clock_rpm clk_cxo_clk_src_ao>,
  7431. + <&clock_gcc clk_gpll0_ao>;
  7432. + #clock-cells = <1>;
  7433. + };
  7434. +
  7435. + ocmem: qcom,ocmem@fdd00000 {
  7436. + compatible = "qcom,msm-ocmem";
  7437. + reg = <0xfdd00000 0x2000>,
  7438. + <0xfdd02000 0x2000>,
  7439. + <0xfe039000 0x400>,
  7440. + <0xfec00000 0x200000>;
  7441. + reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
  7442. + interrupts = <0 76 0 0 77 0>;
  7443. + interrupt-names = "ocmem_irq", "dm_irq";
  7444. + qcom,ocmem-num-regions = <0x4>;
  7445. + qcom,ocmem-num-macros = <0x20>;
  7446. + qcom,resource-type = <0x706d636f>;
  7447. + #address-cells = <1>;
  7448. + #size-cells = <1>;
  7449. + ranges = <0x0 0xfec00000 0x200000>;
  7450. + clocks = <&clock_rpm clk_ocmemgx_core_clk>,
  7451. + <&clock_mmss clk_ocmemcx_ocmemnoc_clk>;
  7452. + clock-names = "core_clk", "iface_clk";
  7453. +
  7454. + partition@0 {
  7455. + reg = <0x0 0x180000>;
  7456. + qcom,ocmem-part-name = "graphics";
  7457. + qcom,ocmem-part-min = <0x80000>;
  7458. + };
  7459. +
  7460. + partition@100000 {
  7461. + reg = <0x180000 0x80000>;
  7462. + qcom,ocmem-part-name = "video";
  7463. + qcom,ocmem-part-min = <0x55000>;
  7464. + };
  7465. +
  7466. + };
  7467. +
  7468. + msm_vidc: qcom,vidc@fdc00000 {
  7469. + compatible = "qcom,msm-vidc";
  7470. + reg = <0xfdc00000 0xff000>;
  7471. + interrupts = <0 44 0>;
  7472. + qcom,hfi = "venus";
  7473. + qcom,reg-presets = <0x800D8 0x707>,
  7474. + <0xe0020 0x55555556>,
  7475. + <0xe0024 0x55555556>,
  7476. + <0x80124 0x3>;
  7477. + qcom,qdss-presets = <0xfc325000 0x1000>,
  7478. + <0xfc326000 0x1000>,
  7479. + <0xfc321000 0x1000>,
  7480. + <0xfc322000 0x1000>,
  7481. + <0xfc323000 0x1000>,
  7482. + <0xfc302000 0x1000>,
  7483. + <0xfa180000 0x1000>,
  7484. + <0xfa181000 0x1000>;
  7485. + qcom,ocmem-size = <524288>; /* 512 * 1024*/
  7486. + qcom,max-hw-load = <1281600>; /* Full 4k @ 30 + 1080p @ 30 */
  7487. + clock-names = "core_clk", "core0_clk", "core1_clk", "core2_clk",
  7488. + "iface_clk", "bus_clk", "mem_clk";
  7489. + venus-supply = <&gdsc_venus>;
  7490. + venus-core0-supply = <&gdsc_venus_core0>;
  7491. + venus-core1-supply = <&gdsc_venus_core1>;
  7492. + venus-core2-supply = <&gdsc_venus_core2>;
  7493. + qcom,clock-configs = <0x3 0x0 0x0 0x0 0x0 0x0 0x0>;
  7494. + qcom,sw-power-collapse;
  7495. + clocks = <&clock_mmss clk_venus0_vcodec0_clk>,
  7496. + <&clock_mmss clk_venus0_core0_vcodec_clk>,
  7497. + <&clock_mmss clk_venus0_core1_vcodec_clk>,
  7498. + <&clock_mmss clk_venus0_core2_vcodec_clk>,
  7499. + <&clock_mmss clk_venus0_ahb_clk>,
  7500. + <&clock_mmss clk_venus0_axi_clk>,
  7501. + <&clock_mmss clk_venus0_ocmemnoc_clk>;
  7502. + qcom,load-freq-tbl =
  7503. + <979200 465000000 0x0c000000>,
  7504. + <979200 465000000 0x01000414>,
  7505. + <979200 465000000 0x030fcfff>,
  7506. + <979200 465000000 0x04000000>,
  7507. + <783360 465000000 0x0c000000>,
  7508. + <783360 465000000 0x01000414>,
  7509. + <783360 465000000 0x030fcfff>,
  7510. + <783360 465000000 0x04000000>,
  7511. + <489600 240000000 0x0c000000>,
  7512. + <489600 240000000 0x01000414>,
  7513. + <489600 240000000 0x030fcfff>,
  7514. + <489600 240000000 0x04000000>,
  7515. + <244800 133330000 0x0c000000>,
  7516. + <244800 133330000 0x01000414>,
  7517. + <244800 133330000 0x030fcfff>,
  7518. + <244800 133330000 0x04000000>;
  7519. + qcom,vidc-iommu-domains {
  7520. + qcom,domain-ns {
  7521. + qcom,vidc-domain-phandle = <&venus_domain_ns>;
  7522. + qcom,vidc-partition-buffer-types = <0x7ff>,
  7523. + <0x800>;
  7524. + };
  7525. + qcom,domain-sec-bs {
  7526. + qcom,vidc-domain-phandle = <&venus_domain_sec_bitstream>;
  7527. + qcom,vidc-partition-buffer-types = <0x241>;
  7528. + };
  7529. + qcom,domain-sec-px {
  7530. + qcom,vidc-domain-phandle = <&venus_domain_sec_pixel>;
  7531. + qcom,vidc-partition-buffer-types = <0x106>;
  7532. + };
  7533. + qcom,domain-sec-np {
  7534. + qcom,vidc-domain-phandle = <&venus_domain_sec_non_pixel>;
  7535. + qcom,vidc-partition-buffer-types = <0x480>;
  7536. + };
  7537. + };
  7538. + qcom,msm-bus-clients {
  7539. + qcom,msm-bus-client@0 {
  7540. + qcom,msm-bus,name = "venc-core1-ddr";
  7541. + qcom,msm-bus,num-cases = <11>;
  7542. + qcom,msm-bus,num-paths = <1>;
  7543. + qcom,msm-bus,vectors-KBps =
  7544. + <63 512 0 0>,
  7545. + <63 512 66800 0>,
  7546. + <63 512 201100 0>,
  7547. + <63 512 201100 0>,
  7548. + <63 512 458300 0>,
  7549. + <63 512 458300 0>,
  7550. + <63 512 889200 0>,
  7551. + <63 512 889200 0>,
  7552. + <63 512 2108700 0>,
  7553. + <63 512 2243700 0>,
  7554. + <63 512 2615000 0>;
  7555. + qcom,bus-configs = <0x1000414>;
  7556. + };
  7557. +
  7558. + qcom,msm-bus-client@1 {
  7559. + qcom,msm-bus,name = "vdec-core0-ddr";
  7560. + qcom,msm-bus,num-cases = <11>;
  7561. + qcom,msm-bus,num-paths = <1>;
  7562. + qcom,msm-bus,vectors-KBps =
  7563. + <63 512 0 0>,
  7564. + <63 512 151600 0>,
  7565. + <63 512 393600 0>,
  7566. + <63 512 393600 0>,
  7567. + <63 512 749100 0>,
  7568. + <63 512 749100 0>,
  7569. + <63 512 1460700 0>,
  7570. + <63 512 1460700 0>,
  7571. + <63 512 2390500 0>,
  7572. + <63 512 2542300 0>,
  7573. + <63 512 2959800 0>;
  7574. + qcom,bus-configs = <0xc000000>;
  7575. + };
  7576. +
  7577. + qcom,msm-bus-client@2 {
  7578. + qcom,msm-bus,name = "vdec-core1-ddr";
  7579. + qcom,msm-bus,num-cases = <11>;
  7580. + qcom,msm-bus,num-paths = <1>;
  7581. + qcom,msm-bus,vectors-KBps =
  7582. + <63 512 0 0>,
  7583. + <63 512 113900 0>,
  7584. + <63 512 296700 0>,
  7585. + <63 512 296700 0>,
  7586. + <63 512 571400 0>,
  7587. + <63 512 571400 0>,
  7588. + <63 512 1088500 0>,
  7589. + <63 512 1088500 0>,
  7590. + <63 512 1811000 0>,
  7591. + <63 512 1962000 0>,
  7592. + <63 512 2242900 0>;
  7593. + qcom,bus-configs = <0x30fcfff>;
  7594. + };
  7595. +
  7596. + qcom,msm-bus-client@3 {
  7597. + qcom,msm-bus,name = "venc-core2-ddr";
  7598. + qcom,msm-bus,num-cases = <11>;
  7599. + qcom,msm-bus,num-paths = <1>;
  7600. + qcom,msm-bus,vectors-KBps =
  7601. + <63 512 0 0>,
  7602. + <63 512 89000 0>,
  7603. + <63 512 270000 0>,
  7604. + <63 512 270000 0>,
  7605. + <63 512 759000 0>,
  7606. + <63 512 759000 0>,
  7607. + <63 512 1050000 0>,
  7608. + <63 512 1050000 0>,
  7609. + <63 512 3077000 0>,
  7610. + <63 512 3811000 0>,
  7611. + <63 512 3812000 0>;
  7612. + qcom,bus-configs = <0x04000000>;
  7613. + };
  7614. + qcom,msm-bus-client@4 {
  7615. + qcom,msm-bus,name = "venc-core1-ocmem";
  7616. + qcom,msm-bus,num-cases = <11>;
  7617. + qcom,msm-bus,num-paths = <1>;
  7618. + qcom,msm-bus,vectors-KBps =
  7619. + <68 604 0 0>,
  7620. + <68 604 69000 2384000>,
  7621. + <68 604 207000 2384000>,
  7622. + <68 604 207000 2384000>,
  7623. + <68 604 470000 2384000>,
  7624. + <68 604 470000 2384000>,
  7625. + <68 604 940000 3632000>,
  7626. + <68 604 940000 3632000>,
  7627. + <68 604 1787000 3632000>,
  7628. + <68 604 1906000 3632000>,
  7629. + <68 604 2234000 3632000>;
  7630. + qcom,bus-configs = <0x10000414>;
  7631. + };
  7632. + qcom,msm-bus-client@5 {
  7633. + qcom,msm-bus,name = "venc-core2-ocmem";
  7634. + qcom,msm-bus,num-cases = <11>;
  7635. + qcom,msm-bus,num-paths = <1>;
  7636. + qcom,msm-bus,vectors-KBps =
  7637. + <68 604 0 0>,
  7638. + <68 604 71000 2384000>,
  7639. + <68 604 214000 2384000>,
  7640. + <68 604 214000 2384000>,
  7641. + <68 604 564000 2384000>,
  7642. + <68 604 564000 2384000>,
  7643. + <68 604 1003000 3632000>,
  7644. + <68 604 1003000 3632000>,
  7645. + <68 604 2040000 3632000>,
  7646. + <68 604 2349000 3632000>,
  7647. + <68 604 2551000 3632000>;
  7648. + qcom,bus-configs = <0x04000000>;
  7649. + };
  7650. +
  7651. + qcom,msm-bus-client@6 {
  7652. + qcom,msm-bus,name = "vdec-core0-ocmem";
  7653. + qcom,msm-bus,num-cases = <11>;
  7654. + qcom,msm-bus,num-paths = <1>;
  7655. + qcom,msm-bus,vectors-KBps =
  7656. + <68 604 0 0>,
  7657. + <68 604 79000 2384000>,
  7658. + <68 604 201000 2384000>,
  7659. + <68 604 201000 2384000>,
  7660. + <68 604 367000 2384000>,
  7661. + <68 604 367000 2384000>,
  7662. + <68 604 735000 3632000>,
  7663. + <68 604 735000 3632000>,
  7664. + <68 604 1175000 3632000>,
  7665. + <68 604 1254000 3632000>,
  7666. + <68 604 1469000 3632000>;
  7667. + qcom,bus-configs = <0xc000000>;
  7668. + };
  7669. +
  7670. + qcom,msm-bus-client@7 {
  7671. + qcom,msm-bus,name = "vdec-core1-ocmem";
  7672. + qcom,msm-bus,num-cases = <11>;
  7673. + qcom,msm-bus,num-paths = <1>;
  7674. + qcom,msm-bus,vectors-KBps =
  7675. + <68 604 0 0>,
  7676. + <68 604 88000 2384000>,
  7677. + <68 604 228000 2384000>,
  7678. + <68 604 228000 2384000>,
  7679. + <68 604 432000 2384000>,
  7680. + <68 604 432000 2384000>,
  7681. + <68 604 865000 3632000>,
  7682. + <68 604 865000 3632000>,
  7683. + <68 604 1374000 3632000>,
  7684. + <68 604 1465000 3632000>,
  7685. + <68 604 1717000 3632000>;
  7686. + qcom,bus-configs = <0x30fcfff>;
  7687. + };
  7688. +
  7689. + qcom,msm-bus-client@8 {
  7690. + qcom,msm-bus,name = "venc-ddr-lp";
  7691. + qcom,msm-bus,num-cases = <11>;
  7692. + qcom,msm-bus,num-paths = <1>;
  7693. + qcom,msm-bus,vectors-KBps =
  7694. + <63 512 0 0>,
  7695. + <63 512 66800 0>,
  7696. + <63 512 201100 0>,
  7697. + <63 512 201100 0>,
  7698. + <63 512 458300 0>,
  7699. + <63 512 458300 0>,
  7700. + <63 512 889200 0>,
  7701. + <63 512 889200 0>,
  7702. + <63 512 1218000 0>,
  7703. + <63 512 1218000 0>,
  7704. + <63 512 1218000 0>;
  7705. + qcom,bus-low-power;
  7706. + qcom,bus-configs = <0x0000004>;
  7707. + };
  7708. +
  7709. + qcom,msm-bus-client@9 {
  7710. + qcom,msm-bus,name = "venus-arm9-ddr";
  7711. + qcom,msm-bus,num-cases = <2>;
  7712. + qcom,msm-bus,num-paths = <1>;
  7713. + qcom,msm-bus,vectors-KBps =
  7714. + <63 512 0 0>,
  7715. + <63 512 1000 1000>;
  7716. + qcom,bus-configs = <0x00000000>;
  7717. + qcom,bus-passive;
  7718. + };
  7719. + };
  7720. + };
  7721. +
  7722. + i2c_1: i2c@f9923000 {
  7723. + compatible = "qcom,i2c-msm-v2";
  7724. + #address-cells = <1>;
  7725. + #size-cells = <0>;
  7726. + reg-names = "qup_phys_addr";
  7727. + reg = <0xf9923000 0x1000>;
  7728. + interrupt-names = "qup_irq";
  7729. + interrupts = <0 95 0>;
  7730. + qcom,clk-freq-out = <400000>;
  7731. + qcom,clk-freq-in = <19200000>;
  7732. + clock-names = "iface_clk", "core_clk";
  7733. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  7734. + <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
  7735. +
  7736. + pinctrl-names = "i2c_active", "i2c_sleep";
  7737. + pinctrl-0 = <&i2c_1_active>;
  7738. + pinctrl-1 = <&i2c_1_sleep>;
  7739. + qcom,noise-rjct-scl = <0>;
  7740. + qcom,noise-rjct-sda = <0>;
  7741. + qcom,master-id = <86>;
  7742. + dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
  7743. + <&dma_blsp1 11 32 0x20000020 0x20>;
  7744. + dma-names = "tx", "rx";
  7745. + status = "disabled";
  7746. + };
  7747. +
  7748. + dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */
  7749. + #dma-cells = <4>;
  7750. + compatible = "qcom,sps-dma";
  7751. + reg = <0xf9904000 0x19000>;
  7752. + interrupts = <0 238 0>;
  7753. + qcom,summing-threshold = <10>;
  7754. + };
  7755. +
  7756. + dma_blsp2: qcom,sps-dma@f9944000 { /* BLSP2 */
  7757. + #dma-cells = <4>;
  7758. + compatible = "qcom,sps-dma";
  7759. + reg = <0xf9944000 0x19000>;
  7760. + interrupts = <0 239 0>;
  7761. + qcom,summing-threshold = <10>;
  7762. + };
  7763. +
  7764. +
  7765. + i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */
  7766. + compatible = "qcom,i2c-msm-v2";
  7767. + #address-cells = <1>;
  7768. + #size-cells = <0>;
  7769. + reg-names = "qup_phys_addr";
  7770. + reg = <0xf9924000 0x1000>;
  7771. + interrupt-names = "qup_irq";
  7772. + interrupts = <0 96 0>;
  7773. + qcom,clk-freq-out = <400000>;
  7774. + qcom,clk-freq-in = <19200000>;
  7775. + clock-names = "iface_clk", "core_clk";
  7776. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  7777. + <&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
  7778. +
  7779. + pinctrl-names = "i2c_active", "i2c_sleep";
  7780. + pinctrl-0 = <&i2c_2_active>;
  7781. + pinctrl-1 = <&i2c_2_sleep>;
  7782. + qcom,noise-rjct-scl = <0>;
  7783. + qcom,noise-rjct-sda = <0>;
  7784. +
  7785. + /* #ifdef VENDOR_EDIT */
  7786. + //add by yangrujin@bsp for dma has some issue causing i2c fail
  7787. + //qcom,disable-dma;
  7788. + /* #endif //VENDOR_EDIT */
  7789. +
  7790. +
  7791. + dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
  7792. + <&dma_blsp1 15 32 0x20000020 0x20>;
  7793. + dma-names = "tx", "rx";
  7794. + qcom,master-id = <86>;
  7795. + };
  7796. +
  7797. + i2c_5: i2c_11: i2c@f9967000 { /* BLSP2 QUP5 */
  7798. + compatible = "qcom,i2c-msm-v2";
  7799. + #address-cells = <1>;
  7800. + #size-cells = <0>;
  7801. + reg-names = "qup_phys_addr";
  7802. + reg = <0xf9967000 0x1000>;
  7803. + interrupt-names = "qup_irq";
  7804. + interrupts = <0 105 0>;
  7805. + qcom,clk-freq-out = <100000>;
  7806. + qcom,clk-freq-in = <19200000>;
  7807. + clock-names = "iface_clk", "core_clk";
  7808. + clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
  7809. + <&clock_gcc clk_gcc_blsp2_qup5_i2c_apps_clk>;
  7810. +
  7811. + pinctrl-names = "i2c_active", "i2c_sleep";
  7812. + pinctrl-0 = <&i2c_5_active>;
  7813. + pinctrl-1 = <&i2c_5_sleep>;
  7814. + qcom,noise-rjct-scl = <0>;
  7815. + qcom,noise-rjct-sda = <0>;
  7816. + //#ifndef VENDOR_EDIT
  7817. + /*zhiguang.su@MultiMedia.AudioDrv , 2015/4/13, dma mode will cause I2C fail*/
  7818. + qcom,disable-dma;
  7819. + //#endif
  7820. + dmas = <&dma_blsp2 20 64 0x20000020 0x20>,
  7821. + <&dma_blsp2 21 32 0x20000020 0x20>;
  7822. + dma-names = "tx", "rx";
  7823. + qcom,master-id = <84>;
  7824. + };
  7825. +
  7826. + i2c_6: i2c@f9928000 { /* BLSP1 QUP6 */
  7827. + compatible = "qcom,i2c-msm-v2";
  7828. + #address-cells = <1>;
  7829. + #size-cells = <0>;
  7830. + status = "disabled";
  7831. + reg-names = "qup_phys_addr";
  7832. + reg = <0xf9928000 0x1000>;
  7833. + interrupt-names = "qup_irq";
  7834. + interrupts = <0 100 0>;
  7835. + qcom,clk-freq-out = <400000>;
  7836. + qcom,clk-freq-in = <19200000>;
  7837. + clock-names = "iface_clk", "core_clk";
  7838. + clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
  7839. + <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;
  7840. +
  7841. + pinctrl-names = "i2c_active", "i2c_sleep";
  7842. + pinctrl-0 = <&i2c_6_active>;
  7843. + pinctrl-1 = <&i2c_6_sleep>;
  7844. + qcom,noise-rjct-scl = <0>;
  7845. + qcom,noise-rjct-sda = <0>;
  7846. + dmas = <&dma_blsp1 22 64 0x20000020 0x20>,
  7847. + <&dma_blsp1 23 32 0x20000020 0x20>;
  7848. + dma-names = "tx", "rx";
  7849. + qcom,master-id = <86>;
  7850. + };
  7851. +
  7852. + sound {
  7853. + compatible = "qcom,msm8994-asoc-snd";
  7854. + qcom,model = "msm8994-tomtom-snd-card";
  7855. + reg = <0xfe034000 0x4>,
  7856. + <0xfe035000 0x4>,
  7857. + <0xfe036000 0x4>,
  7858. + <0xfe037000 0x4>;
  7859. + reg-names = "lpaif_pri_mode_muxsel",
  7860. + "lpaif_sec_mode_muxsel",
  7861. + "lpaif_tert_mode_muxsel",
  7862. + "lpaif_quat_mode_muxsel";
  7863. +
  7864. + qcom,audio-routing =
  7865. + "AIF4 VI", "MCLK",
  7866. + "RX_BIAS", "MCLK",
  7867. + "LDO_H", "MCLK",
  7868. + "MADINPUT", "MCLK";
  7869. + //#ifndef VENDOR_EDIT
  7870. + /*zhiguang.su@MultiMedia.AudioDrv , 2015/3/19, delete unsed mic*/
  7871. + //"AMIC1", "MIC BIAS1 Internal1",
  7872. + //"MIC BIAS1 Internal1", "Handset Mic",
  7873. + //"AMIC2", "MIC BIAS2 External",
  7874. + //"MIC BIAS2 External", "Headset Mic",
  7875. + //"AMIC3", "MIC BIAS2 External",
  7876. + //"MIC BIAS2 External", "ANCRight Headset Mic",
  7877. + //"AMIC4", "MIC BIAS2 External",
  7878. + //"MIC BIAS2 External", "ANCLeft Headset Mic",
  7879. + //"DMIC1", "MIC BIAS1 External",
  7880. + //"MIC BIAS1 External", "Digital Mic1",
  7881. + //"DMIC2", "MIC BIAS1 External",
  7882. + //"MIC BIAS1 External", "Digital Mic2",
  7883. + //"DMIC3", "MIC BIAS3 External",
  7884. + //"MIC BIAS3 External", "Digital Mic3",
  7885. + //"DMIC4", "MIC BIAS3 External",
  7886. + //"MIC BIAS3 External", "Digital Mic4",
  7887. + //"DMIC5", "MIC BIAS4 External",
  7888. + //"MIC BIAS4 External", "Digital Mic5",
  7889. + //"DMIC6", "MIC BIAS4 External",
  7890. + //"MIC BIAS4 External", "Digital Mic6";
  7891. + //#endif
  7892. +
  7893. + clock-names = "osr_clk";
  7894. + clocks = <&clock_rpm clk_div_clk1>;
  7895. + qcom,cdc-mclk-gpios = <&pm8994_gpios 15 0>;
  7896. + qcom,tomtom-mclk-clk-freq = <9600000>;
  7897. + pinctrl-names = "sleep",
  7898. + "auxpcm-active",
  7899. + "mi2s-active",
  7900. + //#ifdef VENDOR_EDIT
  7901. + /*zhiguang.su@MultiMedia.AudioDrv,changed for quat i2s */
  7902. + "active",
  7903. + "quat_mi2s_active",
  7904. + "quat_aux_active";
  7905. + //#endif
  7906. +//#ifdef VENDOR_EDIT
  7907. +//pinctrl-0 = <&pri_mi2s_sleep>, <&pri_mi2s_sd0_sleep>,
  7908. +// <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  7909. +//pinctrl-1 = <&pri_mi2s_sleep>, <&pri_mi2s_sd0_sleep>,
  7910. +// <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  7911. +//pinctrl-2 = <&pri_mi2s_active>, <&pri_mi2s_sd0_active>,
  7912. +// <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  7913. +//pinctrl-3 = <&pri_mi2s_active>, <&pri_mi2s_sd0_active>,
  7914. +// <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  7915. +//#endif
  7916. +
  7917. +//#ifdef VENDOR_EDIT
  7918. +/*zhiguang.su@MultiMedia.AudioDrv,2015-4-8,remove unused pri-i2s for conflict pins with BSP module.*/
  7919. + pinctrl-0 = <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  7920. + pinctrl-1 = <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  7921. + pinctrl-2 = <&sec_aux_pcm_sleep>, <&sec_aux_pcm_din_sleep>;
  7922. + pinctrl-3 = <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  7923. +//#endif
  7924. +//#ifdef VENDOR_EDIT
  7925. +/*zhiguang.su@MultiMedia.AudioDrv changed for quat i2s */
  7926. + pinctrl-4 = <&quat_mi2s_active>, <&quat_mi2s_mclk_active>, <&quat_mi2s_sd0_active> , <&quat_mi2s_sd1_active>;
  7927. + pinctrl-5 = <&quat_mi2s_active>, <&quat_mi2s_mclk_active>, <&quat_mi2s_sd0_active> , <&quat_mi2s_sd1_active> , <&sec_aux_pcm_active>, <&sec_aux_pcm_din_active>;
  7928. +//#endif
  7929. + asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
  7930. + <&loopback>, <&compress>, <&hostless>,
  7931. + <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>;
  7932. + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2",
  7933. + "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback",
  7934. + "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe",
  7935. + "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm",
  7936. + "msm-compr-dsp";
  7937. +//#ifdef VENDOR_EDIT
  7938. +/*zhiguang.su@MultiMedia.AudioDrv changed for quat i2s*/
  7939. + asoc-cpu = <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_hdmi>, <&dai_mi2s>,<&qua_mi2s>,
  7940. + <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
  7941. + <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
  7942. + <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, <&bt_sco_rx>,
  7943. + <&bt_sco_tx>, <&int_fm_rx>, <&int_fm_tx>, <&afe_pcm_rx>,
  7944. + <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>,
  7945. + <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>,
  7946. + <&incall_music2_rx>;
  7947. + asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
  7948. + "msm-dai-q6-hdmi.8", "msm-dai-q6-mi2s.0","msm-dai-q6-mi2s.3",
  7949. + "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385",
  7950. + "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387",
  7951. + "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389",
  7952. + "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391",
  7953. + "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393",
  7954. + "msm-dai-q6-dev.16395", "msm-dai-q6-dev.12288",
  7955. + "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292",
  7956. + "msm-dai-q6-dev.12293", "msm-dai-q6-dev.224",
  7957. + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
  7958. + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
  7959. + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
  7960. + "msm-dai-q6-dev.32770";
  7961. +//#endif
  7962. + asoc-codec = <&stub_codec>;
  7963. + asoc-codec-names = "msm-stub-codec.1";
  7964. + };
  7965. +
  7966. + qcom,msm-adsp-loader {
  7967. + compatible = "qcom,adsp-loader";
  7968. + qcom,adsp-state = <0>;
  7969. + };
  7970. +
  7971. + qcom,msm-audio-ion {
  7972. + compatible = "qcom,msm-audio-ion";
  7973. + };
  7974. +
  7975. + pcm0: qcom,msm-pcm {
  7976. + compatible = "qcom,msm-pcm-dsp";
  7977. + qcom,msm-pcm-dsp-id = <0>;
  7978. + };
  7979. +
  7980. + qcom,msm-pcm-lpa {
  7981. + compatible = "qcom,msm-pcm-lpa";
  7982. + };
  7983. +
  7984. + pcm2: qcom,msm-ultra-low-latency {
  7985. + compatible = "qcom,msm-pcm-dsp";
  7986. + qcom,msm-pcm-dsp-id = <2>;
  7987. + qcom,msm-pcm-low-latency;
  7988. + qcom,latency-level = "ultra";
  7989. + };
  7990. +
  7991. + pcm1: qcom,msm-pcm-low-latency {
  7992. + compatible = "qcom,msm-pcm-dsp";
  7993. + qcom,msm-pcm-dsp-id = <1>;
  7994. + qcom,msm-pcm-low-latency;
  7995. + qcom,latency-level = "regular";
  7996. + };
  7997. +
  7998. + routing: qcom,msm-pcm-routing {
  7999. + compatible = "qcom,msm-pcm-routing";
  8000. + };
  8001. +
  8002. + compr: qcom,msm-compr-dsp {
  8003. + compatible = "qcom,msm-compr-dsp";
  8004. + };
  8005. +
  8006. + compress: qcom,msm-compress-dsp {
  8007. + compatible = "qcom,msm-compress-dsp";
  8008. + };
  8009. +
  8010. + voip: qcom,msm-voip-dsp {
  8011. + compatible = "qcom,msm-voip-dsp";
  8012. + };
  8013. +
  8014. + voice: qcom,msm-pcm-voice {
  8015. + compatible = "qcom,msm-pcm-voice";
  8016. + qcom,destroy-cvd;
  8017. + };
  8018. +
  8019. + stub_codec: qcom,msm-stub-codec {
  8020. + compatible = "qcom,msm-stub-codec";
  8021. + };
  8022. +
  8023. + qcom,msm-dai-fe {
  8024. + compatible = "qcom,msm-dai-fe";
  8025. + };
  8026. +
  8027. + afe: qcom,msm-pcm-afe {
  8028. + compatible = "qcom,msm-pcm-afe";
  8029. + };
  8030. +
  8031. + dai_hdmi: qcom,msm-dai-q6-hdmi {
  8032. + compatible = "qcom,msm-dai-q6-hdmi";
  8033. + qcom,msm-dai-q6-dev-id = <8>;
  8034. + };
  8035. +
  8036. + lsm: qcom,msm-lsm-client {
  8037. + compatible = "qcom,msm-lsm-client";
  8038. + };
  8039. +
  8040. + loopback: qcom,msm-pcm-loopback {
  8041. + compatible = "qcom,msm-pcm-loopback";
  8042. + };
  8043. +
  8044. + qcom,msm-voice-svc {
  8045. + compatible = "qcom,msm-voice-svc";
  8046. + };
  8047. +
  8048. + cpe: qcom,msm-cpe-lsm {
  8049. + compatible = "qcom,msm-cpe-lsm";
  8050. + };
  8051. +
  8052. + qcom,msm-dai-q6 {
  8053. + compatible = "qcom,msm-dai-q6";
  8054. + sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
  8055. + compatible = "qcom,msm-dai-q6-dev";
  8056. + qcom,msm-dai-q6-dev-id = <16384>;
  8057. + };
  8058. +
  8059. + sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
  8060. + compatible = "qcom,msm-dai-q6-dev";
  8061. + qcom,msm-dai-q6-dev-id = <16385>;
  8062. + };
  8063. +
  8064. + sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
  8065. + compatible = "qcom,msm-dai-q6-dev";
  8066. + qcom,msm-dai-q6-dev-id = <16386>;
  8067. + };
  8068. +
  8069. + sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
  8070. + compatible = "qcom,msm-dai-q6-dev";
  8071. + qcom,msm-dai-q6-dev-id = <16387>;
  8072. + };
  8073. +
  8074. + sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
  8075. + compatible = "qcom,msm-dai-q6-dev";
  8076. + qcom,msm-dai-q6-dev-id = <16388>;
  8077. + };
  8078. +
  8079. + sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
  8080. + compatible = "qcom,msm-dai-q6-dev";
  8081. + qcom,msm-dai-q6-dev-id = <16389>;
  8082. + };
  8083. +
  8084. + sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
  8085. + compatible = "qcom,msm-dai-q6-dev";
  8086. + qcom,msm-dai-q6-dev-id = <16390>;
  8087. + };
  8088. +
  8089. + sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
  8090. + compatible = "qcom,msm-dai-q6-dev";
  8091. + qcom,msm-dai-q6-dev-id = <16391>;
  8092. + };
  8093. +
  8094. + sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
  8095. + compatible = "qcom,msm-dai-q6-dev";
  8096. + qcom,msm-dai-q6-dev-id = <16392>;
  8097. + };
  8098. +
  8099. + sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
  8100. + compatible = "qcom,msm-dai-q6-dev";
  8101. + qcom,msm-dai-q6-dev-id = <16393>;
  8102. + };
  8103. +
  8104. + sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
  8105. + compatible = "qcom,msm-dai-q6-dev";
  8106. + qcom,msm-dai-q6-dev-id = <16395>;
  8107. + };
  8108. +
  8109. + bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
  8110. + compatible = "qcom,msm-dai-q6-dev";
  8111. + qcom,msm-dai-q6-dev-id = <12288>;
  8112. + };
  8113. +
  8114. + bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
  8115. + compatible = "qcom,msm-dai-q6-dev";
  8116. + qcom,msm-dai-q6-dev-id = <12289>;
  8117. + };
  8118. +
  8119. + int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
  8120. + compatible = "qcom,msm-dai-q6-dev";
  8121. + qcom,msm-dai-q6-dev-id = <12292>;
  8122. + };
  8123. +
  8124. + int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
  8125. + compatible = "qcom,msm-dai-q6-dev";
  8126. + qcom,msm-dai-q6-dev-id = <12293>;
  8127. + };
  8128. +
  8129. + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
  8130. + compatible = "qcom,msm-dai-q6-dev";
  8131. + qcom,msm-dai-q6-dev-id = <224>;
  8132. + };
  8133. +
  8134. + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
  8135. + compatible = "qcom,msm-dai-q6-dev";
  8136. + qcom,msm-dai-q6-dev-id = <225>;
  8137. + };
  8138. +
  8139. + afe_proxy_rx: com,msm-dai-q6-afe-proxy-rx {
  8140. + compatible = "qcom,msm-dai-q6-dev";
  8141. + qcom,msm-dai-q6-dev-id = <241>;
  8142. + };
  8143. +
  8144. + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
  8145. + compatible = "qcom,msm-dai-q6-dev";
  8146. + qcom,msm-dai-q6-dev-id = <240>;
  8147. + };
  8148. +
  8149. + incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
  8150. + compatible = "qcom,msm-dai-q6-dev";
  8151. + qcom,msm-dai-q6-dev-id = <32771>;
  8152. + };
  8153. +
  8154. + incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
  8155. + compatible = "qcom,msm-dai-q6-dev";
  8156. + qcom,msm-dai-q6-dev-id = <32772>;
  8157. + };
  8158. +
  8159. + incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
  8160. + compatible = "qcom,msm-dai-q6-dev";
  8161. + qcom,msm-dai-q6-dev-id = <32773>;
  8162. + };
  8163. +
  8164. + incall_music2_rx: qcom,msm-dai-q6-incall-music-2-rx {
  8165. + compatible = "qcom,msm-dai-q6-dev";
  8166. + qcom,msm-dai-q6-dev-id = <32770>;
  8167. + };
  8168. + };
  8169. +
  8170. + dai_pri_auxpcm: qcom,msm-pri-auxpcm {
  8171. + compatible = "qcom,msm-auxpcm-dev";
  8172. + qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  8173. + qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  8174. + qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  8175. + qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  8176. + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
  8177. + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
  8178. + qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  8179. + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  8180. + qcom,msm-auxpcm-interface = "primary";
  8181. + };
  8182. +
  8183. + dai_sec_auxpcm: qcom,msm-sec-auxpcm {
  8184. + compatible = "qcom,msm-auxpcm-dev";
  8185. + qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
  8186. + qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
  8187. + qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
  8188. + qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
  8189. + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
  8190. + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
  8191. + qcom,msm-cpudai-auxpcm-data = <0>, <0>;
  8192. + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
  8193. + qcom,msm-auxpcm-interface = "secondary";
  8194. + };
  8195. +
  8196. + qcom,msm-dai-mi2s {
  8197. + compatible = "qcom,msm-dai-mi2s";
  8198. + dai_mi2s: qcom,msm-dai-q6-mi2s-prim {
  8199. + compatible = "qcom,msm-dai-q6-mi2s";
  8200. + qcom,msm-dai-q6-mi2s-dev-id = <0>;
  8201. +//#ifdef VENDOR_EDIT
  8202. +/*zhiguang.su@MultiMedia.AudioDrv ,changed for quat i2s*/
  8203. +
  8204. + qcom,msm-mi2s-rx-lines = <1>;
  8205. + qcom,msm-mi2s-tx-lines = <2>;
  8206. + };
  8207. +
  8208. + qua_mi2s: qcom,msm-dai-q6-mi2s-quat {
  8209. + compatible = "qcom,msm-dai-q6-mi2s";
  8210. + qcom,msm-dai-q6-mi2s-dev-id = <3>;
  8211. + qcom,msm-mi2s-rx-lines = <1>;
  8212. + qcom,msm-mi2s-tx-lines = <2>;
  8213. + };
  8214. +//#endif
  8215. + };
  8216. +
  8217. + hostless: qcom,msm-pcm-hostless {
  8218. + compatible = "qcom,msm-pcm-hostless";
  8219. + };
  8220. +
  8221. + tsens: tsens@fc4a8000 {
  8222. + compatible = "qcom,msm8994-tsens";
  8223. + reg = <0xfc4a8000 0x2000>,
  8224. + <0xfc4bc000 0x1000>;
  8225. + reg-names = "tsens_physical", "tsens_eeprom_physical";
  8226. + interrupts = <0 184 0>;
  8227. + interrupt-names = "tsens-upper-lower";
  8228. + qcom,sensors = <16>;
  8229. + qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200>;
  8230. + };
  8231. +
  8232. + qcom_tzlog: tz-log@fe87f720 {
  8233. + compatible = "qcom,tz-log";
  8234. + reg = <0xfe87f720 0x2000>;
  8235. + };
  8236. +
  8237. + qcom_crypto1fde: qcrypto1fde@fd440000 {
  8238. + compatible = "qcom,qcrypto";
  8239. + reg = <0xfd440000 0x20000>,
  8240. + <0xfd444000 0x9000>;
  8241. + reg-names = "crypto-base","crypto-bam-base";
  8242. + interrupts = <0 236 0>;
  8243. + qcom,bam-pipe-pair = <2>;
  8244. + qcom,ce-hw-instance = <1>;
  8245. + qcom,ce-device = <0>;
  8246. + qcom,clk-mgmt-sus-res;
  8247. + qcom,msm-bus,name = "qcrypto-noc";
  8248. + qcom,msm-bus,num-cases = <2>;
  8249. + qcom,msm-bus,num-paths = <1>;
  8250. + qcom,msm-bus,vectors-KBps =
  8251. + <55 512 0 0>,
  8252. + <55 512 393600 393600>;
  8253. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  8254. + clocks = <&clock_rpm clk_qcrypto_ce2_clk>,
  8255. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  8256. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  8257. + qcom,support-core-clk-only;
  8258. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  8259. + qcom,use-sw-aes-xts-algo;
  8260. + qcom,use-sw-aes-ccm-algo;
  8261. + qcom,use-sw-ahash-algo;
  8262. + qcom,ce-opp-freq = <171430000>;
  8263. + };
  8264. +
  8265. + qcom_crypto2fde: qcrypto2fde@0xfd3c0000 {
  8266. + compatible = "qcom,qcrypto";
  8267. + reg = <0xfd3c0000 0x20000>,
  8268. + <0xfd3c4000 0x9000>;
  8269. + reg-names = "crypto-base","crypto-bam-base";
  8270. + interrupts = <0 297 0>;
  8271. + qcom,bam-pipe-pair = <2>;
  8272. + qcom,ce-hw-instance = <2>;
  8273. + qcom,ce-device = <0>;
  8274. + qcom,clk-mgmt-sus-res;
  8275. + qcom,msm-bus,name = "qcrypto-noc";
  8276. + qcom,msm-bus,num-cases = <2>;
  8277. + qcom,msm-bus,num-paths = <1>;
  8278. + qcom,msm-bus,vectors-KBps =
  8279. + <55 512 0 0>,
  8280. + <55 512 393600 393600>;
  8281. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  8282. + clocks = <&clock_rpm clk_qcrypto_ce3_clk>,
  8283. + <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
  8284. + <&clock_rpm clk_gcc_ce3_axi_m_clk>;
  8285. + qcom,support-core-clk-only;
  8286. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  8287. + qcom,use-sw-aes-xts-algo;
  8288. + qcom,use-sw-aes-ccm-algo;
  8289. + qcom,use-sw-ahash-algo;
  8290. + qcom,ce-opp-freq = <171430000>;
  8291. + };
  8292. +
  8293. + qcom_crypto1pfe: qcrypto1pfe@fd440000 {
  8294. + compatible = "qcom,qcrypto";
  8295. + reg = <0xfd440000 0x20000>,
  8296. + <0xfd444000 0x9000>;
  8297. + reg-names = "crypto-base","crypto-bam-base";
  8298. + interrupts = <0 236 0>;
  8299. + qcom,bam-pipe-pair = <0>;
  8300. + qcom,ce-hw-instance = <1>;
  8301. + qcom,ce-device = <1>;
  8302. + qcom,clk-mgmt-sus-res;
  8303. + qcom,msm-bus,name = "qcrypto-noc";
  8304. + qcom,msm-bus,num-cases = <2>;
  8305. + qcom,msm-bus,num-paths = <1>;
  8306. + qcom,msm-bus,vectors-KBps =
  8307. + <55 512 0 0>,
  8308. + <55 512 393600 393600>;
  8309. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  8310. + clocks = <&clock_rpm clk_qcrypto_ce2_clk>,
  8311. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  8312. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  8313. + qcom,support-core-clk-only;
  8314. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  8315. + qcom,use-sw-aes-xts-algo;
  8316. + qcom,use-sw-aes-ccm-algo;
  8317. + qcom,use-sw-ahash-algo;
  8318. + qcom,ce-opp-freq = <171430000>;
  8319. + };
  8320. +
  8321. + qcom_crypto2pfe: qcrypto2pfe@0xfd3c0000 {
  8322. + compatible = "qcom,qcrypto";
  8323. + reg = <0xfd3c0000 0x20000>,
  8324. + <0xfd3c4000 0x9000>;
  8325. + reg-names = "crypto-base","crypto-bam-base";
  8326. + interrupts = <0 297 0>;
  8327. + qcom,bam-pipe-pair = <0>;
  8328. + qcom,ce-hw-instance = <2>;
  8329. + qcom,ce-device = <1>;
  8330. + qcom,clk-mgmt-sus-res;
  8331. + qcom,msm-bus,name = "qcrypto-noc";
  8332. + qcom,msm-bus,num-cases = <2>;
  8333. + qcom,msm-bus,num-paths = <1>;
  8334. + qcom,msm-bus,vectors-KBps =
  8335. + <55 512 0 0>,
  8336. + <55 512 393600 393600>;
  8337. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  8338. + clocks = <&clock_rpm clk_qcrypto_ce3_clk>,
  8339. + <&clock_rpm clk_gcc_ce3_ahb_m_clk>,
  8340. + <&clock_rpm clk_gcc_ce3_axi_m_clk>;
  8341. + qcom,support-core-clk-only;
  8342. + qcom,use-sw-aes-cbc-ecb-ctr-algo;
  8343. + qcom,use-sw-aes-xts-algo;
  8344. + qcom,use-sw-aes-ccm-algo;
  8345. + qcom,use-sw-ahash-algo;
  8346. + qcom,ce-opp-freq = <171430000>;
  8347. + };
  8348. +
  8349. + qcom_cedev: qcedev@fd440000 {
  8350. + compatible = "qcom,qcedev";
  8351. + reg = <0xfd440000 0x20000>,
  8352. + <0xfd444000 0x9000>;
  8353. + reg-names = "crypto-base","crypto-bam-base";
  8354. + interrupts = <0 236 0>;
  8355. + qcom,bam-pipe-pair = <1>;
  8356. + qcom,ce-hw-instance = <0>;
  8357. + qcom,ce-device = <0>;
  8358. + qcom,msm-bus,name = "qcedev-noc";
  8359. + qcom,msm-bus,num-cases = <2>;
  8360. + qcom,msm-bus,num-paths = <1>;
  8361. + qcom,msm-bus,vectors-KBps =
  8362. + <55 512 0 0>,
  8363. + <55 512 393600 393600>;
  8364. + clock-names = "core_clk_src", "iface_clk", "bus_clk";
  8365. + clocks = <&clock_rpm clk_qcedev_ce2_clk>,
  8366. + <&clock_rpm clk_gcc_ce2_ahb_m_clk>,
  8367. + <&clock_rpm clk_gcc_ce2_axi_m_clk>;
  8368. + qcom,support-core-clk-only;
  8369. + qcom,ce-opp-freq = <171430000>;
  8370. + };
  8371. +
  8372. + qcom,qseecom@6500000{
  8373. + compatible = "qcom,qseecom";
  8374. + reg = <0x0E900000 0x1900000>;//reg = <0x6500000 0x500000>; ----> <0x0E700000 0x700000>; ----> <0x0E900000 0x1900000>; /*VENDOR_EDIT changhua add more memory for fpc1150 and alipay in TZ*/
  8375. + reg-names = "secapp-region";
  8376. + qcom,disk-encrypt-pipe-pair = <2>;
  8377. + qcom,file-encrypt-pipe-pair = <0>;
  8378. + qcom,support-multiple-ce-hw-instance;
  8379. + qcom,hlos-num-ce-hw-instances = <2>;
  8380. + qcom,hlos-ce-hw-instance = <1 2>;
  8381. + qcom,qsee-ce-hw-instance = <0>;
  8382. + qcom,msm-bus,name = "qseecom-noc";
  8383. + qcom,msm-bus,num-cases = <4>;
  8384. + qcom,msm-bus,num-paths = <1>;
  8385. + qcom,support-fde;
  8386. + qcom,support-pfe;
  8387. + qcom,no-clock-support;
  8388. + qcom,msm-bus,vectors-KBps =
  8389. + <55 512 0 0>,
  8390. + <55 512 0 0>,
  8391. + <55 512 120000 1200000>,
  8392. + <55 512 393600 3936000>;
  8393. + clock-names = "core_clk", "ufs_core_clk_src", "ufs_core_clk",
  8394. + "ufs_bus_clk", "ufs_iface_clk";
  8395. + clocks = <&clock_rpm clk_qseecom_ce1_clk>,
  8396. + <&clock_gcc clk_ufs_axi_clk_src>,
  8397. + <&clock_gcc clk_gcc_ufs_axi_clk>,
  8398. + <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
  8399. + <&clock_gcc clk_gcc_ufs_ahb_clk>;
  8400. + qcom,ce-opp-freq = <171430000>;
  8401. + };
  8402. +
  8403. + qcom,sensor-information {
  8404. + compatible = "qcom,sensor-information";
  8405. + sensor_information0: qcom,sensor-information@0 {
  8406. + qcom,sensor-type = "tsens";
  8407. + qcom,sensor-name = "tsens_tz_sensor0";
  8408. + };
  8409. +
  8410. + sensor_information1: qcom,sensor-information@1 {
  8411. + qcom,sensor-type = "tsens";
  8412. + qcom,sensor-name = "tsens_tz_sensor1";
  8413. + };
  8414. +
  8415. + sensor_information2: qcom,sensor-information@2 {
  8416. + qcom,sensor-type = "tsens";
  8417. + qcom,sensor-name = "tsens_tz_sensor2";
  8418. + qcom,alias-name = "pop_mem";
  8419. + };
  8420. +
  8421. + sensor_information3: qcom,sensor-information@3 {
  8422. + qcom,sensor-type = "tsens";
  8423. + qcom,sensor-name = "tsens_tz_sensor3";
  8424. + };
  8425. +
  8426. + sensor_information4: qcom,sensor-information@4 {
  8427. + qcom,sensor-type = "tsens";
  8428. + qcom,sensor-name = "tsens_tz_sensor4";
  8429. + };
  8430. +
  8431. + sensor_information5: qcom,sensor-information@5 {
  8432. + qcom,sensor-type = "tsens";
  8433. + qcom,sensor-name = "tsens_tz_sensor5";
  8434. + };
  8435. +
  8436. + sensor_information6: qcom,sensor-information@6 {
  8437. + qcom,sensor-type = "tsens";
  8438. + qcom,sensor-name = "tsens_tz_sensor6";
  8439. + qcom,alias-name = "cpu7";
  8440. + };
  8441. +
  8442. + sensor_information7: qcom,sensor-information@7 {
  8443. + qcom,sensor-type = "tsens";
  8444. + qcom,sensor-name = "tsens_tz_sensor7";
  8445. + qcom,alias-name = "cpu0";
  8446. + };
  8447. +
  8448. + sensor_information8: qcom,sensor-information@8 {
  8449. + qcom,sensor-type = "tsens";
  8450. + qcom,sensor-name = "tsens_tz_sensor8";
  8451. + qcom,alias-name = "cpu1";
  8452. + };
  8453. +
  8454. + sensor_information9: qcom,sensor-information@9 {
  8455. + qcom,sensor-type = "tsens";
  8456. + qcom,sensor-name = "tsens_tz_sensor9";
  8457. + qcom,alias-name = "cpu2";
  8458. + };
  8459. +
  8460. + sensor_information10: qcom,sensor-information@10 {
  8461. + qcom,sensor-type = "tsens";
  8462. + qcom,sensor-name = "tsens_tz_sensor10";
  8463. + qcom,alias-name = "cpu3";
  8464. + };
  8465. +
  8466. + sensor_information11: qcom,sensor-information@11 {
  8467. + qcom,sensor-type = "tsens";
  8468. + qcom,sensor-name = "tsens_tz_sensor11";
  8469. + };
  8470. +
  8471. + sensor_information12: qcom,sensor-information@12 {
  8472. + qcom,sensor-type = "tsens";
  8473. + qcom,sensor-name = "tsens_tz_sensor12";
  8474. + qcom,alias-name = "gpu";
  8475. + };
  8476. +
  8477. + sensor_information13: qcom,sensor-information@13 {
  8478. + qcom,sensor-type = "tsens";
  8479. + qcom,sensor-name = "tsens_tz_sensor13";
  8480. + qcom,alias-name = "cpu4";
  8481. + };
  8482. +
  8483. + sensor_information14: qcom,sensor-information@14 {
  8484. + qcom,sensor-type = "tsens";
  8485. + qcom,sensor-name = "tsens_tz_sensor14";
  8486. + qcom,alias-name = "cpu5";
  8487. + };
  8488. +
  8489. + sensor_information15: qcom,sensor-information@15 {
  8490. + qcom,sensor-type = "tsens";
  8491. + qcom,sensor-name = "tsens_tz_sensor15";
  8492. + qcom,alias-name = "cpu6";
  8493. + };
  8494. +
  8495. + sensor_information16: qcom,sensor-information@16 {
  8496. + qcom,sensor-type = "alarm";
  8497. + qcom,sensor-name = "pm8994_tz";
  8498. + qcom,scaling-factor = <1000>;
  8499. + };
  8500. +
  8501. + sensor_information17: qcom,sensor-information@17 {
  8502. + qcom,sensor-type = "adc";
  8503. + qcom,sensor-name = "msm_therm";
  8504. + };
  8505. +
  8506. + sensor_information18: qcom,sensor-information@18 {
  8507. + qcom,sensor-type = "adc";
  8508. + qcom,sensor-name = "emmc_therm";
  8509. + };
  8510. +
  8511. + sensor_information19: qcom,sensor-information@19 {
  8512. + qcom,sensor-type = "adc";
  8513. + qcom,sensor-name = "pa_therm0";
  8514. + };
  8515. +
  8516. + sensor_information20: qcom,sensor-information@20 {
  8517. + qcom,sensor-type = "adc";
  8518. + qcom,sensor-name = "pa_therm1";
  8519. + };
  8520. +
  8521. + sensor_information21: qcom,sensor-information@21 {
  8522. + qcom,sensor-type = "adc";
  8523. + qcom,sensor-name = "quiet_therm";
  8524. + };
  8525. +
  8526. + sensor_information22: qcom,sensor-information@22 {
  8527. + qcom,sensor-type = "llm";
  8528. + qcom,sensor-name = "LLM_IA57";
  8529. + };
  8530. +
  8531. + sensor_information23: qcom,sensor-information-23 {
  8532. + qcom,sensor-type = "adc";
  8533. + qcom,sensor-name = "battery";
  8534. + };
  8535. + };
  8536. +
  8537. + qcom,msm-thermal {
  8538. + compatible = "qcom,msm-thermal";
  8539. + qcom,sensor-id = <7>;
  8540. + qcom,poll-ms = <250>;
  8541. + qcom,limit-temp = <60>;
  8542. + qcom,temp-hysteresis = <10>;
  8543. + qcom,therm-reset-temp = <115>;
  8544. + qcom,freq-step = <2>;
  8545. + qcom,freq-control-mask = <0xff>;
  8546. + qcom,core-limit-temp = <80>;
  8547. + qcom,core-temp-hysteresis = <10>;
  8548. + qcom,core-control-mask = <0xfe>;
  8549. + qcom,hotplug-temp = <105>;
  8550. + qcom,hotplug-temp-hysteresis = <40>;
  8551. + qcom,cpu-sensors = "tsens_tz_sensor7", "tsens_tz_sensor8",
  8552. + "tsens_tz_sensor9", "tsens_tz_sensor10",
  8553. + "tsens_tz_sensor13", "tsens_tz_sensor14",
  8554. + "tsens_tz_sensor15", "tsens_tz_sensor6";
  8555. + qcom,freq-mitigation-temp = <95>;
  8556. + qcom,freq-mitigation-temp-hysteresis = <10>;
  8557. + qcom,freq-mitigation-value = <960000>;
  8558. + qcom,freq-mitigation-control-mask = <0xF0>;
  8559. + qcom,online-hotplug-core;
  8560. + qcom,synchronous-cluster-id = <0 1>;
  8561. + qcom,mx-restriction-temp = <5>;
  8562. + qcom,mx-restriction-temp-hysteresis = <10>;
  8563. + qcom,mx-retention-min = <3>;
  8564. + vdd-mx-supply = <&pm8994_s2_corner>;
  8565. +
  8566. + qcom,vdd-restriction-temp = <5>;
  8567. + qcom,vdd-restriction-temp-hysteresis = <10>;
  8568. +
  8569. + vdd-dig-supply = <&pm8994_s1_floor_corner>;
  8570. + vdd-gfx-supply = <&pmi8994_s2_floor_corner>;
  8571. +
  8572. + qcom,vdd-dig-rstr{
  8573. + qcom,vdd-rstr-reg = "vdd-dig";
  8574. + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  8575. + qcom,min-level = <1>; /* No Request */
  8576. + };
  8577. +
  8578. + qcom,vdd-gfx-rstr{
  8579. + qcom,vdd-rstr-reg = "vdd-gfx";
  8580. + qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
  8581. + qcom,min-level = <1>; /* No Request */
  8582. + };
  8583. +
  8584. + msm_thermal_freq: qcom,vdd-apps-rstr{
  8585. + qcom,vdd-rstr-reg = "vdd-apps";
  8586. + qcom,levels = <302400 600000 600000>;
  8587. + qcom,freq-req;
  8588. + };
  8589. + };
  8590. +
  8591. + qcom,bcl {
  8592. + compatible = "qcom,bcl";
  8593. + qcom,bcl-enable;
  8594. + qcom,bcl-framework-interface;
  8595. + qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
  8596. + qcom,bcl-hotplug-list = <&CPU6 &CPU7>;
  8597. + qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
  8598. + qcom,ibat-monitor {
  8599. + qcom,low-threshold-uamp = <3400000>;
  8600. + qcom,high-threshold-uamp = <4200000>;
  8601. + qcom,mitigation-freq-khz = <768000>;
  8602. + qcom,vph-high-threshold-uv = <3500000>;
  8603. + qcom,vph-low-threshold-uv = <3300000>;
  8604. + qcom,soc-low-threshold = <20>;
  8605. + qcom,thermal-handle = <&msm_thermal_freq>;
  8606. + };
  8607. + };
  8608. +
  8609. + cnss: qcom,cnss@06300000 {
  8610. + compatible = "qcom,cnss";
  8611. + reg = <0x06300000 0x200000>;
  8612. + reg-names = "ramdump";
  8613. + wlan-en-gpio = <&msm_gpio 113 0>;
  8614. + vdd-wlan-supply = <&bt_vreg>;
  8615. + vdd-wlan-io-supply = <&pm8994_s4>;
  8616. + vdd-wlan-xtal-supply = <&pm8994_l30>;
  8617. + qcom,notify-modem-status;
  8618. + pinctrl-names = "default";
  8619. + pinctrl-0 = <&cnss_default>;
  8620. + qcom,wlan-rc-num = <1>;
  8621. + qcom,wlan-uart-access;
  8622. +
  8623. + qcom,msm-bus,name = "msm-cnss";
  8624. + qcom,msm-bus,num-cases = <4>;
  8625. + qcom,msm-bus,num-paths = <1>;
  8626. + qcom,msm-bus,vectors-KBps =
  8627. + <100 512 0 0>, /* No vote */
  8628. + <100 512 6250 200000>, /* 50 Mbps */
  8629. + <100 512 25000 200000>, /* 200 Mbps */
  8630. + <100 512 100000 200000>; /* 800 Mbps */
  8631. + };
  8632. +
  8633. + audio_heap {
  8634. + compatible = "qcom,msm-shared-memory";
  8635. + qcom,proc-id = <1>;
  8636. + linux,contiguous-region = <&audio_mem>;
  8637. + };
  8638. +
  8639. + adsp_heap {
  8640. + compatible = "qcom,msm-shared-memory";
  8641. + qcom,proc-id = <1>;
  8642. + linux,contiguous-region = <&adsp_mem>;
  8643. + };
  8644. +
  8645. + qcom,msm-core@fc4b8000 {
  8646. + compatible = "qcom,apss-core-ea";
  8647. + reg = <0xfc4b8000 0x1000>;
  8648. + qcom,low-hyst-temp = <10>;
  8649. + qcom,high-hyst-temp = <5>;
  8650. + qcom,polling-interval = <50>;
  8651. +
  8652. + qcom,core-mapping {
  8653. + qcom,cpu0-chars {
  8654. + qcom,sensor = <&sensor_information7>;
  8655. + qcom,cpu-name = <&CPU0>;
  8656. + };
  8657. +
  8658. + qcom,cpu1-chars {
  8659. + qcom,sensor = <&sensor_information8>;
  8660. + qcom,cpu-name = <&CPU1>;
  8661. + };
  8662. +
  8663. + qcom,cpu2-chars {
  8664. + qcom,sensor = <&sensor_information9>;
  8665. + qcom,cpu-name = <&CPU2>;
  8666. + };
  8667. +
  8668. + qcom,cpu3-chars {
  8669. + qcom,sensor = <&sensor_information10>;
  8670. + qcom,cpu-name = <&CPU3>;
  8671. + };
  8672. +
  8673. + qcom,cpu4-chars {
  8674. + qcom,sensor = <&sensor_information13>;
  8675. + qcom,cpu-name = <&CPU4>;
  8676. + };
  8677. +
  8678. + qcom,cpu5-chars {
  8679. + qcom,sensor = <&sensor_information14>;
  8680. + qcom,cpu-name = <&CPU5>;
  8681. + };
  8682. +
  8683. + qcom,cpu6-chars {
  8684. + qcom,sensor = <&sensor_information15>;
  8685. + qcom,cpu-name = <&CPU6>;
  8686. + };
  8687. +
  8688. + qcom,cpu7-chars {
  8689. + qcom,sensor = <&sensor_information6>;
  8690. + qcom,cpu-name = <&CPU7>;
  8691. + };
  8692. + };
  8693. + };
  8694. +
  8695. + qcom,system-health-monitor {
  8696. + compatible = "qcom,system-health-monitor";
  8697. +
  8698. + qcom,system-health-monitor-modem {
  8699. + qcom,subsys-name = "msm_mpss";
  8700. + qcom,ssrestart-string = "modem";
  8701. + };
  8702. + };
  8703. +
  8704. + cpuss_dump {
  8705. + compatible = "qcom,cpuss-dump";
  8706. + qcom,itlb_dump100 {
  8707. + qcom,dump-node = <&L1_itlb_100>;
  8708. + qcom,dump-id = <0x24>;
  8709. + };
  8710. + qcom,itlb_dump101 {
  8711. + qcom,dump-node = <&L1_itlb_101>;
  8712. + qcom,dump-id = <0x25>;
  8713. + };
  8714. + qcom,itlb_dump102 {
  8715. + qcom,dump-node = <&L1_itlb_102>;
  8716. + qcom,dump-id = <0x26>;
  8717. + };
  8718. + qcom,itlb_dump103 {
  8719. + qcom,dump-node = <&L1_itlb_103>;
  8720. + qcom,dump-id = <0x27>;
  8721. + };
  8722. + qcom,dtlb_dump100 {
  8723. + qcom,dump-node = <&L1_dtlb_100>;
  8724. + qcom,dump-id = <0x44>;
  8725. + };
  8726. + qcom,dtlb_dump101 {
  8727. + qcom,dump-node = <&L1_dtlb_101>;
  8728. + qcom,dump-id = <0x45>;
  8729. + };
  8730. + qcom,dtlb_dump102 {
  8731. + qcom,dump-node = <&L1_dtlb_102>;
  8732. + qcom,dump-id = <0x46>;
  8733. + };
  8734. + qcom,dtlb_dump103 {
  8735. + qcom,dump-node = <&L1_dtlb_103>;
  8736. + qcom,dump-id = <0x47>;
  8737. + };
  8738. + qcom,l2_tlb_dump0 {
  8739. + qcom,dump-node = <&L2_tlb_0>;
  8740. + qcom,dump-id = <0x120>;
  8741. + };
  8742. + qcom,l2_tlb_dump100 {
  8743. + qcom,dump-node = <&L2_tlb_1>;
  8744. + qcom,dump-id = <0x121>;
  8745. + };
  8746. + qcom,l2_dump0 {
  8747. + qcom,dump-node = <&L2_0>; /* L2 cache dump for A53 cluster */
  8748. + qcom,dump-id = <0xC0>;
  8749. + };
  8750. + qcom,l2_dump1 {
  8751. + qcom,dump-node = <&L2_1>; /* L2 cache dumo for A57 cluster */
  8752. + qcom,dump-id = <0xC1>;
  8753. + };
  8754. + qcom,l1_i_cache0 {
  8755. + qcom,dump-node = <&L1_I_0>;
  8756. + qcom,dump-id = <0x60>;
  8757. + };
  8758. + qcom,l1_i_cache1 {
  8759. + qcom,dump-node = <&L1_I_1>;
  8760. + qcom,dump-id = <0x61>;
  8761. + };
  8762. + qcom,l1_i_cache2 {
  8763. + qcom,dump-node = <&L1_I_2>;
  8764. + qcom,dump-id = <0x62>;
  8765. + };
  8766. + qcom,l1_i_cache3 {
  8767. + qcom,dump-node = <&L1_I_3>;
  8768. + qcom,dump-id = <0x63>;
  8769. + };
  8770. + qcom,l1_i_cache100 {
  8771. + qcom,dump-node = <&L1_I_100>;
  8772. + qcom,dump-id = <0x64>;
  8773. + };
  8774. + qcom,l1_i_cache101 {
  8775. + qcom,dump-node = <&L1_I_101>;
  8776. + qcom,dump-id = <0x65>;
  8777. + };
  8778. + qcom,l1_i_cache102 {
  8779. + qcom,dump-node = <&L1_I_102>;
  8780. + qcom,dump-id = <0x66>;
  8781. + };
  8782. + qcom,l1_i_cache103 {
  8783. + qcom,dump-node = <&L1_I_103>;
  8784. + qcom,dump-id = <0x67>;
  8785. + };
  8786. + qcom,l1_d_cache0 {
  8787. + qcom,dump-node = <&L1_D_0>;
  8788. + qcom,dump-id = <0x80>;
  8789. + };
  8790. + qcom,l1_d_cache1 {
  8791. + qcom,dump-node = <&L1_D_1>;
  8792. + qcom,dump-id = <0x81>;
  8793. + };
  8794. + qcom,l1_d_cache2 {
  8795. + qcom,dump-node = <&L1_D_2>;
  8796. + qcom,dump-id = <0x82>;
  8797. + };
  8798. + qcom,l1_d_cache3 {
  8799. + qcom,dump-node = <&L1_D_3>;
  8800. + qcom,dump-id = <0x83>;
  8801. + };
  8802. + qcom,l1_d_cache100 {
  8803. + qcom,dump-node = <&L1_D_100>;
  8804. + qcom,dump-id = <0x84>;
  8805. + };
  8806. + qcom,l1_d_cache101 {
  8807. + qcom,dump-node = <&L1_D_101>;
  8808. + qcom,dump-id = <0x85>;
  8809. + };
  8810. + qcom,l1_d_cache102 {
  8811. + qcom,dump-node = <&L1_D_102>;
  8812. + qcom,dump-id = <0x86>;
  8813. + };
  8814. + qcom,l1_d_cache103 {
  8815. + qcom,dump-node = <&L1_D_103>;
  8816. + qcom,dump-id = <0x87>;
  8817. + };
  8818. + };
  8819. +
  8820. + qcom,avtimer@fe09c000 {
  8821. + compatible = "qcom,avtimer";
  8822. + reg = <0xFE09C00C 0x4>,
  8823. + <0xFE09C010 0x4>;
  8824. + reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
  8825. + qcom,clk_div = <27>;
  8826. + };
  8827. +
  8828. + cci@f9100000 {
  8829. + compatible = "arm,cci-400";
  8830. + #address-cells = <1>;
  8831. + #size-cells = <1>;
  8832. + reg = <0xf9100000 0x1000>;
  8833. + ranges = <0x0 0xf9100000 0x10000>;
  8834. + hw-version = <8>;
  8835. +
  8836. + pmu@a000 {
  8837. + compatible = "arm,cci-400-pmu";
  8838. + reg = <0x9000 0x5000>;
  8839. + interrupts = <0 344 0>,
  8840. + <0 344 0>,
  8841. + <0 344 0>,
  8842. + <0 344 0>,
  8843. + <0 344 0>;
  8844. + };
  8845. +
  8846. + };
  8847. +};
  8848. +
  8849. +&gdsc_usb30 {
  8850. + reg = <0xfc4003c4 0x4>;
  8851. + status = "ok";
  8852. +};
  8853. +
  8854. +&gdsc_pcie_0 {
  8855. + status = "ok";
  8856. +};
  8857. +
  8858. +&gdsc_pcie_1 {
  8859. + status = "ok";
  8860. +};
  8861. +
  8862. +&gdsc_ufs {
  8863. + status = "ok";
  8864. +};
  8865. +
  8866. +&gdsc_venus {
  8867. + clock-names = "ocmem_clk", "bus_clk", "core_clk";
  8868. + clocks = <&clock_mmss clk_venus0_ocmemnoc_clk>,
  8869. + <&clock_mmss clk_venus0_axi_clk>,
  8870. + <&clock_mmss clk_venus0_vcodec0_clk>;
  8871. + status = "ok";
  8872. +};
  8873. +
  8874. +&gdsc_venus_core0 {
  8875. + qcom,support-hw-trigger;
  8876. + clock-names = "core0_clk";
  8877. + clocks = <&clock_mmss clk_venus0_core0_vcodec_clk>;
  8878. + status = "ok";
  8879. +};
  8880. +
  8881. +&gdsc_venus_core1 {
  8882. + qcom,support-hw-trigger;
  8883. + clock-names = "core1_clk";
  8884. + clocks = <&clock_mmss clk_venus0_core1_vcodec_clk>;
  8885. + status = "ok";
  8886. +};
  8887. +
  8888. +&gdsc_venus_core2 {
  8889. + qcom,support-hw-trigger;
  8890. + clock-names = "core2_clk";
  8891. + clocks = <&clock_mmss clk_venus0_core2_vcodec_clk>;
  8892. + status = "ok";
  8893. +};
  8894. +
  8895. +&gdsc_mdss {
  8896. + clock-names = "bus_clk", "core_clk";
  8897. + clocks = <&clock_mmss clk_mdss_axi_clk>,
  8898. + <&clock_mmss clk_mdss_mdp_clk>;
  8899. + status = "ok";
  8900. +};
  8901. +
  8902. +&gdsc_camss_top {
  8903. + clock-names = "csi0_clk", "csi1_clk", "bus_clk";
  8904. + clocks = <&clock_mmss clk_camss_csi_vfe0_clk>,
  8905. + <&clock_mmss clk_camss_csi_vfe1_clk>,
  8906. + <&clock_mmss clk_camss_micro_ahb_clk>;
  8907. + status = "ok";
  8908. +};
  8909. +
  8910. +&gdsc_jpeg {
  8911. + clock-names = "bus_clk", "core0_clk", "core1_clk", "core2_clk";
  8912. + clocks = <&clock_mmss clk_camss_jpeg_jpeg_axi_clk>,
  8913. + <&clock_mmss clk_camss_jpeg_jpeg0_clk>,
  8914. + <&clock_mmss clk_camss_jpeg_jpeg1_clk>,
  8915. + <&clock_mmss clk_camss_jpeg_jpeg2_clk>;
  8916. + parent-supply = <&gdsc_camss_top>;
  8917. + status = "ok";
  8918. +};
  8919. +
  8920. +&gdsc_vfe {
  8921. + clock-names = "bus_clk";
  8922. + clocks = <&clock_mmss clk_camss_vfe_vfe_axi_clk>;
  8923. + parent-supply = <&gdsc_camss_top>;
  8924. + status = "ok";
  8925. +};
  8926. +
  8927. +&gdsc_cpp {
  8928. + clock-names = "bus_clk", "core_clk";
  8929. + clocks = <&clock_mmss clk_camss_vfe_cpp_axi_clk>,
  8930. + <&clock_mmss clk_camss_vfe_cpp_clk>;
  8931. + parent-supply = <&gdsc_camss_top>;
  8932. + status = "ok";
  8933. +};
  8934. +
  8935. +&gdsc_fd {
  8936. + clock-names = "bus_clk", "core_clk";
  8937. + clocks = <&clock_mmss clk_fd_axi_clk>,
  8938. + <&clock_mmss clk_fd_core_clk>;
  8939. + status = "ok";
  8940. +};
  8941. +
  8942. +&gdsc_oxili_cx {
  8943. + status = "ok";
  8944. +};
  8945. +
  8946. +&gdsc_oxili_gx {
  8947. + clock-names = "core_clk";
  8948. + clocks = <&clock_mmss clk_oxili_gfx3d_clk>;
  8949. + status = "ok";
  8950. + parent-supply = <&pmi8994_s2_corner>;
  8951. +};
  8952. +
  8953. +#include "msm-pm8994-rpm-regulator.dtsi"
  8954. +#include "msm-pm8994.dtsi"
  8955. +#include "msm-pmi8994.dtsi"
  8956. +#include "msm8994-regulator.dtsi"
  8957. +#include "msm8994-ion.dtsi"
  8958. +#include "msm8994-iommu.dtsi"
  8959. +#include "msm8994-iommu-domains.dtsi"
  8960. +#include "msm8994-camera.dtsi"
  8961. +#include "msm8994-gpu.dtsi"
  8962. +#include "dsi-panel-sim-video.dtsi"
  8963. +#include "dsi-panel-sim-dualmipi0-video.dtsi"
  8964. +#include "dsi-panel-sim-dualmipi1-video.dtsi"
  8965. +#include "dsi-panel-sim-cmd.dtsi"
  8966. +#include "dsi-panel-sim-dualmipi0-cmd.dtsi"
  8967. +#include "dsi-panel-sim-dualmipi1-cmd.dtsi"
  8968. diff --git a/arch/arm64/boot/dts/14049_HW_12/dsi-panel-jd35695-1080p-cmd.dtsi b/arch/arm64/boot/dts/14049_HW_12/dsi-panel-jd35695-1080p-cmd.dtsi
  8969. new file mode 100755
  8970. index 0000000..7dcd17d
  8971. --- /dev/null
  8972. +++ b/arch/arm64/boot/dts/14049_HW_12/dsi-panel-jd35695-1080p-cmd.dtsi
  8973. @@ -0,0 +1,212 @@
  8974. +/************************************************************
  8975. + * Copyright (c) 2013-2013 OPPO Mobile communication Corp.ltd.,
  8976. + * VENDOR_EDIT
  8977. + * Description: device tree for jdi cmd panel.
  8978. + * Version : 1.0
  8979. + * Date : 2013-12-12
  8980. + * Author : yangxinqin
  8981. + *
  8982. + * This program is free software; you can redistribute it and/or modify
  8983. + * it under the terms of the GNU General Public License version 2 and
  8984. + * only version 2 as published by the Free Software Foundation.
  8985. + *
  8986. + * This program is distributed in the hope that it will be useful,
  8987. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8988. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  8989. + * GNU General Public License for more details.
  8990. + */
  8991. +
  8992. +/*---------------------------------------------------------------------------
  8993. + * This file is autogenerated file using gcdb parser. Please do not edit it.
  8994. + * Update input XML file to add a new entry or update variable in this file
  8995. + * VERSION = "1.0"
  8996. + *---------------------------------------------------------------------------*/
  8997. +&mdss_mdp {
  8998. +dsi_jd35695_1080_cmd: qcom,mdss_dsi_jd35695_1080p_cmd {
  8999. + compatible = "qcom,mdss-dsi-panel";
  9000. + status = "ok";
  9001. + qcom,cont-splash-enabled;
  9002. + qcom,mdss-dsi-panel-name = "jd35695 1080p cmd mode dsi panel";
  9003. + qcom,mdss-dsi-panel-manufacture = "JDI";
  9004. + qcom,mdss-dsi-panel-version = "JD35695";
  9005. + qcom,mdss-dsi-backlight-version= "PMI8994";
  9006. + qcom,mdss-dsi-backlight-manufacture = "Qualcomm";
  9007. + qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
  9008. + qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
  9009. + qcom,mdss-dsi-panel-destination = "display_1";
  9010. + qcom,mdss-dsi-panel-framerate = <60>;
  9011. + qcom,mdss-dsi-virtual-channel-id = <0>;
  9012. + qcom,mdss-dsi-stream = <0>;
  9013. + qcom,mdss-dsi-panel-width = <1080>;
  9014. + qcom,mdss-dsi-panel-height = <1920>;
  9015. + qcom,mdss-dsi-h-front-porch = <100>;
  9016. + qcom,mdss-dsi-h-back-porch = <82>;
  9017. + qcom,mdss-dsi-h-pulse-width = <8>;
  9018. + qcom,mdss-dsi-h-sync-skew = <0>;
  9019. + qcom,mdss-dsi-v-back-porch = <7>;
  9020. + qcom,mdss-dsi-v-front-porch = <3>;
  9021. + qcom,mdss-dsi-v-pulse-width = <2>;
  9022. + qcom,mdss-dsi-h-left-border = <0>;
  9023. + qcom,mdss-dsi-h-right-border = <0>;
  9024. + qcom,mdss-dsi-v-top-border = <0>;
  9025. + qcom,mdss-dsi-v-bottom-border = <0>;
  9026. + qcom,mdss-dsi-bpp = <24>;
  9027. + qcom,mdss-dsi-underflow-color = <0x0000ff>;
  9028. + qcom,mdss-dsi-border-color = <0>;
  9029. + qcom,mdss-dsi-on-command = [
  9030. + 15 01 00 00 00 00 02 FF 10
  9031. + 15 01 00 00 00 00 02 35 00
  9032. + 39 01 00 00 00 00 05 2a 00 00 04 37
  9033. + 39 01 00 00 00 00 05 2b 00 00 07 7f
  9034. +
  9035. + 29 01 00 00 00 00 03 44 05 00
  9036. + 15 01 00 00 00 00 02 FF E0
  9037. + 15 01 00 00 00 00 02 B5 86
  9038. + 15 01 00 00 00 00 02 B6 77
  9039. + 15 01 00 00 00 00 02 B8 AD
  9040. + 15 01 00 00 00 00 02 FB 01
  9041. + 15 01 00 00 00 00 02 FF 10
  9042. +
  9043. + 15 01 00 00 00 00 02 36 03 //add for lcd rotater 180
  9044. + 15 01 00 00 00 00 02 FF 23
  9045. + 15 01 00 00 00 00 02 08 03
  9046. + 15 01 00 00 00 00 02 FF 10
  9047. + 15 01 00 00 00 00 02 51 FF
  9048. + 15 01 00 00 00 00 02 53 2C
  9049. + 15 01 00 00 00 00 02 55 02
  9050. +
  9051. + 15 01 00 00 00 00 02 FF 23
  9052. + 15 01 00 00 00 00 02 FB 01
  9053. + 15 01 00 00 00 00 02 05 24
  9054. + 15 01 00 00 00 00 02 01 84
  9055. + 15 01 00 00 00 00 02 FF 10
  9056. +
  9057. + 05 01 00 00 64 00 02 11 00
  9058. + 05 01 00 00 11 00 02 29 00
  9059. +
  9060. + ];
  9061. + qcom,mdss-dsi-off-command = [
  9062. + 15 01 00 00 00 00 02 FF 10
  9063. + 15 01 00 00 00 00 02 53 00
  9064. + 05 01 00 00 11 00 02 28 00
  9065. + 05 01 00 00 32 00 02 10 00];
  9066. +
  9067. + qcom,mdss-dsi-color-test-on-command=
  9068. + [
  9069. + 05 01 00 00 32 00 02 28 00
  9070. + 05 01 00 00 32 00 02 10 00
  9071. + 15 01 00 00 00 00 02 FF 24
  9072. + 15 01 00 00 00 00 02 EC 01
  9073. + 15 01 00 00 00 00 02 FF 20
  9074. + 15 01 00 00 00 00 02 67 4D];
  9075. +
  9076. +
  9077. + qcom,mdss-dsi-color-test-off-command =
  9078. + [
  9079. + 15 01 00 00 00 00 02 FF 24
  9080. + 15 01 00 00 00 00 02 EC 00
  9081. + 15 01 00 00 00 00 02 FF 10
  9082. + 15 01 00 00 00 00 02 35 00
  9083. + 29 01 00 00 00 00 03 44 05 00
  9084. + 15 01 00 00 00 00 02 FF 10
  9085. + 05 01 00 00 78 00 02 11 00
  9086. + 05 01 00 00 32 00 02 29 00];
  9087. +
  9088. + qcom,mdss-dsi-cabc-off-command = [15 01 00 00 10 00 02 55 00
  9089. + 05 01 00 00 10 00 02 29 00];
  9090. + qcom,mdss-dsi-cabc-ui-command = [15 01 00 00 10 00 02 55 01
  9091. + 05 01 00 00 10 00 02 29 00];
  9092. + qcom,mdss-dsi-cabc-still-image-command = [15 01 00 00 10 00 02 55 02
  9093. + 05 01 00 00 10 00 02 29 00];
  9094. + qcom,mdss-dsi-cabc-video-command = [15 01 00 00 10 00 02 55 03
  9095. + 05 01 00 00 10 00 02 29 00];
  9096. +
  9097. + qcom,mdss-dsi-on-command_shoushi = [
  9098. +
  9099. + 15 01 00 00 00 00 02 36 03 //add for lcd rotater 180
  9100. + 15 01 00 00 00 00 02 FF 23
  9101. + 15 01 00 00 00 00 02 08 03
  9102. + 15 01 00 00 00 00 02 FF 10
  9103. + 15 01 00 00 00 00 02 51 FF
  9104. + 15 01 00 00 00 00 02 53 2C
  9105. + 15 01 00 00 00 00 02 55 02
  9106. +
  9107. + 15 01 00 00 00 00 02 FF 23
  9108. + 15 01 00 00 00 00 02 FB 01
  9109. + 15 01 00 00 00 00 02 05 24
  9110. + 15 01 00 00 00 00 02 01 84
  9111. + 15 01 00 00 00 00 02 FF 10
  9112. + 05 01 00 00 78 00 02 11 00
  9113. + 05 01 00 00 60 00 02 29 00
  9114. +
  9115. + ];
  9116. +
  9117. + qcom,mdss-dsi-color-test-on-command-state = "dsi_lp_mode";
  9118. + qcom,mdss-dsi-color-test-off-command-state = "dsi_lp_mode";
  9119. +
  9120. + qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
  9121. + qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
  9122. + qcom,mdss-dsi-h-sync-pulse = <1>;
  9123. + qcom,mdss-dsi-traffic-mode = "burst_mode";
  9124. + qcom,mdss-dsi-lane-map = "lane_map_0123";
  9125. + qcom,mdss-dsi-bllp-eof-power-mode;
  9126. + qcom,mdss-dsi-bllp-power-mode;
  9127. + qcom,mdss-dsi-lane-0-state;
  9128. + qcom,mdss-dsi-lane-1-state;
  9129. + qcom,mdss-dsi-lane-2-state;
  9130. + qcom,mdss-dsi-lane-3-state;
  9131. + qcom,mdss-dsi-panel-timings = [E7 43 37 00 60 6C 39 45 5b 03 04 00];
  9132. +
  9133. +
  9134. +
  9135. + qcom,mdss-dsi-t-clk-post = <0x20>;
  9136. + qcom,mdss-dsi-t-clk-pre = <0x3e>;
  9137. + qcom,mdss-dsi-dma-trigger = "trigger_sw";
  9138. + qcom,mdss-dsi-mdp-trigger = "none";
  9139. + qcom,mdss-dsi-te-pin-select = <1>;
  9140. + qcom,mdss-dsi-wr-mem-start = <0x2c>;
  9141. + qcom,mdss-dsi-wr-mem-continue = <0x3c>;
  9142. + qcom,mdss-dsi-te-dcs-command = <1>;
  9143. + qcom,mdss-dsi-te-check-enable;
  9144. + qcom,mdss-dsi-te-using-te-pin;
  9145. +
  9146. +
  9147. +
  9148. +
  9149. + qcom,mdss-dsi-bl-min-level = <1>;
  9150. + qcom,mdss-dsi-bl-max-level = <4095>;/*guozhiming@oem.cn modify 2015-03-24*/
  9151. + qcom,mdss-dsi-lp11-init;
  9152. + //qcom,mdss-dsi-init-delay-us=<50000>;
  9153. + /**************************************************************************/
  9154. + // qcom,esd-check-enabled;
  9155. + // qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08];
  9156. + // qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
  9157. + // qcom,mdss-dsi-panel-status-check-mode = "reg_read_jd35695";
  9158. + // qcom,mdss-dsi-panel-status-read-length = <8>;
  9159. + // qcom,mdss-dsi-panel-max-error-count = <2>;
  9160. + // qcom,mdss-dsi-panel-status-value = <0x9c 0x00 0x00 0x02 0x40 0x80 0x00 0x00>;
  9161. + /******************************************************************************/
  9162. + // qcom,mdss-dsi-dma-trigger = "trigger_sw";
  9163. + // qcom,mdss-dsi-mdp-trigger = "trigger_sw";
  9164. +
  9165. +
  9166. +
  9167. + // qcom,mdss-tear-check-frame-rate=<6000>;
  9168. + // qcom,mdss-tear-check-sync-cfg-height = <1932>; /* Height + VBP + VFP + VSW */
  9169. + // qcom,mdss-tear-check-sync-init-val= <1920>; /* Height */
  9170. + //qcom,mdss-tear-check-sync-threshold-start = <4>;
  9171. + // qcom,mdss-tear-check-sync-threshold-continue = <4>;
  9172. + // qcom,mdss-tear-check-start-pos= <1920>; /* Height */
  9173. + // qcom,mdss-tear-check-rd-ptr-trigger-intr= <1921>; /* Height + 1 */
  9174. +
  9175. + qcom,mdss-pan-physical-width-dimension = <70>;
  9176. + qcom,mdss-pan-physical-height-dimension = <127>;
  9177. +
  9178. +
  9179. + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
  9180. + qcom,mdss-dsi-reset-sequence = <1 11>, <0 2>, <1 12>;
  9181. +
  9182. + };
  9183. +};
  9184. +
  9185. +
  9186. diff --git a/arch/arm64/boot/dts/14049_HW_12/msm8994.dtsi b/arch/arm64/boot/dts/14049_HW_12/msm8994.dtsi
  9187. new file mode 100644
  9188. index 0000000..1424ed1
  9189. --- /dev/null
  9190. +++ b/arch/arm64/boot/dts/14049_HW_12/msm8994.dtsi
  9191. @@ -0,0 +1,3812 @@
  9192. +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  9193. + *
  9194. + * This program is free software; you can redistribute it and/or modify
  9195. + * it under the terms of the GNU General Public License version 2 and
  9196. + * only version 2 as published by the Free Software Foundation.
  9197. + *
  9198. + * This program is distributed in the hope that it will be useful,
  9199. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9200. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9201. + * GNU General Public License for more details.
  9202. + */
  9203. +
  9204. +/memreserve/ 0x00000000 0x00001000;
  9205. +/memreserve/ 0xac1c0000 0x00001000;
  9206. +
  9207. +#include "skeleton64.dtsi"
  9208. +#include <dt-bindings/clock/msm-clocks-8994.h>
  9209. +
  9210. +/ {
  9211. + model = "Qualcomm Technologies, Inc. MSM 8994";
  9212. + compatible = "qcom,msm8994";
  9213. + qcom,msm-id = <207 0x0>;
  9214. + qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  9215. + interrupt-parent = <&intc>;
  9216. +
  9217. + chosen {
  9218. + bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1";
  9219. + };
  9220. +
  9221. + aliases {
  9222. + sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  9223. + /*do not enable sdhc2 and sdhc3
  9224. + sdhc2 = &sdhc_2;
  9225. + sdhc3 = &sdhc_3;
  9226. + */
  9227. + i2c6 = &i2c_6; /* I2C6 NFC qup6 device */
  9228. + i2c1 = &i2c_1;
  9229. + i2c2 = &i2c_2;
  9230. + i2c5 = &i2c_5;
  9231. + spi0 = &spi_0;
  9232. + /*#ifdef VENDOR_EDIT modify for fpc1021 fingerprints*/
  9233. + spi12 = &spi_12;
  9234. + /*#end VENDOR_EDIT*/
  9235. + qup2 = &i2c_2;
  9236. + };
  9237. +
  9238. + cpus {
  9239. + #address-cells = <1>;
  9240. + #size-cells = <0>;
  9241. + cpu-map {
  9242. + cluster0 {
  9243. + core0 {
  9244. + cpu = <&CPU0>;
  9245. + };
  9246. + core1 {
  9247. + cpu = <&CPU1>;
  9248. + };
  9249. + core2 {
  9250. + cpu = <&CPU2>;
  9251. + };
  9252. + core3 {
  9253. + cpu = <&CPU3>;
  9254. + };
  9255. + };
  9256. +
  9257. + cluster1 {
  9258. + core0 {
  9259. + cpu = <&CPU4>;
  9260. + };
  9261. + core1 {
  9262. + cpu = <&CPU5>;
  9263. + };
  9264. + core2 {
  9265. + cpu = <&CPU6>;
  9266. + };
  9267. + core3 {
  9268. + cpu = <&CPU7>;
  9269. + };
  9270. + };
  9271. + };
  9272. +
  9273. + CPU0: cpu@0 {
  9274. + device_type = "cpu";
  9275. + compatible = "arm,cortex-a53";
  9276. + reg = <0x0>;
  9277. + enable-method = "qcom,8994-arm-cortex-acc";
  9278. + qcom,acc = <&acc0>;
  9279. + qcom,ldo = <&ldo0>;
  9280. + next-level-cache = <&L2_0>;
  9281. + L2_0: l2-cache {
  9282. + compatible = "arm,arch-cache";
  9283. + cache-level = <2>;
  9284. + power-domain = <&l2ccc_0>;
  9285. + qcom,dump-size = <0x0>; /* A53 L2 dump not supported */
  9286. + L2_tlb_0: l2-tlb {
  9287. + qcom,dump-size = <0x4000>;
  9288. + };
  9289. + };
  9290. + L1_I_0: l1-icache {
  9291. + compatible = "arm,arch-cache";
  9292. + qcom,dump-size = <0x9040>;
  9293. + };
  9294. + L1_D_0: l1-dcache {
  9295. + compatible = "arm,arch-cache";
  9296. + qcom,dump-size = <0x9040>;
  9297. + };
  9298. + };
  9299. +
  9300. + CPU1: cpu@1 {
  9301. + device_type = "cpu";
  9302. + compatible = "arm,cortex-a53";
  9303. + reg = <0x1>;
  9304. + enable-method = "qcom,8994-arm-cortex-acc";
  9305. + qcom,acc = <&acc1>;
  9306. + qcom,ldo = <&ldo1>;
  9307. + next-level-cache = <&L2_0>;
  9308. + L1_I_1: l1-icache {
  9309. + compatible = "arm,arch-cache";
  9310. + qcom,dump-size = <0x9040>;
  9311. + };
  9312. + L1_D_1: l1-dcache {
  9313. + compatible = "arm,arch-cache";
  9314. + qcom,dump-size = <0x9040>;
  9315. + };
  9316. + };
  9317. +
  9318. + CPU2: cpu@2 {
  9319. + device_type = "cpu";
  9320. + compatible = "arm,cortex-a53";
  9321. + reg = <0x2>;
  9322. + enable-method = "qcom,8994-arm-cortex-acc";
  9323. + qcom,acc = <&acc2>;
  9324. + qcom,ldo = <&ldo2>;
  9325. + next-level-cache = <&L2_0>;
  9326. + L1_I_2: l1-icache {
  9327. + compatible = "arm,arch-cache";
  9328. + qcom,dump-size = <0x9040>;
  9329. + };
  9330. + L1_D_2: l1-dcache {
  9331. + compatible = "arm,arch-cache";
  9332. + qcom,dump-size = <0x9040>;
  9333. + };
  9334. + };
  9335. +
  9336. + CPU3: cpu@3 {
  9337. + device_type = "cpu";
  9338. + compatible = "arm,cortex-a53";
  9339. + reg = <0x3>;
  9340. + enable-method = "qcom,8994-arm-cortex-acc";
  9341. + qcom,acc = <&acc3>;
  9342. + qcom,ldo = <&ldo3>;
  9343. + next-level-cache = <&L2_0>;
  9344. + L1_I_3: l1-icache {
  9345. + compatible = "arm,arch-cache";
  9346. + qcom,dump-size = <0x9040>;
  9347. + };
  9348. + L1_D_3: l1-dcache {
  9349. + compatible = "arm,arch-cache";
  9350. + qcom,dump-size = <0x9040>;
  9351. + };
  9352. + };
  9353. +
  9354. + CPU4: cpu@100 {
  9355. + device_type = "cpu";
  9356. + compatible = "arm,cortex-a57";
  9357. + reg = <0x100>;
  9358. + enable-method = "qcom,8994-arm-cortex-acc";
  9359. + qcom,acc = <&acc4>;
  9360. + qcom,ldo = <&ldo4>;
  9361. + next-level-cache = <&L2_1>;
  9362. + L2_1: l2-cache {
  9363. + compatible = "arm,arch-cache";
  9364. + cache-level = <2>;
  9365. + qcom,dump-size = <0x280040>; /*A57 Cluster L2 size is 1MB */
  9366. + power-domain = <&l2ccc_1>;
  9367. + L2_tlb_1: l2-tlb {
  9368. + qcom,dump-size = <0x4000>;
  9369. + };
  9370. + };
  9371. + L1_itlb_100: l1-itlb {
  9372. + qcom,dump-size = <0x400>;
  9373. + };
  9374. + L1_dtlb_100: l1-dtlb {
  9375. + qcom,dump-size = <0x400>;
  9376. + };
  9377. + L1_I_100: l1-icache {
  9378. + compatible = "arm,arch-cache";
  9379. + qcom,dump-size = <0xd840>;
  9380. + };
  9381. + L1_D_100: l1-dcache {
  9382. + compatible = "arm,arch-cache";
  9383. + qcom,dump-size = <0x9040>;
  9384. + };
  9385. + };
  9386. +
  9387. + CPU5: cpu@101 {
  9388. + device_type = "cpu";
  9389. + compatible = "arm,cortex-a57";
  9390. + reg = <0x101>;
  9391. + enable-method = "qcom,8994-arm-cortex-acc";
  9392. + qcom,acc = <&acc5>;
  9393. + qcom,ldo = <&ldo5>;
  9394. + next-level-cache = <&L2_1>;
  9395. + L1_itlb_101: l1-itlb {
  9396. + qcom,dump-size = <0x400>;
  9397. + };
  9398. + L1_dtlb_101: l1-dtlb {
  9399. + qcom,dump-size = <0x400>;
  9400. + };
  9401. + L1_I_101: l1-icache {
  9402. + compatible = "arm,arch-cache";
  9403. + qcom,dump-size = <0xd840>;
  9404. + };
  9405. + L1_D_101: l1-dcache {
  9406. + compatible = "arm,arch-cache";
  9407. + qcom,dump-size = <0x9040>;
  9408. + };
  9409. + };
  9410. +
  9411. + CPU6: cpu@102 {
  9412. + device_type = "cpu";
  9413. + compatible = "arm,cortex-a57";
  9414. + reg = <0x102>;
  9415. + enable-method = "qcom,8994-arm-cortex-acc";
  9416. + qcom,acc = <&acc6>;
  9417. + qcom,ldo = <&ldo6>;
  9418. + next-level-cache = <&L2_1>;
  9419. + L1_itlb_102: l1-itlb {
  9420. + qcom,dump-size = <0x400>;
  9421. + };
  9422. + L1_dtlb_102: l1-dtlb {
  9423. + qcom,dump-size = <0x400>;
  9424. + };
  9425. + L1_I_102: l1-icache {
  9426. + compatible = "arm,arch-cache";
  9427. + qcom,dump-size = <0xd840>;
  9428. + };
  9429. + L1_D_102: l1-dcache {
  9430. + compatible = "arm,arch-cache";
  9431. + qcom,dump-size = <0x9040>;
  9432. + };
  9433. + };
  9434. +
  9435. + CPU7: cpu@103 {
  9436. + device_type = "cpu";
  9437. + compatible = "arm,cortex-a57";
  9438. + reg = <0x103>;
  9439. + enable-method = "qcom,8994-arm-cortex-acc";
  9440. + qcom,acc = <&acc7>;
  9441. + qcom,ldo = <&ldo7>;
  9442. + next-level-cache = <&L2_1>;
  9443. + L1_itlb_103: l1-itlb {
  9444. + qcom,dump-size = <0x400>;
  9445. + };
  9446. + L1_dtlb_103: l1-dtlb {
  9447. + qcom,dump-size = <0x400>;
  9448. + };
  9449. + L1_I_103: l1-icache {
  9450. + compatible = "arm,arch-cache";
  9451. + qcom,dump-size = <0xd840>;
  9452. + };
  9453. + L1_D_103: l1-dcache {
  9454. + compatible = "arm,arch-cache";
  9455. + qcom,dump-size = <0x9040>;
  9456. + };
  9457. + };
  9458. + };
  9459. +
  9460. + soc: soc { };
  9461. +
  9462. + memory {
  9463. + #address-cells = <2>;
  9464. + #size-cells = <2>;
  9465. +
  9466. + secure_mem: secure_region@0 {
  9467. + linux,reserve-contiguous-region;
  9468. + reg = <0 0 0 0x12c00000>;
  9469. + label = "secure_mem";
  9470. + };
  9471. +
  9472. + adsp_mem: adsp_region@0 {
  9473. + linux,reserve-contiguous-region;
  9474. + reg = <0 0 0 0x3F00000>;
  9475. + label = "adsp_mem";
  9476. + };
  9477. +
  9478. + qsecom_mem: qsecom_region@0 {
  9479. + linux,reserve-contiguous-region;
  9480. + reg = <0 0 0 0x1800000>;
  9481. + label = "qseecom_mem";
  9482. + };
  9483. +
  9484. + audio_mem: audio_region@0 {
  9485. + linux,reserve-contiguous-region;
  9486. + linux,reserve-region;
  9487. + reg = <0 0 0 0x614000>;
  9488. + label = "audio_mem";
  9489. + };
  9490. +
  9491. + removed_regions: removed_regions@0 {
  9492. + linux,reserve-contiguous-region;
  9493. + linux,reserve-region;
  9494. + linux,remove-completely;
  9495. + reg = <0 0x06300000 0 0xD00000>;
  9496. + label = "memory_hole";
  9497. + };
  9498. + /*#ifdef VENDOR_EDIT*/
  9499. + nvbackup_regions: nvbackup_regions@0 {
  9500. + linux,reserve-contiguous-region;
  9501. + oem,reserve-region;
  9502. + reg = <0 0x06200000 0 0x100000>;
  9503. + label = "memory_nvbackup";
  9504. + };
  9505. + /*#endif VENDOR_EDIT*/
  9506. + dfps_data_mem: dfps_data_mem@0 {
  9507. + linux,reserve-contiguous-region;
  9508. + linux,reserve-region;
  9509. + reg = <0 0x03400000 0 0x1000>;
  9510. + label = "dfps_data_mem";
  9511. + };
  9512. + cont_splash_mem: cont_splash_mem@0 {
  9513. + linux,reserve-contiguous-region;
  9514. + linux,reserve-region;
  9515. + reg = <0 0x03401000 0 0x2200000>;
  9516. + label = "cont_splash_mem";
  9517. + };
  9518. +
  9519. + peripheral_mem: peripheral_region@0 {
  9520. + linux,reserve-contiguous-region;
  9521. + linux,reserve-region;
  9522. + linux,remove-completely;
  9523. + reg = <0 0x0ca00000 0 0x1f00000>;
  9524. + label = "peripheral_mem";
  9525. + };
  9526. +/*#ifdef VENDOR_EDIT //changhua.li add for enlarge TZ APP memory to 25M*/
  9527. + tzapp_mem: tzapp_region@0 {
  9528. +
  9529. + linux,reserve-contiguous-region;
  9530. +
  9531. + linux,reserve-region;
  9532. +
  9533. + linux,remove-completely;
  9534. +
  9535. + reg = <0 0x0E900000 0 0x1900000>;
  9536. +
  9537. + label = "tzapp_mem";
  9538. +
  9539. + };
  9540. +/*#endif VENDOR_EDIT*/
  9541. +
  9542. +
  9543. + modem_mem: modem_region@0 {
  9544. + linux,reserve-contiguous-region;
  9545. + linux,reserve-region;
  9546. + linux,remove-completely;
  9547. + reg = <0 0x07000000 0 0x5a00000>;
  9548. + label = "modem_mem";
  9549. + };
  9550. +
  9551. +/* #ifdef VENDOR_EDIT // add by xcb for ramoops 2015-03-31 */
  9552. + ramoops_mem: ramoops_region@0 {
  9553. + linux,reserve-contiguous-region;
  9554. + oem,reserve-region;//modify by jiachenghui for ramoops reserve region
  9555. + //linux,remove-completely;//del by jiachenghui for ramoops reserve region
  9556. + reg = <0 0xac000000 0 0x00100000>;//modify from 0x05800000 to 0xac000000 by jiachenghui for ramoops reserve region
  9557. + label = "ramoops_mem";
  9558. + };
  9559. +/* #endif VENDOR_EDIT */
  9560. +
  9561. + param_mem: param_region@0 {
  9562. + linux,reserve-contiguous-region;
  9563. + oem,reserve-region;
  9564. + //linux,remove-completely;
  9565. + reg = <0 0xac200000 0 0x00100000>;
  9566. + label = "param_mem";
  9567. + };
  9568. + mtp_regions: mtp_regions@0 {
  9569. + linux,reserve-contiguous-region;
  9570. + oem,reserve-region;
  9571. + reg = <0 0xAC400000 0 0x00100000>;
  9572. + label = "memory_mtp";
  9573. + };
  9574. + };
  9575. +};
  9576. +
  9577. +#include "msm-gdsc.dtsi"
  9578. +#include "msm8994-smp2p.dtsi"
  9579. +#include "msm8994-ipcrouter.dtsi"
  9580. +#include "msm8994-mdss.dtsi"
  9581. +#include "msm8994-mdss-pll.dtsi"
  9582. +#include "msm8994-bus.dtsi"
  9583. +
  9584. +&soc {
  9585. + #address-cells = <1>;
  9586. + #size-cells = <1>;
  9587. + ranges = <0 0 0 0xffffffff>;
  9588. + compatible = "simple-bus";
  9589. +
  9590. + cpuss@fd4a8000 {
  9591. + compatible = "qcom,cpuss-8994";
  9592. + reg = <0xfd4a8000 0x4>;
  9593. + };
  9594. +
  9595. + acc0:clock-controller@f908b004 {
  9596. + compatible = "qcom,arm-cortex-acc";
  9597. + reg = <0xf9070000 0x1000>,
  9598. + <0xf908b000 0x1000>,
  9599. + <0xf900b000 0x1000>;
  9600. + };
  9601. +
  9602. + acc1:clock-controller@f909b004 {
  9603. + compatible = "qcom,arm-cortex-acc";
  9604. + reg = <0xf9071000 0x1000>,
  9605. + <0xf909b000 0x1000>,
  9606. + <0xf900b000 0x1000>;
  9607. + };
  9608. +
  9609. + acc2:clock-controller@f90ab004 {
  9610. + compatible = "qcom,arm-cortex-acc";
  9611. + reg = <0xf9072000 0x1000>,
  9612. + <0xf90ab000 0x1000>,
  9613. + <0xf900b000 0x1000>;
  9614. + };
  9615. +
  9616. + acc3:clock-controller@f90bb004 {
  9617. + compatible = "qcom,arm-cortex-acc";
  9618. + reg = <0xf9073000 0x1000>,
  9619. + <0xf90bb000 0x1000>,
  9620. + <0xf900b000 0x1000>;
  9621. + };
  9622. +
  9623. + acc4:clock-controller@f90cb004 {
  9624. + compatible = "qcom,arm-cortex-acc";
  9625. + reg = <0xf9074000 0x1000>,
  9626. + <0xf90cb000 0x1000>,
  9627. + <0xf900b000 0x1000>;
  9628. + };
  9629. +
  9630. + acc5:clock-controller@f90db004 {
  9631. + compatible = "qcom,arm-cortex-acc";
  9632. + reg = <0xf9075000 0x1000>,
  9633. + <0xf90db000 0x1000>,
  9634. + <0xf900b000 0x1000>;
  9635. + };
  9636. +
  9637. + acc6:clock-controller@f90eb004 {
  9638. + compatible = "qcom,arm-cortex-acc";
  9639. + reg = <0xf9076000 0x1000>,
  9640. + <0xf90eb000 0x1000>,
  9641. + <0xf900b000 0x1000>;
  9642. + };
  9643. +
  9644. + acc7:clock-controller@f90fb004 {
  9645. + compatible = "qcom,arm-cortex-acc";
  9646. + reg = <0xf9077000 0x1000>,
  9647. + <0xf90fb000 0x1000>,
  9648. + <0xf900b000 0x1000>;
  9649. + };
  9650. +
  9651. + ldo0:ldo-vref@f9070000 {
  9652. + compatible = "qcom,8994-cpu-ldo-vref";
  9653. + reg = <0xf9070000 0x30>;
  9654. + qcom,ldo-vref-ret = <0x2a>;
  9655. + };
  9656. +
  9657. + ldo1:ldo-vref@f9071000 {
  9658. + compatible = "qcom,8994-cpu-ldo-vref";
  9659. + reg = <0xf9071000 0x30>;
  9660. + qcom,ldo-vref-ret = <0x2a>;
  9661. + };
  9662. +
  9663. + ldo2:ldo-vref@f9072000 {
  9664. + compatible = "qcom,8994-cpu-ldo-vref";
  9665. + reg = <0xf9072000 0x30>;
  9666. + qcom,ldo-vref-ret = <0x2a>;
  9667. + };
  9668. +
  9669. + ldo3:ldo-vref@f9073000 {
  9670. + compatible = "qcom,8994-cpu-ldo-vref";
  9671. + reg = <0xf9073000 0x30>;
  9672. + qcom,ldo-vref-ret = <0x2a>;
  9673. + };
  9674. +
  9675. + ldo4:ldo-vref@f9074000 {
  9676. + compatible = "qcom,8994-cpu-ldo-vref";
  9677. + reg = <0xf9074000 0x30>;
  9678. + qcom,ldo-vref-ret = <0x3e>;
  9679. + };
  9680. +
  9681. + ldo5:ldo-vref@f9075000 {
  9682. + compatible = "qcom,8994-cpu-ldo-vref";
  9683. + reg = <0xf9075000 0x30>;
  9684. + qcom,ldo-vref-ret = <0x3e>;
  9685. + };
  9686. +
  9687. + ldo6:ldo-vref@f9076000 {
  9688. + compatible = "qcom,8994-cpu-ldo-vref";
  9689. + reg = <0xf9076000 0x30>;
  9690. + qcom,ldo-vref-ret = <0x3e>;
  9691. + };
  9692. +
  9693. :
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