module booth(prod, mcand, mplier);

	input [31:0] mcand, mplier;
	output reg [63:0] prod;

	//reg start = 1;
	reg [4:0] bit = 0;
	reg lostbit;


	wire [33:0] mcand_p1 = {mcand[31], mcand[31], mcand}; // times 1
	wire [33:0] mcand_p2 = {mcand[31], mcand, 1'b0}; // times 2
	wire [33:0] mcand_n1 = -mcand_p1; // times -1
	wire [33:0] mcand_n2 = -mcand_p2; // times -2

	reg [1:0] mb;
	reg [33:0] hprod_next;
	reg [33:0] hprod_prev;



	integer i;

	always@(mcand, mplier) begin

			bit = 5'b10000;
			prod = {32'b0, mplier};
			lostbit = 0;

			for( i = 0; i < bit; i = i + 1) begin

			hprod_prev = { prod[63], prod[63], prod[63:32] };

			mb = prod[1:0];

         case ( {mb,lostbit} )
          3'b000: hprod_next = hprod_prev;
          3'b001: hprod_next = hprod_prev + mcand_p1;
          3'b010: hprod_next = hprod_prev + mcand_p1;
          3'b011: hprod_next = hprod_prev + mcand_p2;
          3'b100: hprod_next = hprod_prev + mcand_n2;
          3'b101: hprod_next = hprod_prev + mcand_n1;
          3'b110: hprod_next = hprod_prev + mcand_n1;
          3'b111: hprod_next = hprod_prev;
         endcase

        lostbit = prod[1];

        prod = { hprod_next, prod[31:2] };

		end
	end
endmodule