module stack
#(
        parameter WIDTH_BW=32,
        parameter DEPTH_BW=8
)
(
        input  wire clk,
        input  wire rst_n,

        input  wire                push,
        input  wire [WIDTH_BW-1:0] push_data,

        input  wire                pop,
        output wire [WIDTH_BW-1:0] pop_data
);

        reg [DEPTH_BW-1:0] mem_ptr;
        reg [DEPTH_BW-1:0] rd_addr;

        reg [WIDTH_BW-1:0] tos;

        wire [WIDTH_BW-1:0] mem_read_data;



        // mem ptr
        always @(posedge clk)
        if( !rst_n )
                mem_ptr <= 'd0;
        else case( {push,pop} )
                2'b01: mem_ptr <= mem_ptr - 'd1;
                2'b10: mem_ptr <= mem_ptr + 'd1;
        endcase


        // rd_addr
        always @*
        case( {push,pop} )
                2'b01:   rd_addr = mem_ptr - 'd2;
                2'b10:   rd_addr = mem_ptr;
                default: rd_addr = mem_ptr - 'd1;
        endcase


        // tos
        always @(posedge clk)
        case( {push,pop} )
                2'b01: tos <= mem_read_data;

                2'b10,
                2'b11: tos <= push_data;
        endcase

        // pop_data
        assign pop_data = tos;

        // memory
        mem #( .WIDTH_BW(WIDTH_BW),
               .DEPTH_BW(DEPTH_BW),
               .SAMEADDR_BYPASS(1),
               .SAMEADDR_BREAK(0)
        ) memblk
        (
                .clk(clk),

                .r_addr(rd_addr),
                .r_data(mem_read_data),

                .w_addr(mem_ptr),
                .w_ena(push && !pop),
                .w_data(tos)
        );


endmodule