INNOVUS19.10.000

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CCRs Fixed in Release 19.1 RTM
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CCMPR02055052	Support UPF3.0 Parser
CCMPR02051505	setEdit(inn1625) vs setEditMode(inn1812) compatibility
CCMPR02051463	get_ccopt_skew_group_delay crashed
CCMPR02049931	place_opt_design crashes with "set_limited_access_feature FlipFlopMergeAndSplit false"
CCMPR02048344	Strange routeDesign -wireOpt behavior in 19.10
CCMPR02046944	SEGV during assign_clock_tree_source_groups for a design with preserved ports v19.10-d235_1
CCMPR02044791	Wire edit commands add redundant floating VIA10
CCMPR02043082	Push partition_push_network is too slow with power_intent
CCMPR02040212	legalizePin issues IMPPTN-562 warning with strange coordinates
CCMPR02040038	IQRC does not see physical connectivity between terminal wire segment  (IMPEXT-1392)
CCMPR02039773	SEGV crashing optDesign at post_route during delay calculation
CCMPR02039687	Position based net connection in instance after assembleDesign
CCMPR02039644	routeDesign crash with setNanoRouteMode -routeWithTimingDriven true
CCMPR02039141	editPowerVia command to add power vias from M3 to M1 rails takes long time to complete
CCMPR02039084	ColorizePowerMesh hangs for long time
CCMPR02038227	Filler node is crashing while executing the verifyLitho command
CCMPR02038189	delete_constant_nets (deleteDangling1b1Or0s) does not respect dont_touch_hports
CCMPR02037672	addRepeaterByRule crashes after using "free_power_intent"
CCMPR02037525	NanoRoute not routing straight shots on same metal layer well
CCMPR02036862	Please map legacy setViaGenMode -ignore_design_boundary to Stylus
CCMPR02036858	Add *.enc to filetype pull down menu when using "Restore Design" in the GUI
CCMPR02036850	Long runtime of the partition command
CCMPR02036828	NanoRoute crash in 18.11, critical design
CCMPR02036805	Crash during defIn command
CCMPR02036535	tQuantus TCAP/XCAP optimism Vs iQuantus in 18.12
CCMPR02036318	postcts SEGVs with cdcc14CompressedWave5reset
CCMPR02035579	Text box size from OA design become very large in Innovus
CCMPR02035291	Got a crash when place_opt_design ran
CCMPR02033930	checkPlace struck after placement in Innovus 18.11
CCMPR02033257	Error: IMPCCOPT-1337 during the synthesize_ccopt_flexible_htrees command
CCMPR02032764	Virtual connects appear to have incorrect coordinates
CCMPR02032636	place_opt -opt SEGVs with malformed bucket chain in Tcl_DeleteHashEntry
CCMPR02031696	Error IMPVB-23 while loading Calibre PM rdb file in Innovus
CCMPR02031656	The summaryReport "Layer ... Information" header string is not getting reset between layers
CCMPR02031489	Tool is crashing during the detailRoute -fix_drc in the filler node step
CCMPR02031459	postCTS optimization SEGVs during delay calculation with cdcc14CompressedWave5resetEv
CCMPR02030914	Innovus crash when clicking letter R from schematic view
CCMPR02029817	EDI writes UPF with a syntax error
CCMPR02028956	postroute opt SEGVs in initial delay calculation
CCMPR02027675	Placement crash caused by fake term
CCMPR02026908	NR creates voltage spacing violations with negative bias nets
CCMPR02026480	synthesize_ccopt_flexible_htrees runs out of memory at "Computing placement data ..."
CCMPR02025889	get_db returns invalid values for the attribute .bbox.dx
CCMPR02025882	SEGV during diode insertion for antenna fixes
CCMPR02025643	IMPCK-1021 on a three-metal layer design
CCMPR02025474	NanoRoute not routing straight
CCMPR02023427	SEGV in ccopt_design
CCMPR02022945	oasisOut corrupted after refinePlace
CCMPR02021837	Tool crashes while restoring the saved db
CCMPR02021529	SEGV during create_floorplan
CCMPR02021410	tQuantus SEGV during clock_design in 19.1
CCMPR02021250	Nano route crashes during diode insertion for the antenna fix
CCMPR02020915	Add fillers in postroute dbs caused tool to SEGV
CCMPR02020208	optDesign -postRoute -expandedViews crashes
CCMPR02018934	Auto track generation issue when tech lef uses FIRSTLASTPITCH
CCMPR02018117	Extra vias appear after partition
CCMPR02017530	Long secondary P/G routing to lower layer target while shorter target exist in higher metal
CCMPR02016909	verify_drc does still not detect voltage spacing violation despite recent DB fixes
CCMPR02016644	Why special route needs more overlap of a macro pin than regular route so that IQuantus finds the physical connectivity?
CCMPR02016087	**WARN: (IMPOAX-1339):  Mask value for layer 'CM1' specified in technology data
CCMPR02015670	FlexH routing has too much jogging
CCMPR02015528	dbShape very slow with INSIDE, STRADDLE, and OUTSIDE
CCMPR02015460	edit_update_route_layer broken - innovus 18.12-e077_1
CCMPR02014494	SEGV during ccopt_design
CCMPR02014301	verify_drc missed VIA1.EN.10 violations when vias not centered on std cell pins pin
CCMPR02014228	defOut does not define vias used in the design, while "dumpOutVias" defines it
CCMPR02013592	Vias are missing after partition
CCMPR02013591	SEGV observed during place_opt_design with OA db
CCMPR02012767	common_ui: The edit_update_route_width command is changing/deleting the fixed via
CCMPR02011516	AddStripe could not be extended over the block unless saveDesing, freeDesign, restoreDesign are done
CCMPR02011473	CCOpt SEGV at CCOpt::Cts::Balancer::Balance, the end of globalDetailRoute
CCMPR02011408	refinePlace runtime is 22 minutes or more on 3.5M block
CCMPR02011320	View name being wrap
CCMPR02011016	Default power domain gets partition box and not boxes
CCMPR02010918	place_connected SEGVs in refinePlace with SDPs defined and unplaced
CCMPR02010514	sroute connects block pin to vertical stripes instead of horizontal stripe
CCMPR02010440	The defIn command with larger die size on rectilinear design leaves gaps in the design
CCMPR02009234	SEGV during CCOPT
CCMPR02009061	add_stripes is creating EolExt Spacing DRC violations
CCMPR02008833	SEGV during flex htree implementation
CCMPR02008610	Innovus 1812: core dump during ILM model generation
CCMPR02007904	fcroute -type power does not drop via and does not jog resulting in opens when connecting bumps to stripes
CCMPR02007435	Crash during route_design
CCMPR02007340	Innovus 1812 SEG fault when generating ILM model
CCMPR02007181	Innovus 18.11 SEGV in ccopt_design
CCMPR02004738	Crash during postroute power optimization
CCMPR02004533	To allow customized append prefix to auto generated vias (generateVias)
CCMPR02003887	Latest 181 place_opt_design SEG fault with ILM
CCMPR02003674	Incorect max VOLTAGE setup on negative bias nets
CCMPR02003218	Tool crash during interactive special route
CCMPR02003122	Innovus issues: **DIAG: invalid input to rcdb! internal node missing on net_id
CCMPR02002574	INVS 181 fails to save OA design because of missing tech layer PC (poly)
CCMPR02001610	Innovus crash during CCOpt used for buffer tree synthesis procedure
CCMPR02001589	Pipeline placement with Kmean on is not balanced
CCMPR02001117	write_lef_library outputs float instead int for ANTENNACUMDIFFAREARATIO
CCMPR02000790	Nonsensical timing on routed clk_mesh net - innovus1812
CCMPR02000738	Flip chip fcroute is not routing to all the selected bumps
CCMPR02000630	report_timing SEGVs on large flattened design
CCMPR02000571	ERROR (NREX-94) There are 10 routing layers in design, 0 layers are mapped to techfile. Please check the mapping file
CCMPR02000356	verify_drc does not flag Metal_to_Cut voltage spacing violations, internal domain's max voltage is not correct
CCMPR02000003	addStripe does not put in staple vias in particular areas
CCMPR01999693	7nm stacked vias with MAXCELLEXTENSION leaves DRCs beneath wide PG stripes
CCMPR01999622	Innovus crashes when trying to load db in an existing Innovus session
CCMPR01999385	Ports getting VSS/VDD attributes instead of tieHi/tieLo
CCMPR01999126	place_opt_design results in crash with latest Innovus 171
CCMPR01998410	preRoute extractor is generating very large cap
CCMPR01997773	synthesize_flexhible_htree run time
CCMPR01997670	IMPOPT-608 improperly reported on fully routed design preventing optDesign -postRoute from running
CCMPR01997363	delete_place_blockages continue to be accessible and not output any message
CCMPR01996818	save design crashes after using delete_clock_tree_repeaters
CCMPR01996736	verifyACLimit requires 20nm license even when 7nm license checked out
CCMPR01996074	checkPlace is crashing in 18.11-e061_1
CCMPR01995645	Wire shape is seen in GUI but part of it is not selectable/not returned by dbQuery
CCMPR01995534	Innovus crash with assembleDesign
CCMPR01995297	SEGV while loading OA db
CCMPR01995000	Floorplan step is getting crashed while sourcing addModule port file when IO port is selected
CCMPR01994489	Crash during spare cell addition on an ILM based full-chip placeOpt DB
CCMPR01994368	Unassign bump caused tool to SEGV
CCMPR01994364	INVS 18.12: Tool gives internal error IMPCCOPT-1337 during H-tree generation with customized sink list provided
CCMPR01994256	streamOut stuck when we add path metal under pin
CCMPR01993236	tQuantus with virtual metal fill fails to model increased coupling cap associated with fill
CCMPR01993072	ib_cell does not honor padding
CCMPR01992751	dbget crash in 18.11-e061
CCMPR01992241	Odd timing discrepancy between SI and non-SI
CCMPR01991422	Clock latency has no effect when we reload the DB
CCMPR01991416	assembleDesign FATAL ERROR due to port inconsistency
CCMPR01990939	setEditMode -connectPin default value is not correct
CCMPR01990712	NR should not add patch-wires on top of pins that implicitly widen the pin shapes
CCMPR01990209	routeDesign crash at RC extraction
CCMPR01990078	ccopt_design timing analysis SEGV
CCMPR01989395	DIAG errors from add_tieoffs emitted by CCOpt code even though running place_opt_design
CCMPR01989345	read_physical -add_lefs generates ERROR: (IMPSE-110)
CCMPR01989030	create_route_blockage in 18.12 rounds off coordinates
CCMPR01988547	Need an official way to open the Timing Debug window from a command
CCMPR01988343	editPowerVia to create maximum number of cuts in the intersection (w/o changing wire shape)
CCMPR01988254	Innovus is getting crash while ccopt_design
CCMPR01987794	CCOpt segmentation fault
CCMPR01987611	synthesize_ccopt_flexible_htrees: long runtime at "Computing placement data for flexible H-tree"
CCMPR01987471	Post-route optimization hangs with the ERROR: (IMPSYUTIL-2)
CCMPR01987116	18.1x stops on setViaEdit -allow_geom_drc 1 > /dev/null
CCMPR01985524	Quick abstract inference does not create metal blockages in 18.1
CCMPR01983228	write_lef_abstract does not color pin shapes on M1 correctly
CCMPR01982662	Question on messages printed when invoking the timeDesign command
CCMPR01982246	streamOut -merge is creating a GDS with multiple top structures breaking downstream flows
CCMPR01982216	Spelling error in the "gui_dim_foreground -lightness_level medium" option
CCMPR01982090	.globals file cannot be read back without error through Innovus
CCMPR01981568	181/182 DIAG and SEGV during create_clock_tree_spec
CCMPR01981106	Errors during eco_design with 17.15
CCMPR01980067	Wire widening creates minStep violations
CCMPR01979552	Innovus tool changes orientation when moving pad cells
CCMPR01979198	Innovus 18 crashes on setNanoRouteMode -routeUseAutoVia true
CCMPR01977245	remove_assign/init_remove_assign is not able to remove assign statement
CCMPR01976209	synthesize_ccopt_flexible_htrees crashed with 18.11,18.12 and 18.20
CCMPR01974522	write_lef_library creates invalid LEF file on cells with MUSTJOIN pins.
CCMPR01974303	place_opt_design hangs during in2reg path group optimization
CCMPR01974294	zoom to metal fill causes SEGV
CCMPR01973819	write_lef_library creates a corrupted lef file
CCMPR01973725	addInst snap to one row below the expected row
CCMPR01972187	Innovus 18.1 extraction with tQuantus is failing
CCMPR01971806	Response time of Timing Debugger is very slow
CCMPR01971303	Min cut in LEF for Innovus 18.1 causing DRC
CCMPR01970959	NanoRoute to connect preroutes without using trim (on track next to wide metal)
CCMPR01970864	Status attributes regarding status of the current design
CCMPR01970765	DRV preCTS optimization using normal buffers for cross domain paths
CCMPR01970010	How can we write out a netlist, by excluding PG pins of instances from BE ECO db?
CCMPR01969915	Innovus IO PAD routing using FCROUTE leaves many opens and thousands of DRCs
CCMPR01969845	editPowerVia does not always pick the correct solution
CCMPR01969784	Wrong IEEE1801 PST handling in Innovus while merging multiple power states.
CCMPR01969777	CCOpt places clock buffer w/via pillar beneath wide power rail creating downstream DRCs
CCMPR01969257	synthesize_ccopt_flexible_htrees hangs
CCMPR01968936	Tool crashing while updating timing
CCMPR01968395	addStripe crashed in 18.11-e061_1
CCMPR01968362	oasisOut outputting duplicate text labels on bump shape resulting in DRC errors about off center text
CCMPR01967420	sroute is creating shorts with std cell geometries
CCMPR01967106	NR is not able to clean up Macro pin access DRCs
CCMPR01966885	Innovus 18.1 hangs during via pillar insertion
CCMPR01966833	Routing QOR degradation 18.11 vs 17.14
CCMPR01965947	**ERROR: (IMPSYC-194) message flagged for the addHaloToBlock command needs improvement
CCMPR01965602	Via pillar y-pitch not honored
CCMPR01964727	addStripe hangs with use_fgc true
CCMPR01964425	write_db stops with ERROR: (UI-476) message
CCMPR01964258	Postroute optimization hangs due to the addFiller command
CCMPR01963241	NR/ecoRoute fails to resolve M1 trim metal violation
CCMPR01963228	18.1 verify_drc flags M5/M7 directional spanlength spacing violations that PVS does not
CCMPR01963072	Cannot reset modify_ndr -minCut to value 1
CCMPR01962601	routeDesign exceeds 800GB memory usage: memory jump in TDGR
CCMPR01962435	DB access command keeps incorrect placement halo
CCMPR01962315	Innovus crashing at init_design
CCMPR01961813	Documentation for trace_through_to is inadequate
CCMPR01961026	Mesh-based secondary PG routing leaves lots of DRCs
CCMPR01960572	place_opt_design is modifying rectilinear floorplan boundary
CCMPR01960045	Timing in 18.1 more optimistic than 17.15
CCMPR01960041	Placement resulting in V0 violations with colored V0
CCMPR01959418	editPowerVia runtime increased 84 times from 17.1 to 18.1
CCMPR01959360	INNOVUS crash while saving OA design
CCMPR01959050	Highlight PD gives SEGV
CCMPR01958208	Deletion of unwanted pgTerm caused all bumps unassigned
CCMPR01958079	passiveFill shapes add multiple shapes overtop each other with successive runs
CCMPR01956970	Crash with extractRC called from Innovus
CCMPR01954979	Innovus: init_design failing with IMPOAX-929 for hierarchical PCell in the express PCell cache
CCMPR01954599	optDeisgn -postroute segv
CCMPR01954371	How to add/query object1/object2 information using create_marker/get_db?
CCMPR01954079	place_opt_design -opt takes 90hrs for multiBitFlopOpt and freeFlopMerge flow
CCMPR01953839	Abort during route_design in 18.11-e055_1
CCMPR01953753	NanoRoute adds unnecessary patch wire
CCMPR01953010	routeDesign fails during parasitic extraction
CCMPR01952429	Innovus IO PAD routing using fcroute does not complete
CCMPR01952368	Placement is creating overlap of cell V3 OBS SPACING 0 with V3 PG
CCMPR01951940	optDesign -postRoute results in hang/DRC explosion
CCMPR01951176	refinePlace should not crash when  design is not in memory
CCMPR01951135	Crash in saveDesign
CCMPR01950404	Instant crash with report_obj_connectivity -ports
CCMPR01949858	addRepeaterByRule -postRoute will not add buffer on net that goes around macro and -preRoute adds right at the sink only
CCMPR01948429	Part 2: 17.15 routing violations from via-down to memory pins
CCMPR01948238	Crash with the violationBrowserHide command
CCMPR01948236	verify_drc is wrong for ARRAYSPACING ... WITHIN ... ARRAYWIDTH
CCMPR01947984	verify_drc misses cut EOL violation with 18.11 version but catches in 17.1x
CCMPR01947870	Pin access took long time for two cells with setNanoRouteMode -routeExpWithTrimMetal
CCMPR01947572	add_stripes do not error out when syntax is wrong
CCMPR01945584	TCL execution continues **ERROR: (IMPLIC-90) to terminate TCL script execution
CCMPR01944678	M2/M3 power staples added with the addStripe command are extending outside of the core boundary of the design
CCMPR01944534	verify_drc very slow taking multiple days
CCMPR01944340	ECO routing to fix ARRAYSPACING violations marked by verify_drc
CCMPR01944168	Buffer budget violations seen when using new mixed buffer/inverter flow in extreme flow
CCMPR01944100	streamOut crash
CCMPR01943523	Stack trace during timeDesign -reportOnly
CCMPR01943135	Tool crashes when propagate_activity is run
CCMPR01941965	171/181: SEGV during postroute optimization during ECO shielding
CCMPR01940993	place_opt_design crash of large chip
CCMPR01940925	tQuantus skips special nets which caused tQuantus and QRC correlation issue
CCMPR01940096	Cell Viewer does not appear to display cells of CLASS COVER
CCMPR01939977	Floorplan core bbox modified during design import without warning
CCMPR01939612	check_pin_assignment does not output report to screen
CCMPR01938807	skewClock -postRoute crashes
CCMPR01937840	SEGV ERROR while cloning
CCMPR01937708	optDesign -drv prefers AOBs over secondary islands for buffering
CCMPR01937352	editPowerVia drops a via having Cut Spacing violation with STD cell geometry
CCMPR01937069	optDesign not buffering HFN nets in secondary domain (MSV aware topology)
CCMPR01936562	Detail routing jogs on NDR nets creating DSLSpc violations
CCMPR01934572	18.1 create_route_blockage -rects runs much slower than create_route_blockage -area in 17.1x
CCMPR01934422	False My.S.2.1.1 rules flagged by verify_drc
CCMPR01934242	Detail Routing crashes in 17.15-e018
CCMPR01934173	NanoRoute falls over in 18.1 with ERROR (NRAG-28) Cannot do strict search
CCMPR01933623	High memory usage and runtime during editPowerVia
CCMPR01933608	addFiller creates real and false checkPlace violations
CCMPR01933601	CCOpt crashed during clustering
CCMPR01933584	ccopt_design -cts crash at clustering
CCMPR01933156	editAddVia adding special Via on a regular net
CCMPR01933006	add_io_buffers command does not add buffers for output ports driven by power or ground net
CCMPR01931842	checkPinAssignment fails to catch some violations
CCMPR01931763	routeDesign crashing during optimization when run with setNanoRouteMode -routeWithOpt true
CCMPR01931496	Innovus hanging on saveDesign
CCMPR01930541	Ostrich core dump when reading sign off spef file
CCMPR01930205	Innovus creates unspecified "vdd" power net
CCMPR01929024	routeDesign to fix more cut Spacing violations
CCMPR01928244	Big slow down using setViaGenMode -ignore_DRC false, with editPowerVia
CCMPR01926752	Ostrich hangs when reading signoff spef file for several blocks
CCMPR01926556	VIA3.R.4:M4 Calibre Drc not reported by Innovus
CCMPR01926442	Tracks not re-created when using filter option with oaIn
CCMPR01925327	Almost 30K M1 DSLCOL violations with newer builds where 17.14-e040_1 routed near clean
CCMPR01925158	Hierarchical upf - top level scope contains redundant set_port_attribute from sons
CCMPR01924649	ERRORs due to set_max_delay -from clock -to clock in constraints: units and missing analysis views
CCMPR01924632	Nanoroute shield wire DRC violations
CCMPR01924207	place_opt_design is using high Memory after global placement
CCMPR01923810	verify_drc fails to catch VIAINPINONLY DRC violation
CCMPR01923713	Support layer based spacing constraint in pin assignment
CCMPR01923446	18.10--non-determinism in POD
CCMPR01923159	editPowerVia exits possibly due to memory issue
CCMPR01922769	Current being incorrectly distributed between the primary ground pin and the bulk ground pin
CCMPR01921606	SDP stack splits when it comes across prefixed cells
CCMPR01921587	tQuantus extraction of clock via pillars results in miscorrelation of cap/res vs tQRC/iQRC/QRC
CCMPR01921566	Innovus is not able to resolve cutSameMaskSpacing violations
CCMPR01921051	route_fix_signoff_drc to warn and list global routed or unconnected nets
CCMPR01920786	**ERROR: (IMPCCOPT-1222):While running synthesize_ccopt_flexible_htrees in 18.1
CCMPR01920382	check_place should not report fixed instances inside soft placement blockage as violations
CCMPR01920080	Stack Trace Error in Stylus flow
CCMPR01919706	addEndCap long runtime in large design
CCMPR01919531	Innovus crashes on loadFPlan command
CCMPR01919383	False trim to trim violation in verify_drc
CCMPR01919238	Manual editing is not honoring the track color for wire color assignment
CCMPR01919045	Unacceptable long run time for read liberty
CCMPR01918930	check_drc did not flag M4.R.7
CCMPR01918883	18.10-a087_1-non-determinism in CCOpt spine flow
CCMPR01918786	timeDesign -preCts segv
CCMPR01918379	Shielding Percentage on clock nets drops significantly from 94% after CTS to 60% at postroute
CCMPR01918011	False short between SADP_FILLS and unused pin in verify_drc
CCMPR01917899	Incremental UPF having duplicate information
CCMPR01917611	optDesign does not honor preserveModuleFunction
CCMPR01917303	17.15 routing violations from via-down to memory pins
CCMPR01916693	Congestion Repair not occurring on 4 metal layer design
CCMPR01916619	optDesign -postRoute SEGV
CCMPR01916593	Die size change with saveDesign and restoreDesign Back with set fpgOddEvenSitesRowConstraint 2
CCMPR01915378	assign_partition_pin inefficiently assigning pins
CCMPR01915338	Tool is throwing **DIAG message while running "routeDesign -trackOpt"
CCMPR01914741	placeDesign -noPrePlaceOpt takes 7 hours on design with 7 insts
CCMPR01914726	Crash in route stage due to net integrity problem from global routing
CCMPR01914599	171/181 tool add AO cell which are not needed, such cell impact negatively frequency target
CCMPR01914222	preCTS useful skew is leaving many skewing opportunities
CCMPR01914032	Cell Viewer incorrectly displays asymmetric vias
CCMPR01913386	Some SDP stacks are not being pin-aligned
CCMPR01913232	scanReorder with inter-chain swapping turned on made no changes to the domains where it was enabled
CCMPR01912800	preroute_opt clock tree expansion adds repeaters in the incorrect power domain
CCMPR01912273	Buffer add by opt resulting in CLP violations
CCMPR01912257	Innovus not reporting Mx.En.10.1 enclosure violation on M7
CCMPR01911530	Patch wires getting added create DRC violations. Patch wires not needed
CCMPR01911496	Tempus to return prompt after read_db
CCMPR01911308	ccopt_design -cts crash after clustering
CCMPR01911022	ILM internal paths showing up at the parent level by report_timing
CCMPR01910144	17.14 place_opt_design SEGV during extraction
CCMPR01909561	INNOVUS: Make common report_area_summary command across tools
CCMPR01908841	Violation browser GUI should not change focus when hide/show/show only this type is selected
CCMPR01908649	verifyPowerDomain reports a false IMPMSMV-8301 for isolation location fanout
CCMPR01908273	G2 power routing is not connecting properly to pins
CCMPR01906436	Loading db after setting set_db oa_update_mode auto results in pins having placement status of cover instead of fixed
CCMPR01906356	optDesign leaving many nets unbuffered in VDD_MX domains (MSV gas-station topology)
CCMPR01906318	sroute runtime 7X slower than 17.12 in 17.13 or newer
CCMPR01906232	Spelling and grammatical mistake in IMPSE-124 message
CCMPR01905471	*DIAG:(Missing Adj): + 0.066 & ERROR: (TA-1029): a reporting error...  during report_timing
CCMPR01904798	Innovus is crashing during source group allocation in CTS
CCMPR01904562	Innovus does not save the library path in relative path format using the saveDesign -relativePath command
CCMPR01904499	Moorea isInstColorConflictLegal() should not flip instance color if no DRC
CCMPR01902667	v2 cut spacing violations after place_opt_design
CCMPR01902264	Innovus Crash during timeDesign with Multi-CPU option with Innovus-17.1
CCMPR01902203	Tool crashes while running check_connectivity
CCMPR01901702	place_opt_design crash with m_heapCount && m_nodeList messages
CCMPR01901485	Select-all followed by copy in Innovus GUI object attributes field only fills copy/paste buffer not middle-mouse
CCMPR01901252	Stylus to please enable running of flow without reporting followed later with reporting
CCMPR01900393	NR creates layer jumps that cannot fix process antenna violation
CCMPR01900055	reportPowerDomain gives inconsistent voltage values
CCMPR01900044	Innovus does not mark M4.S.27 violations by check_drc
CCMPR01899252	lremove functionality inconsistent between Tempus/Voltus/Genus/Innovus legacyUI vs CUI
CCMPR01899219	Levelshifters not getting inserted and few of the nets in this design not getting clamped as per default cpf rule
CCMPR01898681	get_db multiline -if clauses output extra newlines to stdout
CCMPR01898530	Innovus crash during PlaceOpt with Block ILM
CCMPR01897629	ERROR IMPLF-381 message needs to be flagged for standard cells with "CLASS CORE" property only
CCMPR01897349	optDesign -postRoute: Timing degradation seen within ecoRoute call
CCMPR01896657	sVIA and sWIRE are modified outside the yellow box in parallel edit
CCMPR01895113	Innovus creates max via stack DRCs which are not reported by Innovus as violations
CCMPR01894559	Innovus crashes if the number of objects reported is more than 536870909
CCMPR01894510	17.1x ecoRoute adding unnecessary M3 patch metal
CCMPR01894033	Better suggestion for attachTerm and attachModulePort
CCMPR01893695	Tool is not honoring the list in -exclude_elements for the level_shifter rule correctly
CCMPR01893633	Crash in setIntegRouteConstraint
CCMPR01890864	Mincut DRC error not seen by Innovus as violation
CCMPR01890572	dont_touch of hinst cannot be removed
CCMPR01890331	Malformed Via from VIAGEN
CCMPR01889179	attachTerm run time exponential degradation
CCMPR01887920	Ccopt_design -cts hangs after clustering
CCMPR01887249	runtime issue for starting level-shifter placement with spgOption.shifterMode
CCMPR01886644	Need Common UI support for these options for setOptMode
CCMPR01882839	Multipass CTS configured with opt_ignore property crashes
CCMPR01882585	sroute creates DRC
CCMPR01881856	TNS x3 worse for reselection all compared to slack based reselection (-310ns vs -101ns)
CCMPR01880659	Support UPF set_port_attribute feedthrough and unconnected
CCMPR01880138	Crash with multiple resize_floorplan commands (GUI)
CCMPR01879487	Long saveDesign runtime on design with 1.5 M instances
CCMPR01879298	How to increase precision in verify reporting
CCMPR01876164	Innovus routes to power pin inside routing blockage (and creates shorts)
CCMPR01873951	Enhance wire editor to accept a list of vias to ignore
CCMPR01873950	SEGV in report_timing after assembleDesign
CCMPR01869930	verify_drc gets CUTCLASS wrong for ARRAYSPACING
CCMPR01869627	Innovus hangs during place_opt_design
CCMPR01869304	SEGV crash at optDesign -postCTS -hold in 17.12 version
CCMPR01868480	verifyPowerVia report incorrect distance in report file, correct one in Violation browser
CCMPR01867643	saveDesign takes roughly an hour
CCMPR01867132	Crash during restoreDesign  of an assembled design
CCMPR01865552	171/181 verifyConnectivity does not report unrouted net when IO pin are unplaced
CCMPR01855635	PWR nets are not pushed down into partition as expected
CCMPR01854089	Enhancement of Via pillars to support power routing
CCMPR01852129	Innovus needs controls for not added EEQ cells in the netlist (LVS requirement)
CCMPR01851275	17.12 commit_power_intent leaving 15k retnFlop vdd_ext open but 15.24 build is not
CCMPR01849939	DRC increase at post-route opt due to high local density
CCMPR01847215	write_timing_model SEGVs in 17.11 and early versions of 17.12/18.1
CCMPR01842874	Innovus route_design QOR degrades from 16.21 to 17.1 version.
CCMPR01840991	addFiller needs to be multithreaded
CCMPR01839568	place_opt_design crash
CCMPR01839093	"ccopt" leaves too many max_tran violation
CCMPR01834721	ecoRoute -fix_drc area to route open nets in area w/o any area limitation
CCMPR01833756	Floorplan code to provide callback registration for floorplan changes (like placement-blockages, tracks)
CCMPR01833617	verify_drc reports false LB min witdh error
CCMPR01829781	Post CTS hold fixing does not fix all violation when min_delay is on module pin
CCMPR01817952	read_stream should also support oasis format
CCMPR01811286	Get huge numbers of TCLCMD-513 warnings when using get_db to query the .clocks attribute of a pin
CCMPR01810483	create_ccopt_clock_tree_spec hangs
CCMPR01807374	verify_drc miss DRCs to diagonal special route
CCMPR01807373	Encounter saveNetlist io port ordering issue
CCMPR01802847	Innovus crashes during delay calculation in addMetalFill
CCMPR01794219	streamOut oasisOut mapfile enhancement needed for mapping SADP and trimmetal fill shapes
CCMPR01792686	Custom shape polygon is not being saved in Common UI and even object attribute is not working on it
CCMPR01790128	Adding via pillar run time issue
CCMPR01789477	write_db/saveDesign does not adequately sanitize comments in constraint files
CCMPR01787945	The summaryReport command is reporting box area for pad cell instead of reporting rectilinear area
CCMPR01776838	get_db pg_nets reports tie nets under pg
CCMPR01772729	Adding -rc_corners option for write_extraction_spec command
CCMPR01758143	editAddTrimMetal should allow pin as argument with layer control rather than selected object
CCMPR01749914	Error TECHLIB-9067 while reading in RAM .lib-File
CCMPR01747858	fixHold estimates not matching with final summary due to old CTE SOCV variable
CCMPR01740416	fcroute serial_pad_routing with star connectivity
CCMPR01740161	Request for a tcl command that will select and attach any object to the cursor
CCMPR01714367	Request way to remove custom layers from the Custom Layer tab of Color Preferences Gui
CCMPR01708063	createPinGroup -spreadPin option does not work as documented
CCMPR01699424	oasisOut: How to record the instance information directly on an attribute 'instName' rather integer attribute 300
CCMPR01682932	time_design not honoring opt_time_design_expanded_view=true
CCMPR01667971	saveDesign takes very long time when setSIMode -skip_tw is in use
CCMPR01665686	The path_group target slack multiplies by a factor of 1000 with each write_db / read_db cycle
CCMPR01613077	OAX gets the layer order wrong from standard via
CCMPR01602674	Issue with drouteStrictlyHonorObsInStandardCell true
CCMPR01567410	Attributes table for numerous selected objects
CCMPR01561575	oasisOut is shifting BUMP locations
CCMPR01554953	isLogCommand not documented or in the help
CCMPR01540198	Enhancement: add command to show a path and name to the currently loaded DB
CCMPR01516053	expandedViews does not work with timeDesign -signoff
CCMPR01465935	createLib should also create cdsinfo.tag file.
CCMPR01370636	Preference settings in Instance Based schematic and Clock Tree Debugger windows
CCMPR01290790	redirect -variable takes long time to complete in Tempus