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DSO1072B Partial Fix

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  1. /*
  2. * This file is part of the libsigrok project.
  3. *
  4. * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
  5. * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
  6. * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation, either version 3 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21.  
  22. #include <config.h>
  23. #include <stdlib.h>
  24. #include <stdarg.h>
  25. #include <unistd.h>
  26. #include <errno.h>
  27. #include <string.h>
  28. #include <math.h>
  29. #include <ctype.h>
  30. #include <time.h>
  31. #include <glib.h>
  32. #include <libsigrok/libsigrok.h>
  33. #include "libsigrok-internal.h"
  34. #include "scpi.h"
  35. #include "protocol.h"
  36.  
  37. /*
  38. * This is a unified protocol driver for the DS1000 and DS2000 series.
  39. *
  40. * DS1000 support tested with a Rigol DS1102D.
  41. *
  42. * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02.
  43. *
  44. * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think)
  45. * standard. If you want to read it - it costs real money...
  46. *
  47. * Every response from the scope has a linefeed appended because the
  48. * standard says so. In principle this could be ignored because sending the
  49. * next command clears the output queue of the scope. This driver tries to
  50. * avoid doing that because it may cause an error being generated inside the
  51. * scope and who knows what bugs the firmware has WRT this.
  52. *
  53. * Waveform data is transferred in a format called "arbitrary block program
  54. * data" specified in IEEE 488.2. See Agilents programming manuals for their
  55. * 2000/3000 series scopes for a nice description.
  56. *
  57. * Each data block from the scope has a header, e.g. "#900000001400".
  58. * The '#' marks the start of a block.
  59. * Next is one ASCII decimal digit between 1 and 9, this gives the number of
  60. * ASCII decimal digits following.
  61. * Last are the ASCII decimal digits giving the number of bytes (not
  62. * samples!) in the block.
  63. *
  64. * After this header as many data bytes as indicated follow.
  65. *
  66. * Each data block has a trailing linefeed too.
  67. */
  68.  
  69. static int parse_int(const char *str, int *ret)
  70. {
  71. char *e;
  72. long tmp;
  73.  
  74. errno = 0;
  75. tmp = strtol(str, &e, 10);
  76. if (e == str || *e != '\0') {
  77. sr_dbg("Failed to parse integer: '%s'", str);
  78. return SR_ERR;
  79. }
  80. if (errno) {
  81. sr_dbg("Failed to parse integer: '%s', numerical overflow", str);
  82. return SR_ERR;
  83. }
  84. if (tmp > INT_MAX || tmp < INT_MIN) {
  85. sr_dbg("Failed to parse integer: '%s', value to large/small", str);
  86. return SR_ERR;
  87. }
  88.  
  89. *ret = (int)tmp;
  90. return SR_OK;
  91. }
  92.  
  93. /* Set the next event to wait for in rigol_ds_receive */
  94. static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event)
  95. {
  96. if (event == WAIT_STOP)
  97. devc->wait_status = 2;
  98. else
  99. devc->wait_status = 1;
  100. devc->wait_event = event;
  101. }
  102.  
  103. /*
  104. * Waiting for a event will return a timeout after 2 to 3 seconds in order
  105. * to not block the application.
  106. */
  107. static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2)
  108. {
  109. char *buf;
  110. struct dev_context *devc;
  111. time_t start;
  112.  
  113. if (!(devc = sdi->priv))
  114. return SR_ERR;
  115.  
  116. start = time(NULL);
  117.  
  118. /*
  119. * Trigger status may return:
  120. * "TD" or "T'D" - triggered
  121. * "AUTO" - autotriggered
  122. * "RUN" - running
  123. * "WAIT" - waiting for trigger
  124. * "STOP" - stopped
  125. */
  126.  
  127. if (devc->wait_status == 1) {
  128. do {
  129. if (time(NULL) - start >= 3) {
  130. sr_dbg("Timeout waiting for trigger");
  131. return SR_ERR_TIMEOUT;
  132. }
  133.  
  134. if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
  135. return SR_ERR;
  136. } while (buf[0] == status1 || buf[0] == status2);
  137.  
  138. devc->wait_status = 2;
  139. }
  140. if (devc->wait_status == 2) {
  141. do {
  142. if (time(NULL) - start >= 3) {
  143. sr_dbg("Timeout waiting for trigger");
  144. return SR_ERR_TIMEOUT;
  145. }
  146.  
  147. if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK)
  148. return SR_ERR;
  149. } while (buf[0] != status1 && buf[0] != status2);
  150.  
  151. rigol_ds_set_wait_event(devc, WAIT_NONE);
  152. }
  153.  
  154. return SR_OK;
  155. }
  156.  
  157. /*
  158. * For live capture we need to wait for a new trigger event to ensure that
  159. * sample data is not returned twice.
  160. *
  161. * Unfortunately this will never really work because for sufficiently fast
  162. * timebases and trigger rates it just can't catch the status changes.
  163. *
  164. * What would be needed is a trigger event register with autoreset like the
  165. * Agilents have. The Rigols don't seem to have anything like this.
  166. *
  167. * The workaround is to only wait for the trigger when the timebase is slow
  168. * enough. Of course this means that for faster timebases sample data can be
  169. * returned multiple times, this effect is mitigated somewhat by sleeping
  170. * for about one sweep time in that case.
  171. */
  172. static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi)
  173. {
  174. struct dev_context *devc;
  175. long s;
  176.  
  177. if (!(devc = sdi->priv))
  178. return SR_ERR;
  179.  
  180. /*
  181. * If timebase < 50 msecs/DIV just sleep about one sweep time except
  182. * for really fast sweeps.
  183. */
  184. if (devc->timebase < 0.0499) {
  185. if (devc->timebase > 0.99e-6) {
  186. /*
  187. * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100
  188. * -> 85 percent of sweep time
  189. */
  190. s = (devc->timebase * devc->model->series->num_horizontal_divs
  191. * 85e6) / 100L;
  192. sr_spew("Sleeping for %ld usecs instead of trigger-wait", s);
  193. g_usleep(s);
  194. }
  195. rigol_ds_set_wait_event(devc, WAIT_NONE);
  196. return SR_OK;
  197. } else {
  198. return rigol_ds_event_wait(sdi, 'T', 'A');
  199. }
  200. }
  201.  
  202. /* Wait for scope to got to "Stop" in single shot mode */
  203. static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi)
  204. {
  205. return rigol_ds_event_wait(sdi, 'S', 'S');
  206. }
  207.  
  208. /* Check that a single shot acquisition actually succeeded on the DS2000 */
  209. static int rigol_ds_check_stop(const struct sr_dev_inst *sdi)
  210. {
  211. struct dev_context *devc;
  212. struct sr_channel *ch;
  213. int tmp;
  214.  
  215. if (!(devc = sdi->priv))
  216. return SR_ERR;
  217.  
  218. ch = devc->channel_entry->data;
  219.  
  220. if (devc->model->series->protocol != PROTOCOL_V3)
  221. return SR_OK;
  222.  
  223. if (ch->type == SR_CHANNEL_LOGIC) {
  224. if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
  225. return SR_ERR;
  226. } else {
  227. if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
  228. ch->index + 1) != SR_OK)
  229. return SR_ERR;
  230. }
  231. /* Check that the number of samples will be accepted */
  232. if (rigol_ds_config_set(sdi, ":WAV:POIN %d",
  233. ch->type == SR_CHANNEL_LOGIC ?
  234. devc->digital_frame_size :
  235. devc->analog_frame_size) != SR_OK)
  236. return SR_ERR;
  237. if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK)
  238. return SR_ERR;
  239. /*
  240. * If we get an "Execution error" the scope went from "Single" to
  241. * "Stop" without actually triggering. There is no waveform
  242. * displayed and trying to download one will fail - the scope thinks
  243. * it has 1400 samples (like display memory) and the driver thinks
  244. * it has a different number of samples.
  245. *
  246. * In that case just try to capture something again. Might still
  247. * fail in interesting ways.
  248. *
  249. * Ain't firmware fun?
  250. */
  251. if (tmp & 0x10) {
  252. sr_warn("Single shot acquisition failed, retrying...");
  253. /* Sleep a bit, otherwise the single shot will often fail */
  254. g_usleep(500 * 1000);
  255. rigol_ds_config_set(sdi, ":SING");
  256. rigol_ds_set_wait_event(devc, WAIT_STOP);
  257. return SR_ERR;
  258. }
  259.  
  260. return SR_OK;
  261. }
  262.  
  263. /* Wait for enough data becoming available in scope output buffer */
  264. static int rigol_ds_block_wait(const struct sr_dev_inst *sdi)
  265. {
  266. char *buf;
  267. struct dev_context *devc;
  268. time_t start;
  269. int len;
  270.  
  271. if (!(devc = sdi->priv))
  272. return SR_ERR;
  273.  
  274. if (devc->model->series->protocol == PROTOCOL_V3) {
  275.  
  276. start = time(NULL);
  277.  
  278. do {
  279. if (time(NULL) - start >= 3) {
  280. sr_dbg("Timeout waiting for data block");
  281. return SR_ERR_TIMEOUT;
  282. }
  283.  
  284. /*
  285. * The scope copies data really slowly from sample
  286. * memory to its output buffer, so try not to bother
  287. * it too much with SCPI requests but don't wait too
  288. * long for short sample frame sizes.
  289. */
  290. g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000));
  291.  
  292. if (strcmp(devc->model->series->name, "DSO1000") == 0){
  293. // This series need a different approach
  294.  
  295. // OPC check if scope is ready. Otherwise it freezes
  296. if (sr_scpi_get_string(sdi->conn, "*OPC?", &buf) != SR_OK)
  297. return SR_ERR;
  298.  
  299. // If OPC is ok, quit loop
  300. if (buf[0] == '1')
  301. break;
  302.  
  303. }else{
  304. /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */
  305. if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK)
  306. return SR_ERR;
  307.  
  308. if (parse_int(buf + 5, &len) != SR_OK)
  309. return SR_ERR;
  310. }
  311. } while (buf[0] == 'R' && len < (1000 * 1000));
  312. }
  313.  
  314. rigol_ds_set_wait_event(devc, WAIT_NONE);
  315.  
  316. return SR_OK;
  317. }
  318.  
  319. /* Send a configuration setting. */
  320. SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...)
  321. {
  322. struct dev_context *devc = sdi->priv;
  323. va_list args;
  324. int ret;
  325.  
  326. va_start(args, format);
  327. ret = sr_scpi_send_variadic(sdi->conn, format, args);
  328. va_end(args);
  329.  
  330. if (ret != SR_OK)
  331. return SR_ERR;
  332.  
  333. if (devc->model->series->protocol == PROTOCOL_V2) {
  334. /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
  335. sr_spew("delay %dms", 100);
  336. g_usleep(100 * 1000);
  337. return SR_OK;
  338. } else {
  339. return sr_scpi_get_opc(sdi->conn);
  340. }
  341. }
  342.  
  343. /* Start capturing a new frameset */
  344. SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi)
  345. {
  346. struct dev_context *devc;
  347. gchar *trig_mode;
  348. unsigned int num_channels, i, j;
  349. int buffer_samples;
  350.  
  351. if (!(devc = sdi->priv))
  352. return SR_ERR;
  353.  
  354. const gboolean first_frame = (devc->num_frames == 0);
  355.  
  356. uint64_t limit_frames = devc->limit_frames;
  357. if (devc->num_frames_segmented != 0 && devc->num_frames_segmented < limit_frames)
  358. limit_frames = devc->num_frames_segmented;
  359. if (limit_frames == 0)
  360. sr_dbg("Starting data capture for frameset %" PRIu64,
  361. devc->num_frames + 1);
  362. else
  363. sr_dbg("Starting data capture for frameset %" PRIu64 " of %"
  364. PRIu64, devc->num_frames + 1, limit_frames);
  365.  
  366. switch (devc->model->series->protocol) {
  367. case PROTOCOL_V1:
  368. rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
  369. break;
  370. case PROTOCOL_V2:
  371. if (devc->data_source == DATA_SOURCE_LIVE) {
  372. if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK)
  373. return SR_ERR;
  374. rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
  375. } else {
  376. if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
  377. return SR_ERR;
  378. if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK)
  379. return SR_ERR;
  380. if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK)
  381. return SR_ERR;
  382. if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK)
  383. return SR_ERR;
  384. if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
  385. return SR_ERR;
  386. rigol_ds_set_wait_event(devc, WAIT_STOP);
  387. }
  388. break;
  389. case PROTOCOL_V3:
  390. case PROTOCOL_V4:
  391. case PROTOCOL_V5:
  392. if (first_frame && rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK)
  393. return SR_ERR;
  394. if (devc->data_source == DATA_SOURCE_LIVE) {
  395. if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK)
  396. return SR_ERR;
  397. devc->analog_frame_size = devc->model->series->live_samples;
  398. devc->digital_frame_size = devc->model->series->live_samples;
  399. rigol_ds_set_wait_event(devc, WAIT_TRIGGER);
  400. } else {
  401. if (devc->model->series->protocol == PROTOCOL_V3) {
  402. if (first_frame && rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK)
  403. return SR_ERR;
  404. } else if (devc->model->series->protocol >= PROTOCOL_V4) {
  405. num_channels = 0;
  406.  
  407. /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */
  408. for (i = 0; i < devc->model->analog_channels; i++) {
  409. if (devc->analog_channels[i]) {
  410. num_channels++;
  411. } else if (i >= 2 && devc->model->has_digital) {
  412. for (j = 0; j < 8; j++) {
  413. if (devc->digital_channels[8 * (i - 2) + j]) {
  414. num_channels++;
  415. break;
  416. }
  417. }
  418. }
  419. }
  420.  
  421. buffer_samples = devc->model->series->buffer_samples;
  422. if (first_frame && buffer_samples == 0)
  423. {
  424. /* The DS4000 series does not have a fixed memory depth, it
  425. * can be chosen from the menu and also varies with number
  426. * of active channels. Retrieve the actual number with the
  427. * ACQ:MDEP command. */
  428. sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples);
  429. devc->analog_frame_size = devc->digital_frame_size =
  430. buffer_samples;
  431. }
  432. else if (first_frame)
  433. {
  434. /* The DS1000Z series has a fixed memory depth which we
  435. * need to divide correctly according to the number of
  436. * active channels. */
  437. devc->analog_frame_size = devc->digital_frame_size =
  438. num_channels == 1 ?
  439. buffer_samples :
  440. num_channels == 2 ?
  441. buffer_samples / 2 :
  442. buffer_samples / 4;
  443. }
  444. }
  445.  
  446. if (devc->data_source == DATA_SOURCE_LIVE && rigol_ds_config_set(sdi, ":SINGL") != SR_OK)
  447. return SR_ERR;
  448. rigol_ds_set_wait_event(devc, WAIT_STOP);
  449. if (devc->data_source == DATA_SOURCE_SEGMENTED &&
  450. devc->model->series->protocol <= PROTOCOL_V4)
  451. if (rigol_ds_config_set(sdi, "FUNC:WREP:FCUR %d", devc->num_frames + 1) != SR_OK)
  452. return SR_ERR;
  453. }
  454. break;
  455. }
  456.  
  457. return SR_OK;
  458. }
  459.  
  460. /* Start reading data from the current channel */
  461. SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi)
  462. {
  463. struct dev_context *devc;
  464. struct sr_channel *ch;
  465.  
  466. if (!(devc = sdi->priv))
  467. return SR_ERR;
  468.  
  469. ch = devc->channel_entry->data;
  470.  
  471. sr_dbg("Starting reading data from channel %d", ch->index + 1);
  472.  
  473. const gboolean first_frame = (devc->num_frames == 0);
  474.  
  475. switch (devc->model->series->protocol) {
  476. case PROTOCOL_V1:
  477. case PROTOCOL_V2:
  478. if (ch->type == SR_CHANNEL_LOGIC) {
  479. if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK)
  480. return SR_ERR;
  481. } else {
  482. if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d",
  483. ch->index + 1) != SR_OK)
  484. return SR_ERR;
  485. }
  486. rigol_ds_set_wait_event(devc, WAIT_NONE);
  487. break;
  488. case PROTOCOL_V3:
  489. if (ch->type == SR_CHANNEL_LOGIC) {
  490. if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK)
  491. return SR_ERR;
  492. } else {
  493. if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
  494. ch->index + 1) != SR_OK)
  495. return SR_ERR;
  496. }
  497. if (devc->data_source != DATA_SOURCE_LIVE) {
  498. if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
  499. return SR_ERR;
  500. if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
  501. return SR_ERR;
  502. }
  503. break;
  504. case PROTOCOL_V4:
  505. case PROTOCOL_V5:
  506. if (ch->type == SR_CHANNEL_ANALOG) {
  507. if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d",
  508. ch->index + 1) != SR_OK)
  509. return SR_ERR;
  510. } else {
  511. if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d",
  512. ch->index) != SR_OK)
  513. return SR_ERR;
  514. }
  515.  
  516. if (first_frame && rigol_ds_config_set(sdi,
  517. devc->data_source == DATA_SOURCE_LIVE ?
  518. ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK)
  519. return SR_ERR;
  520.  
  521. if (devc->data_source != DATA_SOURCE_LIVE) {
  522. if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK)
  523. return SR_ERR;
  524. }
  525. break;
  526. }
  527.  
  528. if (devc->model->series->protocol >= PROTOCOL_V3 &&
  529. ch->type == SR_CHANNEL_ANALOG) {
  530. /* Vertical increment. */
  531. if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YINC?",
  532. &devc->vert_inc[ch->index]) != SR_OK)
  533. return SR_ERR;
  534. /* Vertical origin. */
  535. if (first_frame && sr_scpi_get_float(sdi->conn, ":WAV:YOR?",
  536. &devc->vert_origin[ch->index]) != SR_OK)
  537. return SR_ERR;
  538. /* Vertical reference. */
  539. if (first_frame && sr_scpi_get_int(sdi->conn, ":WAV:YREF?",
  540. &devc->vert_reference[ch->index]) != SR_OK)
  541. return SR_ERR;
  542. } else if (ch->type == SR_CHANNEL_ANALOG) {
  543. devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6;
  544. }
  545.  
  546. rigol_ds_set_wait_event(devc, WAIT_BLOCK);
  547.  
  548. devc->num_channel_bytes = 0;
  549. devc->num_header_bytes = 0;
  550. devc->num_block_bytes = 0;
  551.  
  552. return SR_OK;
  553. }
  554.  
  555. /* Read the header of a data block */
  556. static int rigol_ds_read_header(struct sr_dev_inst *sdi)
  557. {
  558. struct sr_scpi_dev_inst *scpi = sdi->conn;
  559. struct dev_context *devc = sdi->priv;
  560. char *buf = (char *) devc->buffer;
  561. size_t header_length;
  562. int ret;
  563.  
  564. /* Try to read the hashsign and length digit. */
  565. if (devc->num_header_bytes < 2) {
  566. ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
  567. 2 - devc->num_header_bytes);
  568. if (ret < 0) {
  569. sr_err("Read error while reading data header.");
  570. return SR_ERR;
  571. }
  572. devc->num_header_bytes += ret;
  573. }
  574.  
  575. if (devc->num_header_bytes < 2)
  576. return 0;
  577.  
  578. if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') {
  579. sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]);
  580. return SR_ERR;
  581. }
  582.  
  583. header_length = 2 + buf[1] - '0';
  584.  
  585. /* Try to read the length. */
  586. if (devc->num_header_bytes < header_length) {
  587. ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes,
  588. header_length - devc->num_header_bytes);
  589. if (ret < 0) {
  590. sr_err("Read error while reading data header.");
  591. return SR_ERR;
  592. }
  593. devc->num_header_bytes += ret;
  594. }
  595.  
  596. if (devc->num_header_bytes < header_length)
  597. return 0;
  598.  
  599. /* Read the data length. */
  600. buf[header_length] = '\0';
  601.  
  602. if (parse_int(buf + 2, &ret) != SR_OK) {
  603. sr_err("Received invalid data block length '%s'.", buf + 2);
  604. return -1;
  605. }
  606.  
  607. sr_dbg("Received data block header: '%s' -> block length %d", buf, ret);
  608.  
  609. return ret;
  610. }
  611.  
  612. SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data)
  613. {
  614. struct sr_dev_inst *sdi;
  615. struct sr_scpi_dev_inst *scpi;
  616. struct dev_context *devc;
  617. struct sr_datafeed_packet packet;
  618. struct sr_datafeed_analog analog;
  619. struct sr_analog_encoding encoding;
  620. struct sr_analog_meaning meaning;
  621. struct sr_analog_spec spec;
  622. struct sr_datafeed_logic logic;
  623. double vdiv, offset, origin;
  624. int len, i, vref;
  625. struct sr_channel *ch;
  626. gsize expected_data_bytes;
  627.  
  628. (void)fd;
  629.  
  630. if (!(sdi = cb_data))
  631. return TRUE;
  632.  
  633. if (!(devc = sdi->priv))
  634. return TRUE;
  635.  
  636. scpi = sdi->conn;
  637.  
  638. if (!(revents == G_IO_IN || revents == 0))
  639. return TRUE;
  640.  
  641. const gboolean first_frame = (devc->num_frames == 0);
  642.  
  643. switch (devc->wait_event) {
  644. case WAIT_NONE:
  645. break;
  646. case WAIT_TRIGGER:
  647. if (rigol_ds_trigger_wait(sdi) != SR_OK)
  648. return TRUE;
  649. if (rigol_ds_channel_start(sdi) != SR_OK)
  650. return TRUE;
  651. return TRUE;
  652. case WAIT_BLOCK:
  653. if (rigol_ds_block_wait(sdi) != SR_OK)
  654. return TRUE;
  655. break;
  656. case WAIT_STOP:
  657. if (rigol_ds_stop_wait(sdi) != SR_OK)
  658. return TRUE;
  659. if (rigol_ds_check_stop(sdi) != SR_OK)
  660. return TRUE;
  661. if (rigol_ds_channel_start(sdi) != SR_OK)
  662. return TRUE;
  663. return TRUE;
  664. default:
  665. sr_err("BUG: Unknown event target encountered");
  666. break;
  667. }
  668.  
  669. ch = devc->channel_entry->data;
  670.  
  671. expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ?
  672. devc->analog_frame_size : devc->digital_frame_size;
  673.  
  674. if (devc->num_block_bytes == 0) {
  675. if (devc->model->series->protocol >= PROTOCOL_V4) {
  676. if (first_frame && rigol_ds_config_set(sdi, ":WAV:START %d",
  677. devc->num_channel_bytes + 1) != SR_OK)
  678. return TRUE;
  679. if (first_frame && rigol_ds_config_set(sdi, ":WAV:STOP %d",
  680. MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE,
  681. devc->analog_frame_size)) != SR_OK)
  682. return TRUE;
  683. }
  684.  
  685. if (devc->model->series->protocol >= PROTOCOL_V3) {
  686.  
  687. if (strcmp(devc->model->series->name, "DSO1000") == 0){
  688. /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */
  689. sr_spew("delay %dms", 100);
  690. g_usleep(100 * 1000);
  691. if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
  692. return TRUE;
  693.  
  694. }else{
  695. if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK)
  696. return TRUE;
  697. if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK)
  698. return TRUE;
  699. }
  700.  
  701. }
  702.  
  703. if (sr_scpi_read_begin(scpi) != SR_OK)
  704. return TRUE;
  705.  
  706. if (devc->format == FORMAT_IEEE488_2) {
  707. sr_dbg("New block header expected");
  708. len = rigol_ds_read_header(sdi);
  709. if (len == 0)
  710. /* Still reading the header. */
  711. return TRUE;
  712. if (len == -1) {
  713. sr_err("Error while reading block header, aborting capture.");
  714. std_session_send_df_frame_end(sdi);
  715. sr_dev_acquisition_stop(sdi);
  716. return TRUE;
  717. }
  718. /* At slow timebases in live capture the DS2072 and
  719. * DS1054Z sometimes return "short" data blocks, with
  720. * apparently no way to get the rest of the data.
  721. * Discard these, the complete data block will appear
  722. * eventually.
  723. */
  724. if (devc->data_source == DATA_SOURCE_LIVE
  725. && (unsigned)len < expected_data_bytes) {
  726. sr_dbg("Discarding short data block: got %d/%d bytes\n", len, (int)expected_data_bytes);
  727. sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1);
  728. devc->num_header_bytes = 0;
  729. return TRUE;
  730. }
  731. devc->num_block_bytes = len;
  732. } else {
  733. devc->num_block_bytes = expected_data_bytes;
  734. }
  735. devc->num_block_read = 0;
  736. }
  737.  
  738. len = devc->num_block_bytes - devc->num_block_read;
  739. if (len > ACQ_BUFFER_SIZE)
  740. len = ACQ_BUFFER_SIZE;
  741. sr_dbg("Requesting read of %d bytes", len);
  742.  
  743. len = sr_scpi_read_data(scpi, (char *)devc->buffer, len);
  744.  
  745. if (len == -1) {
  746. sr_err("Error while reading block data, aborting capture.");
  747. std_session_send_df_frame_end(sdi);
  748. sr_dev_acquisition_stop(sdi);
  749. return TRUE;
  750. }
  751.  
  752. sr_dbg("Received %d bytes.", len);
  753.  
  754. devc->num_block_read += len;
  755.  
  756. if (ch->type == SR_CHANNEL_ANALOG) {
  757. vref = devc->vert_reference[ch->index];
  758. vdiv = devc->vert_inc[ch->index];
  759. origin = devc->vert_origin[ch->index];
  760. offset = devc->vert_offset[ch->index];
  761. if (devc->model->series->protocol >= PROTOCOL_V3)
  762. for (i = 0; i < len; i++)
  763. devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv;
  764. else
  765. for (i = 0; i < len; i++)
  766. devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset;
  767. float vdivlog = log10f(vdiv);
  768. int digits = -(int)vdivlog + (vdivlog < 0.0);
  769. sr_analog_init(&analog, &encoding, &meaning, &spec, digits);
  770. analog.meaning->channels = g_slist_append(NULL, ch);
  771. analog.num_samples = len;
  772. analog.data = devc->data;
  773. analog.meaning->mq = SR_MQ_VOLTAGE;
  774. analog.meaning->unit = SR_UNIT_VOLT;
  775. analog.meaning->mqflags = 0;
  776. packet.type = SR_DF_ANALOG;
  777. packet.payload = &analog;
  778. sr_session_send(sdi, &packet);
  779. g_slist_free(analog.meaning->channels);
  780. } else {
  781. logic.length = len;
  782. // TODO: For the MSO1000Z series, we need a way to express that
  783. // this data is in fact just for a single channel, with the valid
  784. // data for that channel in the LSB of each byte.
  785. logic.unitsize = devc->model->series->protocol >= PROTOCOL_V4 ? 1 : 2;
  786. logic.data = devc->buffer;
  787. packet.type = SR_DF_LOGIC;
  788. packet.payload = &logic;
  789. sr_session_send(sdi, &packet);
  790. }
  791.  
  792. if (devc->num_block_read == devc->num_block_bytes) {
  793. sr_dbg("Block has been completed");
  794. if (devc->model->series->protocol >= PROTOCOL_V3) {
  795. /* Discard the terminating linefeed */
  796. sr_scpi_read_data(scpi, (char *)devc->buffer, 1);
  797. }
  798. if (devc->format == FORMAT_IEEE488_2) {
  799. /* Prepare for possible next block */
  800. devc->num_header_bytes = 0;
  801. devc->num_block_bytes = 0;
  802. if (devc->data_source != DATA_SOURCE_LIVE)
  803. rigol_ds_set_wait_event(devc, WAIT_BLOCK);
  804. }
  805. if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) {
  806. sr_err("Read should have been completed");
  807. }
  808. devc->num_block_read = 0;
  809. } else {
  810. sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read",
  811. devc->num_block_read, devc->num_block_bytes);
  812. }
  813.  
  814. devc->num_channel_bytes += len;
  815.  
  816. if (devc->num_channel_bytes < expected_data_bytes)
  817. /* Don't have the full data for this channel yet, re-run. */
  818. return TRUE;
  819.  
  820. /* End of data for this channel. */
  821. if (devc->model->series->protocol == PROTOCOL_V3) {
  822. /* Signal end of data download to scope */
  823. if (devc->data_source != DATA_SOURCE_LIVE)
  824. /*
  825. * This causes a query error, without it switching
  826. * to the next channel causes an error. Fun with
  827. * firmware...
  828. */
  829. rigol_ds_config_set(sdi, ":WAV:END");
  830. }
  831.  
  832. if (devc->channel_entry->next) {
  833. /* We got the frame for this channel, now get the next channel. */
  834. devc->channel_entry = devc->channel_entry->next;
  835. rigol_ds_channel_start(sdi);
  836. } else {
  837. /* Done with this frame. */
  838. std_session_send_df_frame_end(sdi);
  839.  
  840. devc->num_frames++;
  841.  
  842. /* V5 has no way to read the number of recorded frames, so try to set the
  843. * next frame and read it back instead.
  844. */
  845. if (devc->data_source == DATA_SOURCE_SEGMENTED &&
  846. devc->model->series->protocol == PROTOCOL_V5) {
  847. int frames = 0;
  848. if (rigol_ds_config_set(sdi, "REC:CURR %d", devc->num_frames + 1) != SR_OK)
  849. return SR_ERR;
  850. if (sr_scpi_get_int(sdi->conn, "REC:CURR?", &frames) != SR_OK)
  851. return SR_ERR;
  852. devc->num_frames_segmented = frames;
  853. }
  854.  
  855. if (devc->num_frames == devc->limit_frames ||
  856. devc->num_frames == devc->num_frames_segmented ||
  857. devc->data_source == DATA_SOURCE_MEMORY) {
  858. /* Last frame, stop capture. */
  859. sr_dev_acquisition_stop(sdi);
  860. } else {
  861. /* Get the next frame, starting with the first channel. */
  862. devc->channel_entry = devc->enabled_channels;
  863.  
  864. rigol_ds_capture_start(sdi);
  865.  
  866. /* Start of next frame. */
  867. std_session_send_df_frame_begin(sdi);
  868. }
  869. }
  870.  
  871. return TRUE;
  872. }
  873.  
  874. SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi)
  875. {
  876. struct dev_context *devc;
  877. struct sr_channel *ch;
  878. char *cmd;
  879. unsigned int i;
  880. int res;
  881.  
  882. devc = sdi->priv;
  883.  
  884. /* Analog channel state. */
  885. for (i = 0; i < devc->model->analog_channels; i++) {
  886. cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1);
  887. res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]);
  888. g_free(cmd);
  889. if (res != SR_OK)
  890. return SR_ERR;
  891. ch = g_slist_nth_data(sdi->channels, i);
  892. ch->enabled = devc->analog_channels[i];
  893. }
  894. sr_dbg("Current analog channel state:");
  895. for (i = 0; i < devc->model->analog_channels; i++)
  896. sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off");
  897.  
  898. /* Digital channel state. */
  899. if (devc->model->has_digital) {
  900. if (sr_scpi_get_bool(sdi->conn,
  901. devc->model->series->protocol >= PROTOCOL_V3 ?
  902. ":LA:STAT?" : ":LA:DISP?",
  903. &devc->la_enabled) != SR_OK)
  904. return SR_ERR;
  905. sr_dbg("Logic analyzer %s, current digital channel state:",
  906. devc->la_enabled ? "enabled" : "disabled");
  907. for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
  908. if (devc->model->series->protocol >= PROTOCOL_V5)
  909. cmd = g_strdup_printf(":LA:DISP? D%d", i);
  910. else if (devc->model->series->protocol >= PROTOCOL_V3)
  911. cmd = g_strdup_printf(":LA:DIG%d:DISP?", i);
  912. else
  913. cmd = g_strdup_printf(":DIG%d:TURN?", i);
  914. res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]);
  915. g_free(cmd);
  916. if (res != SR_OK)
  917. return SR_ERR;
  918. ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels);
  919. ch->enabled = devc->digital_channels[i];
  920. sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off");
  921. }
  922. }
  923.  
  924. /* Timebase. */
  925. if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK)
  926. return SR_ERR;
  927. sr_dbg("Current timebase %g", devc->timebase);
  928.  
  929. /* Probe attenuation. */
  930. for (i = 0; i < devc->model->analog_channels; i++) {
  931. cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1);
  932.  
  933. /* DSO1000B series prints an X after the probe factor, so
  934. * we get a string and check for that instead of only handling
  935. * floats. */
  936. char *response;
  937. res = sr_scpi_get_string(sdi->conn, cmd, &response);
  938. if (res != SR_OK)
  939. return SR_ERR;
  940.  
  941. int len = strlen(response);
  942. if (response[len-1] == 'X')
  943. response[len-1] = 0;
  944.  
  945. res = sr_atof_ascii(response, &devc->attenuation[i]);
  946. g_free(response);
  947. g_free(cmd);
  948. if (res != SR_OK)
  949. return SR_ERR;
  950. }
  951. sr_dbg("Current probe attenuation:");
  952. for (i = 0; i < devc->model->analog_channels; i++)
  953. sr_dbg("CH%d %g", i + 1, devc->attenuation[i]);
  954.  
  955. /* Vertical gain and offset. */
  956. if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK)
  957. return SR_ERR;
  958.  
  959. /* Coupling. */
  960. for (i = 0; i < devc->model->analog_channels; i++) {
  961. cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1);
  962. res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]);
  963. g_free(cmd);
  964. if (res != SR_OK)
  965. return SR_ERR;
  966. }
  967. sr_dbg("Current coupling:");
  968. for (i = 0; i < devc->model->analog_channels; i++)
  969. sr_dbg("CH%d %s", i + 1, devc->coupling[i]);
  970.  
  971. /* Trigger source. */
  972. if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK)
  973. return SR_ERR;
  974. sr_dbg("Current trigger source %s", devc->trigger_source);
  975.  
  976. /* Horizontal trigger position. */
  977. if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str,
  978. &devc->horiz_triggerpos) != SR_OK)
  979. return SR_ERR;
  980. sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos);
  981.  
  982. /* Trigger slope. */
  983. if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK)
  984. return SR_ERR;
  985. sr_dbg("Current trigger slope %s", devc->trigger_slope);
  986.  
  987. /* Trigger level. */
  988. if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK)
  989. return SR_ERR;
  990. sr_dbg("Current trigger level %g", devc->trigger_level);
  991.  
  992. return SR_OK;
  993. }
  994.  
  995. SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi)
  996. {
  997. struct dev_context *devc;
  998. char *cmd;
  999. unsigned int i;
  1000. int res;
  1001.  
  1002. devc = sdi->priv;
  1003.  
  1004. /* Vertical gain. */
  1005. for (i = 0; i < devc->model->analog_channels; i++) {
  1006. cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1);
  1007. res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]);
  1008. g_free(cmd);
  1009. if (res != SR_OK)
  1010. return SR_ERR;
  1011. }
  1012. sr_dbg("Current vertical gain:");
  1013. for (i = 0; i < devc->model->analog_channels; i++)
  1014. sr_dbg("CH%d %g", i + 1, devc->vdiv[i]);
  1015.  
  1016. /* Vertical offset. */
  1017. for (i = 0; i < devc->model->analog_channels; i++) {
  1018. cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1);
  1019. res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]);
  1020. g_free(cmd);
  1021. if (res != SR_OK)
  1022. return SR_ERR;
  1023. }
  1024. sr_dbg("Current vertical offset:");
  1025. for (i = 0; i < devc->model->analog_channels; i++)
  1026. sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]);
  1027.  
  1028. return SR_OK;
  1029. }
  1030.  
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