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XikeStor SKS8300-8T OpenWrt bootlader -> RTL8261N driver

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Jun 24th, 2025
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  1. 0.907849] Using MAC 00008243e6800000
  2. [ 0.912089] set sds port 0 to 2
  3. [ 0.915582] set sds port 8 to 3
  4. [ 0.919139] set sds port 16 to 4
  5. [ 0.922734] set sds port 20 to 5
  6. [ 0.926323] set sds port 24 to 6
  7. [ 0.929935] set sds port 25 to 7
  8. [ 0.933529] set sds port 26 to 8
  9. [ 0.937142] set sds port 27 to 9
  10. [ 0.941607] c45_mask: 00000000
  11. [ 1.021476] Realtek RTL8261N mdio-bus:00: Detected PHY type: 1, PHY addr: 0, isBasePort: 1
  12. [ 1.108576] Realtek RTL8261N mdio-bus:08: Detected PHY type: 1, PHY addr: 8, isBasePort: 1
  13. [ 1.195677] Realtek RTL8261N mdio-bus:10: Detected PHY type: 1, PHY addr: 16, isBasePort: 1
  14. [ 1.283502] Realtek RTL8261N mdio-bus:14: Detected PHY type: 1, PHY addr: 20, isBasePort: 1
  15. [ 1.370602] Realtek RTL8261N mdio-bus:18: Detected PHY type: 1, PHY addr: 24, isBasePort: 1
  16. [ 1.457703] Realtek RTL8261N mdio-bus:19: Detected PHY type: 1, PHY addr: 25, isBasePort: 1
  17. [ 1.544803] Realtek RTL8261N mdio-bus:1a: Detected PHY type: 1, PHY addr: 26, isBasePort: 1
  18. [ 1.631904] Realtek RTL8261N mdio-bus:1b: Detected PHY type: 1, PHY addr: 27, isBasePort: 1
  19. [ 1.647562] i2c_dev: i2c /dev entries driver
  20. [ 1.652549] rtl9300_i2c_probe probing I2C adapter
  21. [ 1.657970] i2c-rtl9300 1b00036c.i2c: SCL speed 100000, mode is 0
  22. [ 1.664772] rtl9300_i2c_probe scl_num 0
  23. [ 1.669088] rtl9300_i2c_probe sda_num 0
  24. [ 1.678316] NET: Registered PF_INET6 protocol family
  25. [ 1.703166] Segment Routing with IPv6
  26. [ 1.707479] In-situ OAM (IOAM) with IPv6
  27. [ 1.712095] NET: Registered PF_PACKET protocol family
  28. [ 1.718286] 8021q: 802.1Q VLAN Support v1.8
  29. [ 1.793917] REALTEK RTL9300 SERDES rtldsa_mdio-0:00: Detected internal RTL9300 Serdes
  30. [ 1.830363] REALTEK RTL9300 SERDES rtldsa_mdio-0:08: Detected internal RTL9300 Serdes
  31. [ 1.866624] REALTEK RTL9300 SERDES rtldsa_mdio-0:10: Detected internal RTL9300 Serdes
  32. [ 1.903160] REALTEK RTL9300 SERDES rtldsa_mdio-0:14: Detected internal RTL9300 Serdes
  33. [ 1.939554] REALTEK RTL9300 SERDES rtldsa_mdio-0:18: Detected internal RTL9300 Serdes
  34. [ 1.975681] REALTEK RTL9300 SERDES rtldsa_mdio-0:19: Detected internal RTL9300 Serdes
  35. [ 2.012059] REALTEK RTL9300 SERDES rtldsa_mdio-0:1a: Detected internal RTL9300 Serdes
  36. [ 2.048434] REALTEK RTL9300 SERDES rtldsa_mdio-0:1b: Detected internal RTL9300 Serdes
  37. [ 2.082969] rtl93xx_setup called
  38. [ 2.086627] In rtl83xx_vlan_setup
  39. [ 2.090385] UNKNOWN_MC_PMASK: 000000001fffffff
  40. [ 3.136984] rtl83xx_enable_phy_polling: f110101
  41. [ 3.143245] rtl930x_led_init led_set configuration invalid skipping over this set
  42. [ 3.151617] rtl930x_led_init led_set configuration invalid skipping over this set
  43. [ 3.159976] rtl930x_led_init led_set configuration invalid skipping over this set
  44. [ 3.168540] rtl83xx-switch switch@1b000000: configuring for fixed/internal link mode
  45. [ 3.177469] Realtek RTL8261N mdio-bus:00: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:0
  46. [ 3.187727] Realtek RTL8261N mdio-bus:00: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  47. [ 6.685342[rtkphy_config_init,158] patch chk PASS
  48. [ 6.693512[rtkphy_config_init,166] PHY0: SDS 0x07, 0x10 : 0x8003
  49. [ 6.703133[rtkphy_config_init,169] PHY0: SDS 0x06, 0x12 : 0xA4
  50. [ 6.712753[rtkphy_config_init,174] PHY0: SDS 0x05, 0x00 : 0x100D (link UP)
  51. [ 6.721035] rtl83xx-switch switch@1b000000 lan1 (uninitialized): PH[mdio-bus:00] drive[Realtek RTL8261N] (irq=POLL)
  52. [ 6.734818] Realtek RTL8261N mdio-bus:08: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:8
  53. [ 6.745110] Realtek RTL8261N mdio-bus:08: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  54. [ 10.220416[rtkphy_config_init,158] patch chk PASS
  55. [ 10.228587[rtkphy_config_init,166] PHY8: SDS 0x07, 0x10 : 0x8003
  56. [ 10.238207[rtkphy_config_init,169] PHY8: SDS 0x06, 0x12 : 0xA4
  57. [ 10.247828[rtkphy_config_init,174] PHY8: SDS 0x05, 0x00 : 0x100D (link UP)
  58. [ 10.256049] rtl83xx-switch switch@1b000000 lan2 (uninitialized): PH[mdio-bus:08] drive[Realtek RTL8261N] (irq=POLL)
  59. [ 10.269825] Realtek RTL8261N mdio-bus:10: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:16
  60. [ 10.280198] Realtek RTL8261N mdio-bus:10: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  61. [ 13.768990[rtkphy_config_init,158] patch chk PASS
  62. [ 13.777160[rtkphy_config_init,166] PHY16: SDS 0x07, 0x10 : 0x8003
  63. [ 13.786780[rtkphy_config_init,169] PHY16: SDS 0x06, 0x12 : 0xA4
  64. [ 13.796401[rtkphy_config_init,174] PHY16: SDS 0x05, 0x00 : 0x100D (link UP)
  65. [ 13.805419] rtl83xx-switch switch@1b000000 lan3 (uninitialized): PH[mdio-bus:10] drive[Realtek RTL8261N] (irq=POLL)
  66. [ 13.819160] Realtek RTL8261N mdio-bus:14: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:20
  67. [ 13.829534] Realtek RTL8261N mdio-bus:14: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  68. [ 17.304789[rtkphy_config_init,158] patch chk PASS
  69. [ 17.312959[rtkphy_config_init,166] PHY20: SDS 0x07, 0x10 : 0x8003
  70. [ 17.322579[rtkphy_config_init,169] PHY20: SDS 0x06, 0x12 : 0xA4
  71. [ 17.332200[rtkphy_config_init,174] PHY20: SDS 0x05, 0x00 : 0x100D (link UP)
  72. [ 17.341257] rtl83xx-switch switch@1b000000 lan4 (uninitialized): PH[mdio-bus:14] drive[Realtek RTL8261N] (irq=POLL)
  73. [ 17.354929] Realtek RTL8261N mdio-bus:18: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:24
  74. [ 17.365300] Realtek RTL8261N mdio-bus:18: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  75. [ 20.868362[rtkphy_config_init,158] patch chk PASS
  76. [ 20.876532[rtkphy_config_init,166] PHY24: SDS 0x07, 0x10 : 0x8003
  77. [ 20.886152[rtkphy_config_init,169] PHY24: SDS 0x06, 0x12 : 0xA4
  78. [ 20.895773[rtkphy_config_init,174] PHY24: SDS 0x05, 0x00 : 0x100D (link UP)
  79. [ 20.904720] rtl83xx-switch switch@1b000000 lan5 (uninitialized): PH[mdio-bus:18] drive[Realtek RTL8261N] (irq=POLL)
  80. [ 20.918575] Realtek RTL8261N mdio-bus:19: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:25
  81. [ 20.928952] Realtek RTL8261N mdio-bus:19: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  82. [ 24.404936[rtkphy_config_init,158] patch chk PASS
  83. [ 24.413106[rtkphy_config_init,166] PHY25: SDS 0x07, 0x10 : 0x8003
  84. [ 24.422727[rtkphy_config_init,169] PHY25: SDS 0x06, 0x12 : 0xA4
  85. [ 24.432347[rtkphy_config_init,174] PHY25: SDS 0x05, 0x00 : 0x100D (link UP)
  86. [ 24.441295] rtl83xx-switch switch@1b000000 lan6 (uninitialized): PH[mdio-bus:19] drive[Realtek RTL8261N] (irq=POLL)
  87. [ 24.454979] Realtek RTL8261N mdio-bus:1a: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:26
  88. [ 24.465349] Realtek RTL8261N mdio-bus:1a: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  89. [ 27.955734[rtkphy_config_init,158] patch chk PASS
  90. [ 27.963904[rtkphy_config_init,166] PHY26: SDS 0x07, 0x10 : 0x8003
  91. [ 27.973525[rtkphy_config_init,169] PHY26: SDS 0x06, 0x12 : 0xA4
  92. [ 27.983145[rtkphy_config_init,174] PHY26: SDS 0x05, 0x00 : 0x100D (link UP)
  93. [ 27.992096] rtl83xx-switch switch@1b000000 lan7 (uninitialized): PH[mdio-bus:1a] drive[Realtek RTL8261N] (irq=POLL)
  94. [ 28.005748] Realtek RTL8261N mdio-bus:1b: rtkphy_config_init:11[RTL826XB] phy_id: 0x1CCAF3 PHYAD:27
  95. [ 28.016117] Realtek RTL8261N mdio-bus:1b: PHY type: 1 (RTL8261N/BE), isBasePort: 1, portOffset: 0
  96. [ 31.489308[rtkphy_config_init,158] patch chk PASS
  97. [ 31.497479[rtkphy_config_init,166] PHY27: SDS 0x07, 0x10 : 0x8003
  98. [ 31.507099[rtkphy_config_init,169] PHY27: SDS 0x06, 0x12 : 0xA4
  99. [ 31.516719[rtkphy_config_init,174] PHY27: SDS 0x05, 0x00 : 0x100D (link UP)
  100. [ 31.525730] rtl83xx-switch switch@1b000000 lan8 (uninitialized): PH[mdio-bus:1b] drive[Realtek RTL8261N] (irq=POLL)
  101. [ 31.539607] rtl838x-eth 1b00a300.ethernet eth0: entered promiscuous mode
  102. [ 31.547287] DSA: tree 0 setup
  103. [ 31.550688] LINK state irq: 23
  104. [ 31.554130] In rtl83xx_setup_qos
  105. [ 31.557984] rtl930x_dbgfs_init called
  106. [ 31.562178] rtl83xx-switch switch@1b000000: Link is Up - 10Gbps/Full - flow control off
  107. [ 31.571214] rtl83xx_fib_event_work_do: FIB4 default rule failed
  108. [ 31.577874] rtl83xx_fib_event_work_do: FIB4 default rule failed
  109. [ 31.599578] clk: Disabling unused clocks
  110. [ 31.651617] Freeing unused kernel image (initmem) memory: 9692K
  111. [ 31.658282] This architecture does not have kernel memory protection.
  112. [ 31.665460] Run /init as init process
  113. [ 31.669568] with arguments:
  114. [ 31.672870] /init
  115. [ 31.675388] with environment:
  116. [ 31.678909] HOME=/
  117. [ 31.681534] TERM=linux
  118. [ 32.182946] init: Console is alive
  119. [ 32.187404] init: - watchdog -
  120. [ 32.208346] kmodloader: loading kernel modules from /etc/modules-boot.d/*
  121. [ 32.219854] gpio_button_hotplug: loading out-of-tree module taints kernel.
  122. [ 32.233124] kmodloader: done loading kernel modules from /etc/modules-boot.d/*
  123. [ 32.252112] init: - preinit -
  124. [ 34.787041] random: crng init done
  125.  
  126.  
  127. Cannot parse config file '/etc/fw_env.config': No such file or directory
  128.  
  129.  
  130. Failed to find NVMEM device
  131. [ 35.812100] RESETTING 9300, CPU_PORT 28
  132. [ 36.016951] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
  133. [ 36.025954] In rtl838x_mac_config, mode 1
  134. [ 36.031319] rtl83xx-switch switch@1b000000 lan1: configuring for phy/usxgmii link mode
  135. [ 36.040240] rtl93xx_phylink_mac_config SDS is 2
  136. [ 36.045283] Configuring SerDes 2 for USXGMII mode
  137. [ 36.050535] rtl9300_sds_rst 31
  138. [ 36.073901] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 2
  139. [ 36.140079] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  140. [ 36.147120] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  141. [ 36.154900] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  142. [ 36.162018] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  143. [ 36.169744] rtl9300_phy_enable_10g_1g set medium: 00000002
  144. [ 36.176851] rtl9300_phy_enable_10g_1g set medium after: 00000002
  145. [ 36.205519] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  146. [ 36.217584] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  147. [ 36.225523] rtl9300_force_sds_mode: SDS: 2, mode 30
  148. [ 36.230965] rtl9300_force_sds_mode: serdes 2 forcing to d
  149. [ 36.269966] rtl9300_force_sds_mode: serdes 2 forced to d DONE
  150. [ 36.281382] start_1.1.1 initial value for sds 2
  151. [ 36.343353] end_1.1.1 --
  152. [ 36.346175] start_1.1.2 Load DFE init. value
  153. [ 36.352934] end_1.1.2
  154. [ 36.355458] start_1.1.3 disable LEQ training,enable DFE clock
  155. [ 36.373862] end_1.1.3 --
  156. [ 36.376684] start_1.1.4 offset cali setting
  157. [ 36.383345] end_1.1.4
  158. [ 36.385872] start_1.1.5 LEQ and DFE setting
  159. [ 36.404517] end_1.1.5
  160. [ 36.416041] start_1.2.1 ForegroundOffsetCal_Manual
  161. [ 36.425382] end_1.2.1
  162. [ 36.436376] start_1.2.3 Foreground Calibration
  163. [ 36.454846] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  164. [ 36.463519] rtl9300_do_rx_calibration_2_3: end_1.2.3
  165. [ 36.469078] start_1.4.1
  166. [ 36.692645] end_1.4.1
  167. [ 36.695373] start_1.4.2
  168. [ 36.707909] vth_set_bin = 3
  169. [ 36.710635] vth_set_bin = 3
  170. [ 36.714731] Vth Maunal = 0
  171. [ 36.833677] Tap0 Sign : +
  172. [ 36.836703] tap0_coef_bin = 19
  173. [ 36.840630] tap0 manual = 0
  174. [ 36.850038] end_1.4.2
  175. [ 36.951458] 8021q: adding VLAN 0 to HW filter on device lan1
  176. [ 36.960614] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
  177. [ 36.980403] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  178. [ 36.987859] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  179. [ 37.003405] rtl83xx_fib_event_work_do: FIB4 failed
  180. [ 37.008913] rtl83xx_fib_event_work_do: FIB4 failed
  181. [ 37.014261] rtl83xx_fib_event_work_do: FIB4 failed
  182.  
  183.  
  184. Press th[f] key and hi[enter] to enter failsafe mode
  185.  
  186.  
  187. Press th[1][2][3] o[4] key and hi[enter] to select the debug level
  188. [ 38.897048] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  189. [ 40.099090] Realtek RTL8261N mdio-bus:00: PHY 0 link state changed: DOWN -> UP
  190. [ 40.107207] Realtek RTL8261N mdio-bus:00: WARNING: This is PHY 0, check if PHY 24 also changes
  191. [ 40.120407] rtl83xx-switch switch@1b000000 lan1: Link is Up - 1Gbps/Full - flow control rx/tx
  192. [ 41.241141] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  193. [ 41.246902] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  194. [ 41.259951] rtl83xx-switch switch@1b000000 lan1: Link is Down
  195. [ 41.277892] rtl83xx_fib4_del: no such gateway: 0.0.0.0
  196. [ 41.286851] procd: - early -
  197. [ 41.290673] procd: - watchdog -
  198. [ 41.942807] procd: - watchdog -
  199. [ 41.946884] procd: - ubus -
  200. [ 42.006691] procd: - init -
  201.  
  202.  
  203. Please press Enter to activate this console.
  204. [ 42.898652] kmodloader: loading kernel modules from /etc/modules.d/*
  205. [ 43.069997] kmodloader: done loading kernel modules from /etc/modules.d/*
  206. [ 44.600601] urngd: v1.0.2 started.
  207. [ 48.176640] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  208. [ 66.456681] in rtl838x_eth_stop
  209. [ 66.460406] rtl838x-eth 1b00a300.ethernet eth0: Link is Down
  210. [ 66.989836] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  211. [ 66.997244] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  212. [ 67.004552] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  213. [ 67.011918] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  214. [ 67.221766] RESETTING 9300, CPU_PORT 28
  215. [ 67.426624] rtl838x-eth 1b00a300.ethernet eth0: configuring for fixed/internal link mode
  216. [ 67.435627] In rtl838x_mac_config, mode 1
  217. [ 67.442010] rtl838x-eth 1b00a300.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
  218. [ 67.460816] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  219. [ 67.468288] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  220. [ 67.591381] rtl83xx-switch switch@1b000000 lan1: configuring for phy/usxgmii link mode
  221. [ 67.600304] rtl93xx_phylink_mac_config SDS is 2
  222. [ 67.605344] Configuring SerDes 2 for USXGMII mode
  223. [ 67.610624] rtl9300_sds_rst 31
  224. [ 67.634008] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 2
  225. [ 67.700216] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  226. [ 67.707257] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  227. [ 67.715040] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  228. [ 67.722163] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  229. [ 67.729877] rtl9300_phy_enable_10g_1g set medium: 00000002
  230. [ 67.737009] rtl9300_phy_enable_10g_1g set medium after: 00000002
  231. [ 67.765673] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  232. [ 67.777761] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  233. [ 67.785708] rtl9300_force_sds_mode: SDS: 2, mode 30
  234. [ 67.791161] rtl9300_force_sds_mode: serdes 2 forcing to d
  235. [ 67.830150] rtl9300_force_sds_mode: serdes 2 forced to d DONE
  236. [ 67.841571] start_1.1.1 initial value for sds 2
  237. [ 67.903577] end_1.1.1 --
  238. [ 67.906401] start_1.1.2 Load DFE init. value
  239. [ 67.913166] end_1.1.2
  240. [ 67.915695] start_1.1.3 disable LEQ training,enable DFE clock
  241. [ 67.934090] end_1.1.3 --
  242. [ 67.936911] start_1.1.4 offset cali setting
  243. [ 67.943578] end_1.1.4
  244. [ 67.946107] start_1.1.5 LEQ and DFE setting
  245. [ 67.964761] end_1.1.5
  246. [ 67.976287] start_1.2.1 ForegroundOffsetCal_Manual
  247. [ 67.985632] end_1.2.1
  248. [ 67.996640] start_1.2.3 Foreground Calibration
  249. [ 68.015152] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  250. [ 68.023852] rtl9300_do_rx_calibration_2_3: end_1.2.3
  251. [ 68.029408] start_1.4.1
  252. [ 68.253028] end_1.4.1
  253. [ 68.255759] start_1.4.2
  254. [ 68.268296] vth_set_bin = 3
  255. [ 68.271021] vth_set_bin = 3
  256. [ 68.275115] Vth Maunal = 0
  257. [ 68.394044] Tap0 Sign : +
  258. [ 68.397084] tap0_coef_bin = 18
  259. [ 68.400997] tap0 manual = 0
  260. [ 68.410401] end_1.4.2
  261. [ 68.512099] 8021q: adding VLAN 0 to HW filter on device lan1
  262. [ 68.534075] Realtek RTL8261N mdio-bus:00: PHY 0 link state changed: UP -> DOWN
  263. [ 68.542225] Realtek RTL8261N mdio-bus:00: WARNING: This is PHY 0, check if PHY 24 also changes
  264. [ 68.617907] switch: port 1(lan1) entered blocking state
  265. [ 68.623765] switch: port 1(lan1) entered disabled state
  266. [ 68.629731] rtl83xx-switch switch@1b000000 lan1: entered allmulticast mode
  267. [ 68.637462] rtl838x-eth 1b00a300.ethernet eth0: entered allmulticast mode
  268. [ 68.645931] rtl83xx-switch switch@1b000000 lan1: entered promiscuous mode
  269. [ 68.795071] rtl83xx-switch switch@1b000000 lan2: configuring for phy/usxgmii link mode
  270. [ 68.803991] rtl93xx_phylink_mac_config SDS is 3
  271. [ 68.809088] Configuring SerDes 3 for USXGMII mode
  272. [ 68.814325] rtl9300_sds_rst 31
  273. [ 68.837710] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 3
  274. [ 68.903889] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  275. [ 68.910936] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  276. [ 68.918756] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  277. [ 68.925863] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  278. [ 68.933565] rtl9300_phy_enable_10g_1g set medium: 00000002
  279. [ 68.940700] rtl9300_phy_enable_10g_1g set medium after: 00000002
  280. [ 68.969374] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  281. [ 68.981438] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  282. [ 68.989424] rtl9300_force_sds_mode: SDS: 3, mode 30
  283. [ 68.994854] rtl9300_force_sds_mode: serdes 3 forcing to d
  284. [ 69.033834] rtl9300_force_sds_mode: serdes 3 forced to d DONE
  285. [ 69.045246] start_1.1.1 initial value for sds 3
  286. [ 69.107294] end_1.1.1 --
  287. [ 69.110126] start_1.1.2 Load DFE init. value
  288. [ 69.116857] end_1.1.2
  289. [ 69.119418] start_1.1.3 disable LEQ training,enable DFE clock
  290. [ 69.137826] end_1.1.3 --
  291. [ 69.140643] start_1.1.4 offset cali setting
  292. [ 69.147307] end_1.1.4
  293. [ 69.149841] start_1.1.5 LEQ and DFE setting
  294. [ 69.168488] end_1.1.5
  295. [ 69.180023] start_1.2.1 ForegroundOffsetCal_Manual
  296. [ 69.189372] end_1.2.1
  297. [ 69.200383] start_1.2.3 Foreground Calibration
  298. [ 69.218859] rtl9300_do_rx_calibration_2_3: fgcal_gray: 18, fgcal_binary 27
  299. [ 69.227545] rtl9300_do_rx_calibration_2_3: end_1.2.3
  300. [ 69.233076] start_1.4.1
  301. [ 69.456658] end_1.4.1
  302. [ 69.459407] start_1.4.2
  303. [ 69.471941] vth_set_bin = 4
  304. [ 69.474666] vth_set_bin = 4
  305. [ 69.478795] Vth Maunal = 0
  306. [ 69.597774] Tap0 Sign : +
  307. [ 69.600803] tap0_coef_bin = 20
  308. [ 69.604704] tap0 manual = 0
  309. [ 69.614104] end_1.4.2
  310. [ 69.715520] 8021q: adding VLAN 0 to HW filter on device lan2
  311. [ 69.736793] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  312. [ 69.744239] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
  313. [ 70.125805] switch: port 2(lan2) entered blocking state
  314. [ 70.131732] switch: port 2(lan2) entered disabled state
  315. [ 70.137666] rtl83xx-switch switch@1b000000 lan2: entered allmulticast mode
  316. [ 70.146235] rtl83xx-switch switch@1b000000 lan2: entered promiscuous mode
  317. [ 70.332628] rtl83xx-switch switch@1b000000 lan3: configuring for phy/usxgmii link mode
  318. [ 70.341542] rtl93xx_phylink_mac_config SDS is 4
  319. [ 70.346587] Configuring SerDes 4 for USXGMII mode
  320. [ 70.351865] rtl9300_sds_rst 31
  321. [ 70.375249] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 4
  322. [ 70.441433] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  323. [ 70.448467] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  324. [ 70.456245] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  325. [ 70.463368] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  326. [ 70.471083] rtl9300_phy_enable_10g_1g set medium: 00000002
  327. [ 70.478219] rtl9300_phy_enable_10g_1g set medium after: 00000002
  328. [ 70.506880] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  329. [ 70.518974] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  330. [ 70.526923] rtl9300_force_sds_mode: SDS: 4, mode 30
  331. [ 70.532384] rtl9300_force_sds_mode: serdes 4 forcing to d
  332. [ 70.571375] rtl9300_force_sds_mode: serdes 4 forced to d DONE
  333. [ 70.582791] start_1.1.1 initial value for sds 4
  334. [ 70.644793] end_1.1.1 --
  335. [ 70.647640] start_1.1.2 Load DFE init. value
  336. [ 70.654386] end_1.1.2
  337. [ 70.656901] start_1.1.3 disable LEQ training,enable DFE clock
  338. [ 70.675298] end_1.1.3 --
  339. [ 70.678142] start_1.1.4 offset cali setting
  340. [ 70.684789] end_1.1.4
  341. [ 70.687334] start_1.1.5 LEQ and DFE setting
  342. [ 70.705979] end_1.1.5
  343. [ 70.717526] start_1.2.1 ForegroundOffsetCal_Manual
  344. [ 70.726845] end_1.2.1
  345. [ 70.737872] start_1.2.3 Foreground Calibration
  346. [ 70.756371] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 30
  347. [ 70.765068] rtl9300_do_rx_calibration_2_3: end_1.2.3
  348. [ 70.770624] start_1.4.1
  349. [ 70.994219] end_1.4.1
  350. [ 70.996948] start_1.4.2
  351. [ 71.009483] vth_set_bin = 7
  352. [ 71.012211] vth_set_bin = 7
  353. [ 71.016304] Vth Maunal = 0
  354. [ 71.135210] Tap0 Sign : +
  355. [ 71.138247] tap0_coef_bin = 12
  356. [ 71.142160] tap0 manual = 0
  357. [ 71.151556] end_1.4.2
  358. [ 71.253074] 8021q: adding VLAN 0 to HW filter on device lan3
  359. [ 71.296831] Realtek RTL8261N mdio-bus:00: PHY 0 link state changed: DOWN -> UP
  360. [ 71.304988] Realtek RTL8261N mdio-bus:00: WARNING: This is PHY 0, check if PHY 24 also changes
  361. [ 71.326654] rtl83xx-switch switch@1b000000 lan1: Link is Up - 10Gbps/Full - flow control rx/tx
  362. [ 71.344319] switch: port 1(lan1) entered blocking state
  363. [ 71.350252] switch: port 1(lan1) entered forwarding state
  364. [ 71.547898] switch: port 3(lan3) entered blocking state
  365. [ 71.553750] switch: port 3(lan3) entered disabled state
  366. [ 71.559710] rtl83xx-switch switch@1b000000 lan3: entered allmulticast mode
  367. [ 71.617683] rtl83xx-switch switch@1b000000 lan3: entered promiscuous mode
  368. [ 71.692466] rtl83xx-switch switch@1b000000 lan4: configuring for phy/usxgmii link mode
  369. [ 71.701379] rtl93xx_phylink_mac_config SDS is 5
  370. [ 71.706420] Configuring SerDes 5 for USXGMII mode
  371. [ 71.711698] rtl9300_sds_rst 31
  372. [ 71.735094] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 5
  373. [ 71.801320] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  374. [ 71.808374] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  375. [ 71.816149] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  376. [ 71.823274] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  377. [ 71.830988] rtl9300_phy_enable_10g_1g set medium: 00000002
  378. [ 71.838134] rtl9300_phy_enable_10g_1g set medium after: 00000002
  379. [ 71.866799] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  380. [ 71.878866] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  381. [ 71.886811] rtl9300_force_sds_mode: SDS: 5, mode 30
  382. [ 71.892264] rtl9300_force_sds_mode: serdes 5 forcing to d
  383. [ 71.931251] rtl9300_force_sds_mode: serdes 5 forced to d DONE
  384. [ 71.942668] start_1.1.1 initial value for sds 5
  385. [ 72.004664] end_1.1.1 --
  386. [ 72.007510] start_1.1.2 Load DFE init. value
  387. [ 72.014255] end_1.1.2
  388. [ 72.016770] start_1.1.3 disable LEQ training,enable DFE clock
  389. [ 72.035171] end_1.1.3 --
  390. [ 72.038043] start_1.1.4 offset cali setting
  391. [ 72.044720] end_1.1.4
  392. [ 72.047285] start_1.1.5 LEQ and DFE setting
  393. [ 72.065946] end_1.1.5
  394. [ 72.077499] start_1.2.1 ForegroundOffsetCal_Manual
  395. [ 72.086820] end_1.2.1
  396. [ 72.097833] start_1.2.3 Foreground Calibration
  397. [ 72.116291] rtl9300_do_rx_calibration_2_3: fgcal_gray: 21, fgcal_binary 29
  398. [ 72.124974] rtl9300_do_rx_calibration_2_3: end_1.2.3
  399. [ 72.130527] start_1.4.1
  400. [ 72.354129] end_1.4.1
  401. [ 72.356860] start_1.4.2
  402. [ 72.369398] vth_set_bin = 2
  403. [ 72.372124] vth_set_bin = 2
  404. [ 72.376218] Vth Maunal = 0
  405. [ 72.495117] Tap0 Sign : +
  406. [ 72.498169] tap0_coef_bin = 15
  407. [ 72.502083] tap0 manual = 0
  408. [ 72.511494] end_1.4.2
  409. [ 72.612932] 8021q: adding VLAN 0 to HW filter on device lan4
  410. [ 72.897626] switch: port 4(lan4) entered blocking state
  411. [ 72.903481] switch: port 4(lan4) entered disabled state
  412. [ 72.909442] rtl83xx-switch switch@1b000000 lan4: entered allmulticast mode
  413. [ 72.937718] rtl83xx-switch switch@1b000000 lan4: entered promiscuous mode
  414. [ 72.991753] rtl83xx-switch switch@1b000000 lan1: Link is Down
  415. [ 72.998328] switch: port 1(lan1) entered disabled state
  416. [ 73.004571] rtl83xx-switch switch@1b000000 lan1: Link is Up - 10Gbps/Full - flow control rx/tx
  417. [ 73.014888] switch: port 1(lan1) entered blocking state
  418. [ 73.020829] switch: port 1(lan1) entered forwarding state
  419. [ 73.037691] rtl83xx-switch switch@1b000000 lan5: configuring for phy/usxgmii link mode
  420. [ 73.046543] rtl93xx_phylink_mac_config SDS is 6
  421. [ 73.051677] Configuring SerDes 6 for USXGMII mode
  422. [ 73.056915] rtl9300_sds_rst 31
  423. [ 73.080308] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 6
  424. [ 73.146472] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  425. [ 73.153504] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  426. [ 73.161336] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  427. [ 73.168486] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  428. [ 73.176167] rtl9300_phy_enable_10g_1g set medium: 00000002
  429. [ 73.183292] rtl9300_phy_enable_10g_1g set medium after: 00000002
  430. [ 73.211964] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  431. [ 73.224019] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  432. [ 73.231989] rtl9300_force_sds_mode: SDS: 6, mode 30
  433. [ 73.237448] rtl9300_force_sds_mode: serdes 6 forcing to d
  434. [ 73.276432] rtl9300_force_sds_mode: serdes 6 forced to d DONE
  435. [ 73.287866] start_1.1.1 initial value for sds 6
  436. [ 73.349849] end_1.1.1 --
  437. [ 73.352671] start_1.1.2 Load DFE init. value
  438. [ 73.359436] end_1.1.2
  439. [ 73.361964] start_1.1.3 disable LEQ training,enable DFE clock
  440. [ 73.380369] end_1.1.3 --
  441. [ 73.383189] start_1.1.4 offset cali setting
  442. [ 73.389865] end_1.1.4
  443. [ 73.392395] start_1.1.5 LEQ and DFE setting
  444. [ 73.411048] end_1.1.5
  445. [ 73.422580] start_1.2.1 ForegroundOffsetCal_Manual
  446. [ 73.431924] end_1.2.1
  447. [ 73.442922] start_1.2.3 Foreground Calibration
  448. [ 73.461401] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  449. [ 73.470096] rtl9300_do_rx_calibration_2_3: end_1.2.3
  450. [ 73.475620] start_1.4.1
  451. [ 73.699254] end_1.4.1
  452. [ 73.701985] start_1.4.2
  453. [ 73.714526] vth_set_bin = 2
  454. [ 73.717288] vth_set_bin = 2
  455. [ 73.721394] Vth Maunal = 0
  456. [ 73.840309] Tap0 Sign : +
  457. [ 73.843331] tap0_coef_bin = 22
  458. [ 73.847260] tap0 manual = 0
  459. [ 73.856646] end_1.4.2
  460. [ 73.958528] 8021q: adding VLAN 0 to HW filter on device lan5
  461. [ 74.165772] Realtek RTL8261N mdio-bus:00: PHY 0 link state changed: UP -> DOWN
  462. [ 74.173942] Realtek RTL8261N mdio-bus:00: WARNING: This is PHY 0, check if PHY 24 also changes
  463. [ 74.194462] rtl83xx-switch switch@1b000000 lan1: Link is Down
  464. [ 74.202000] switch: port 1(lan1) entered disabled state
  465. [ 74.211647] switch: port 5(lan5) entered blocking state
  466. [ 74.217596] switch: port 5(lan5) entered disabled state
  467. [ 74.223471] rtl83xx-switch switch@1b000000 lan5: entered allmulticast mode
  468. [ 74.232123] rtl83xx-switch switch@1b000000 lan5: entered promiscuous mode
  469. [ 74.262952] rtl83xx-switch switch@1b000000 lan6: configuring for phy/usxgmii link mode
  470. [ 74.271861] rtl93xx_phylink_mac_config SDS is 7
  471. [ 74.276902] Configuring SerDes 7 for USXGMII mode
  472. [ 74.282182] rtl9300_sds_rst 31
  473. [ 74.305568] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 7
  474. [ 74.371754] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  475. [ 74.378801] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  476. [ 74.386579] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  477. [ 74.393703] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  478. [ 74.401418] rtl9300_phy_enable_10g_1g set medium: 00000002
  479. [ 74.408553] rtl9300_phy_enable_10g_1g set medium after: 00000002
  480. [ 74.437222] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  481. [ 74.449278] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  482. [ 74.457248] rtl9300_force_sds_mode: SDS: 7, mode 30
  483. [ 74.462671] rtl9300_force_sds_mode: serdes 7 forcing to d
  484. [ 74.501660] rtl9300_force_sds_mode: serdes 7 forced to d DONE
  485. [ 74.513093] start_1.1.1 initial value for sds 7
  486. [ 74.575088] end_1.1.1 --
  487. [ 74.577933] start_1.1.2 Load DFE init. value
  488. [ 74.584676] end_1.1.2
  489. [ 74.587258] start_1.1.3 disable LEQ training,enable DFE clock
  490. [ 74.605677] end_1.1.3 --
  491. [ 74.608521] start_1.1.4 offset cali setting
  492. [ 74.615168] end_1.1.4
  493. [ 74.617713] start_1.1.5 LEQ and DFE setting
  494. [ 74.636356] end_1.1.5
  495. [ 74.647904] start_1.2.1 ForegroundOffsetCal_Manual
  496. [ 74.657277] end_1.2.1
  497. [ 74.668295] start_1.2.3 Foreground Calibration
  498. [ 74.686757] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 30
  499. [ 74.695440] rtl9300_do_rx_calibration_2_3: end_1.2.3
  500. [ 74.701002] start_1.4.1
  501. [ 74.924607] end_1.4.1
  502. [ 74.927366] start_1.4.2
  503. [ 74.939901] vth_set_bin = 2
  504. [ 74.942625] vth_set_bin = 1
  505. [ 74.946718] Vth Maunal = 0
  506. [ 75.065628] Tap0 Sign : +
  507. [ 75.068669] tap0_coef_bin = 0
  508. [ 75.072583] tap0 manual = 0
  509. [ 75.081891] end_1.4.2
  510. [ 75.183409] 8021q: adding VLAN 0 to HW filter on device lan6
  511. [ 75.206806] switch: port 6(lan6) entered blocking state
  512. [ 75.212731] switch: port 6(lan6) entered disabled state
  513. [ 75.218689] rtl83xx-switch switch@1b000000 lan6: entered allmulticast mode
  514. [ 75.227241] rtl83xx-switch switch@1b000000 lan6: entered promiscuous mode
  515. [ 75.281908] rtl83xx-switch switch@1b000000 lan7: configuring for phy/usxgmii link mode
  516. [ 75.290815] rtl93xx_phylink_mac_config SDS is 8
  517. [ 75.295859] Configuring SerDes 8 for USXGMII mode
  518. [ 75.301138] rtl9300_sds_rst 31
  519. [ 75.324524] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 8
  520. [ 75.390717] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  521. [ 75.397763] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  522. [ 75.405545] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  523. [ 75.412669] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  524. [ 75.420384] rtl9300_phy_enable_10g_1g set medium: 00000002
  525. [ 75.427550] rtl9300_phy_enable_10g_1g set medium after: 00000002
  526. [ 75.456213] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  527. [ 75.468296] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  528. [ 75.476249] rtl9300_force_sds_mode: SDS: 8, mode 30
  529. [ 75.481710] rtl9300_force_sds_mode: serdes 8 forcing to d
  530. [ 75.520699] rtl9300_force_sds_mode: serdes 8 forced to d DONE
  531. [ 75.532115] start_1.1.1 initial value for sds 8
  532. [ 75.594109] end_1.1.1 --
  533. [ 75.596935] start_1.1.2 Load DFE init. value
  534. [ 75.603701] end_1.1.2
  535. [ 75.606227] start_1.1.3 disable LEQ training,enable DFE clock
  536. [ 75.624640] end_1.1.3 --
  537. [ 75.627484] start_1.1.4 offset cali setting
  538. [ 75.634132] end_1.1.4
  539. [ 75.636648] start_1.1.5 LEQ and DFE setting
  540. [ 75.655301] end_1.1.5
  541. [ 75.666829] start_1.2.1 ForegroundOffsetCal_Manual
  542. [ 75.676182] end_1.2.1
  543. [ 75.687199] start_1.2.3 Foreground Calibration
  544. [ 75.705686] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  545. [ 75.714381] rtl9300_do_rx_calibration_2_3: end_1.2.3
  546. [ 75.719941] start_1.4.1
  547. [ 75.943507] end_1.4.1
  548. [ 75.946230] start_1.4.2
  549. [ 75.958765] vth_set_bin = 3
  550. [ 75.961493] vth_set_bin = 3
  551. [ 75.965586] Vth Maunal = 0
  552. [ 76.084490] Tap0 Sign : +
  553. [ 76.087528] tap0_coef_bin = 17
  554. [ 76.091442] tap0 manual = 0
  555. [ 76.100847] end_1.4.2
  556. [ 76.202289] 8021q: adding VLAN 0 to HW filter on device lan7
  557. [ 76.224879] switch: port 7(lan7) entered blocking state
  558. [ 76.230800] switch: port 7(lan7) entered disabled state
  559. [ 76.236675] rtl83xx-switch switch@1b000000 lan7: entered allmulticast mode
  560. [ 76.245341] rtl83xx-switch switch@1b000000 lan7: entered promiscuous mode
  561. [ 76.268651] Realtek RTL8261N mdio-bus:00: PHY 0 link state changed: DOWN -> UP
  562. [ 76.276720] Realtek RTL8261N mdio-bus:00: WARNING: This is PHY 0, check if PHY 24 also changes
  563. [ 76.311064] Realtek RTL8261N mdio-bus:18: PHY 24 link state changed: DOWN -> UP
  564. [ 76.323020] rtl83xx-switch switch@1b000000 lan8: configuring for phy/usxgmii link mode
  565. [ 76.331941] rtl93xx_phylink_mac_config SDS is 9
  566. [ 76.337037] Configuring SerDes 9 for USXGMII mode
  567. [ 76.342270] rtl9300_sds_rst 31
  568. [ 76.365656] rtl9300_serdes_patch_mode_specific: Applying USXGMII patch for SDS 9
  569. [ 76.431837] rtl9300_phy_enable_10g_1g 1gbit phy: 00001140
  570. [ 76.438867] rtl9300_phy_enable_10g_1g 1gbit phy enabled: 00001140
  571. [ 76.446645] rtl9300_phy_enable_10g_1g 10gbit phy: 00002040
  572. [ 76.453768] rtl9300_phy_enable_10g_1g 10gbit phy after: 00002040
  573. [ 76.461494] rtl9300_phy_enable_10g_1g set medium: 00000002
  574. [ 76.468635] rtl9300_phy_enable_10g_1g set medium after: 00000002
  575. [ 76.497306] rtl9300_serdes_mac_link_config: registers before 00000000 00001403
  576. [ 76.509370] rtl9300_serdes_mac_link_config: registers after 00000000 00001403
  577. [ 76.517339] rtl9300_force_sds_mode: SDS: 9, mode 30
  578. [ 76.522763] rtl9300_force_sds_mode: serdes 9 forcing to d
  579. [ 76.561740] rtl9300_force_sds_mode: serdes 9 forced to d DONE
  580. [ 76.573166] start_1.1.1 initial value for sds 9
  581. [ 76.635171] end_1.1.1 --
  582. [ 76.638029] start_1.1.2 Load DFE init. value
  583. [ 76.644776] end_1.1.2
  584. [ 76.647323] start_1.1.3 disable LEQ training,enable DFE clock
  585. [ 76.665718] end_1.1.3 --
  586. [ 76.668560] start_1.1.4 offset cali setting
  587. [ 76.675206] end_1.1.4
  588. [ 76.677761] start_1.1.5 LEQ and DFE setting
  589. [ 76.696422] end_1.1.5
  590. [ 76.707961] start_1.2.1 ForegroundOffsetCal_Manual
  591. [ 76.717310] end_1.2.1
  592. [ 76.728330] start_1.2.3 Foreground Calibration
  593. [ 76.746799] rtl9300_do_rx_calibration_2_3: fgcal_gray: 63, fgcal_binary 32
  594. [ 76.755479] rtl9300_do_rx_calibration_2_3: end_1.2.3
  595. [ 76.761032] start_1.4.1
  596. [ 76.984602] end_1.4.1
  597. [ 76.987352] start_1.4.2
  598. [ 76.999887] vth_set_bin = 7
  599. [ 77.002611] vth_set_bin = 7
  600. [ 77.006704] Vth Maunal = 0
  601. [ 77.125619] Tap0 Sign : +
  602. [ 77.128664] tap0_coef_bin = 0
  603. [ 77.132578] tap0 manual = 0
  604. [ 77.141877] end_1.4.2
  605. [ 77.243466] 8021q: adding VLAN 0 to HW filter on device lan8
  606. [ 77.261030] rtl83xx-switch switch@1b000000 lan1: Link is Up - 10Gbps/Full - flow control rx/tx
  607. [ 77.270729] rtl83xx-switch switch@1b000000 lan5: Link is Up - 10Gbps/Full - flow control rx/tx
  608. [ 77.293418] switch: port 1(lan1) entered blocking state
  609. [ 77.299339] switch: port 1(lan1) entered forwarding state
  610. [ 77.305737] switch: port 5(lan5) entered blocking state
  611. [ 77.311653] switch: port 5(lan5) entered forwarding state
  612. [ 77.339350] switch: port 8(lan8) entered blocking state
  613. [ 77.345198] switch: port 8(lan8) entered disabled state
  614. [ 77.351173] rtl83xx-switch switch@1b000000 lan8: entered allmulticast mode
  615. [ 77.359838] rtl83xx-switch switch@1b000000 lan8: entered promiscuous mode
  616. [ 77.384142] rtl83xx_fib_event: FIB_RULE ADD/DEL for IPv6 not supported
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