diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index 2184b6c2c784..2e090717d6be 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -30,7 +30,6 @@
 #define PRG_ETH0_EXT_RMII_MODE     4

 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
-#define PRG_ETH0_CLK_M250_SEL_SHIFT    4
 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)

 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
@@ -166,8 +165,9 @@ static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
        return -ENOMEM;

    clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
-   clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
-   clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
+   clk_configs->m250_mux.shift = __ffs(PRG_ETH0_CLK_M250_SEL_MASK);
+   clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK >>
+                    clk_configs->m250_mux.shift;
    clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
                     ARRAY_SIZE(mux_parents), &clk_mux_ops,
                     &clk_configs->m250_mux.hw);