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- .equ delayCnt = 6
- .def tmp = r16
- .def flag = r17
- .def l = r18
- .def r = r19
- .cseg
- rjmp reset
- reset:
- ldi tmp, high(RAMEND)
- out SPH, tmp
- ldi tmp, low(RAMEND)
- out SPL, tmp
- ldi tmp, 0xff
- out DDRA, tmp
- out PORTA, tmp
- ldi flag, 1
- ldi l, (1 << 7)
- ldi r, (1 << 0)
- main:
- rcall delay
- rcall aktivnost
- rjmp main
- aktivnost:
- cpi flag, 1
- breq akt2
- ret
- akt2:
- in tmp, PORTA
- cpi tmp, 0x00
- breq end
- eor tmp, r
- eor tmp, l
- ror l
- rol r
- out PORTA, tmp
- end:
- ret
- delay:
- push r17
- push r18
- push r19
- clr r17
- clr r18
- ldi r19, delayCnt
- delay_loop:
- dec r17
- brne delay_loop
- dec r18
- brne delay_loop
- dec r19
- brne delay_loop
- pop r19
- pop r18
- pop r17
- ret
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