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Oct 23rd, 2019
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  1. .equ delayCnt = 6
  2.  
  3. .def tmp = r16
  4. .def flag = r17
  5. .def l = r18
  6. .def r = r19
  7.  
  8.  
  9. .cseg
  10. rjmp reset
  11.  
  12. reset:
  13. ldi tmp, high(RAMEND)
  14. out SPH, tmp
  15. ldi tmp, low(RAMEND)
  16. out SPL, tmp
  17.  
  18. ldi tmp, 0xff
  19. out DDRA, tmp
  20. out PORTA, tmp
  21.  
  22. ldi flag, 1
  23.  
  24. ldi l, (1 << 7)
  25. ldi r, (1 << 0)
  26.  
  27. main:
  28. rcall delay
  29. rcall aktivnost
  30. rjmp main
  31.  
  32.  
  33.  
  34. aktivnost:
  35. cpi flag, 1
  36. breq akt2
  37.  
  38. ret
  39.  
  40. akt2:
  41. in tmp, PORTA
  42. cpi tmp, 0x00
  43. breq end
  44. eor tmp, r
  45. eor tmp, l
  46. ror l
  47. rol r
  48. out PORTA, tmp
  49. end:
  50.  
  51.  
  52. ret
  53.  
  54.  
  55.  
  56. delay:
  57. push r17
  58. push r18
  59. push r19
  60.  
  61. clr r17
  62. clr r18
  63. ldi r19, delayCnt
  64.  
  65. delay_loop:
  66. dec r17
  67. brne delay_loop
  68. dec r18
  69. brne delay_loop
  70. dec r19
  71. brne delay_loop
  72.  
  73. pop r19
  74. pop r18
  75. pop r17
  76. ret
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