MultP.sv

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.05.2019 22:03:23
// Design Name:
// Module Name: Mp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Mp(
    input [15:0] a,
    input [15:0] b,
    input clk,
    input reset,
    output logic [15:0] result
    );

    logic sign1, sign2;
    logic [9:0] mant1, mant2;
    logic [4:0] exp1, exp2;

    assign sign1 = a[15];
    assign sign2 = b[15];
    assign mant1 = a[9:0];
    assign mant2 = b[9:0];
    assign exp1 = a[14:10];
    assign exp2 = b[14:10];

    logic isNan1, isZero1, isInf1;
    logic isNan2, isZero2, isInf2;

    assign isNan1 = (exp1==5'b11111) & (mant1!=10'b0);
    assign isNan2 = (exp2==5'b11111) & (mant2!=10'b0);
    assign isZero1 = (exp1==5'b00000) & (mant1==10'b0);
    assign isZero2 = (exp2==5'b00000) & (mant2==10'b0);
    assign isInf1 = (exp1==5'b11111) & (mant1==10'b0);
    assign isInf2 = (exp2==5'b11111) & (mant2==10'b0);

    logic[5:0] tmpExpSum;
    logic[5:0] convExpSum;
    logic[5:0] convExpSum2;
    assign tmpExpSum = exp1 + exp2;
    assign convExpSum = tmpExpSum[4:0] - 5'd15;
    assign convExpSum2 = tmpExpSum[4:0] - 5'd14;

    logic[21:0] multRes;

    //multInt Lul (.a({1'b1, mant1}), .b({1'b1, mant2}), .c(multRes), .clock(clk), .reset(reset));
    assign multRes = {1'b1, mant1}*{1'b1, mant2};

    always @(posedge clk) begin
        if (reset) begin
            result <= 16'b0111110000000001; //result - NaN
        end else
        if (isNan1 | isNan2)
             result <= 16'b0111110000000001; //result - NaN
        else
            if ((isInf1 & isZero2) | (isZero1 & isInf2))
                result <= 16'b0111110000000001; //result - NaN
        else
            if ((isInf1 & !isZero2) | (isInf2 & !isZero1))
                result <= 16'b0111110000000000; //result - Inf
        else
            if ((isZero1 & !isInf2) | (!isInf1 & isZero2))
                result <= 16'b0000000000000000; //result - Zero
        else begin
            if (multRes[21]==1'b0) begin
                if (tmpExpSum <= 6'd15)
                    result <= 16'b0000000000000000; //result - Zero
                else if (tmpExpSum >= 6'd46)
                    result <= 16'b0111110000000000; //result - Inf
                else begin
                    result <= {1'b0, convExpSum, multRes[19:10]};
                end
            end else begin
                if (tmpExpSum <= 6'd14)
                    result <= 16'b0000000000000000; //result - Zero
                else if (tmpExpSum >= 6'd45)
                    result <= 16'b0111110000000000; //result - Inf
                else begin
                    result <= {1'b0, convExpSum2, multRes[20:11]};
                end
            end
        end
    end

    always @(posedge clk) begin
        if ((sign1 & !sign2) | (!sign1 & sign2))
                result[15] <= 1;
        else
            result[15] <= 0;
        end

endmodule