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Oct 31st, 2018
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ARM 3.83 KB | None | 0 0
  1.     PRESERVE8
  2.     AREA MyCode,CODE,READONLY
  3.     EXPORT config
  4.     IMPORT my_fprint
  5.     EXPORT asm_pit1_irq
  6. PIT1_IRQHandler EQU asm_pit1_irq+1
  7.     EXPORT PIT1_IRQHandler      ;the vector table must contain odd addresses for the Cortex processor
  8. my_SIM_SCGC5 EQU    0x40048038      ;Address for SIM_SCGC5
  9. my_GPIOC_clken EQU  0x00000200      ;Clock gate enable for port A
  10. my_PORTA_PCR11 EQU  0x4004902C      ;PortA PCR 11 -> LED D7
  11. my_PORTA_PCR28 EQU  0x40049070
  12. my_PORTA_PCR29 EQU  0x40049074
  13. PORTA_PCR_VAL EQU   0x00000140
  14. my_GPIOA_PDOR EQU   0x400FF000
  15. GPIOA_PDOR_VAL EQU  0x30000800
  16. my_GPIOA_PCOR EQU   0x400FF008
  17. my_GPIOA_PSOR EQU   0x400FF004
  18. my_SIM_SCGC6 EQU    0x4004803C
  19. my_SCGC6_value EQU  0x00800000
  20.    
  21. my_PIT_MCR EQU      0x40037000
  22. my_PIT_LDVAL1 EQU   0x40037110
  23. my_LDVAL1_value EQU 0x05F5E0FF
  24. my_PIT_TFLG1 EQU    0x4003711C
  25. my_PIT_TCTRL1 EQU   0x40037118
  26.    
  27. my_NVIC_addr EQU    0xE000E108
  28. my_NVIC_value EQU   0x00000020
  29. config
  30. ;write 1 to bit {9} of SIM_SCGC5, enable Port A clock gate
  31.     LDR     r2, =my_SIM_SCGC5       ;0x40048038
  32.     LDR     r1, =my_GPIOC_clken     ;0x00000200
  33.     LDR     r3, [r2]
  34.     ORR     r3, r3, r1
  35.     STR     r3, [r2]                ;enable GPIO_PORTA
  36.    
  37.     LDR     r2, =my_PORTA_PCR11     ;0x4004902C address for orange LED
  38. ;For PortA PCR11, PCR28, PCR29 (3 LEDs):
  39. ;write 1 to bit {6}, DSE, high drive strength
  40. ;write 001 to bits {8-10}, MUX, alternative 1 GPIO
  41.     LDR     r1, =PORTA_PCR_VAL      ;0x00000140
  42.     STR     r1, [r2]                ;updates memory address to PTA28, yellow LED
  43.     ldr     r2, =my_PORTA_PCR28
  44.     STR     r1, [r2]                ;updates memory address to PTA29, green LED
  45.     ldr     r2, =my_PORTA_PCR29
  46.     STR     r1, [r2]
  47. ;turn off/reset LEDs:
  48. ;set PDOR PTA bits 11, 28, 29 to logic 1
  49.     LDR     r2, =my_GPIOA_PDOR      ;0x4000FF000
  50.     LDR     r1, =GPIOA_PDOR_VAL     ;0x300000800
  51.     STR     r1, [r2], #20           ;updates memory addres to GPIOA_PDDR
  52.    
  53. ;sets PDDR PTA fields 11, 28, 29 to general purpose output (1 to bits {11, 28, 29}
  54.     STR     r1, [r2]
  55.    
  56. ;Set PIT timer by writing 1 to bit {23}
  57.     LDR      r2,=my_SIM_SCGC6       ;0x4004803C
  58.     LDR      r1,=my_SCGC6_value     ;0x00800000
  59.     LDR      r0,[r2]
  60.     ORR      r0,r0,r1
  61.     STR      r0,[r2]                ;enable clock to PIT1
  62.    
  63. ;enable the PIT module (0 to bits {0-1} of the MCR)
  64.     LDR      r2,=my_PIT_MCR         ;0x40037000, memory address for PCR
  65.     MOV      r0,#0
  66.     STR      r0,[r2]                ;stores 0x0 into PCR
  67.    
  68. ;sets the timer to interrupt every 2s by writing LDVAL1
  69.     LDR      r2,=my_PIT_LDVAL1      ;0x40037110, memory address for PIT_LDVAL1
  70. ;want it to trigger every 2s
  71. ;2s/20ns - 1 =100e6 - 1 =0x05F5E0FF
  72.     LDR      r1,=my_LDVAL1_value    ;0x05F5E0FF
  73.     STR      r1,[r2]                ;load the count value to generate interrupt periodically
  74.  
  75. ;store 1 in bits {0,1} of TCTRL1, enable timer and interrupts
  76.     LDR      r2,=my_PIT_TCTRL1      ;0x40037118, memory address for PIT_TCTRL1
  77.     MOV      r0,#0x3
  78.     STR      r0,[r2]                ;set TIE and TEN bits
  79.  
  80. ;NVIC CONVIG
  81.     LDR      r2,=my_NVIC_value      ;0x00000020 sets IRQ 69
  82.     LDR      r1,=my_NVIC_addr       ;0xE000E108
  83.     STR      r2, [r1]
  84.    
  85. loop B loop
  86.    
  87. asm_pit1_irq
  88.     PUSH     {lr}                   ;store LR
  89.     LDR      r2,=my_PIT_TFLG1       ;Load memory address of TFLG1
  90.     MOV      r3,#0x01               ;1 to clear flag
  91.     STR      r3,[r2]                ;store to memory to clear flags
  92.     LDR      r2, =irqcounter        ;load memory address of irqcounter
  93.     LDRB     r3,[r2]                ;loads value from counter into r3
  94.     CMP      r3,#1                  ;if 1 turn off leds
  95.     BEQ      led_off
  96.     ADD      r3,#1                  ;increment counter
  97.     STRB     r3,[r2]                ;stores value of r3 into counter
  98.     B        led_on                 ;if 0 turn on leds
  99. led_off
  100.     MOV      r3,#0x00               ;reset counter (limit between 0 and 1)
  101.     str      r3, [r2]
  102.     LDR      r7, =my_GPIOA_PSOR     ;memory address of PSOR
  103.     LDR      r8, =GPIOA_PDOR_VAL    ;writes 1 at bits {11,28,29} to PSOR
  104.     str      r8, [r7]               ;turns off LEDs
  105.     POP      {pc}
  106. led_on     
  107.     LDR      r7, =my_GPIOA_PCOR     ;memory address of PCOR
  108.     LDR      r8, =GPIOA_PDOR_VAL    ;writes 1 at bits {11, 28, 29} to PCOR
  109.     STR      r8, [r7]               ;turns on LEDs
  110.     POP      {pc}                   ;restore program
  111.    
  112.    
  113.     ALIGN
  114.     AREA MyData, DATA, READWRITE
  115. irqcounter DCD 0x00
  116.        
  117. DCD
  118.  
  119.     END
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