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Código 1

fellpz Jul 17th, 2017 (edited) 54 Never
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  1. module prova(SW,in2,LEDR);
  2.  
  3. input [7:0] SW;
  4. input[2:0] in2;
  5. output[0:0] LEDR;
  6.  
  7. always@(SW or in2)
  8.  
  9. case(in2)
  10. 2'b000:LEDR=SW[0];
  11. 2'b001:LEDR=SW[1];
  12. 2'b010:LEDR=SW[2];
  13. 2'b011:LEDR=SW[3];
  14. 2'b100:LEDR=SW[4];
  15. 2'b101:LEDR=SW[5];
  16. 2'b110:LEDR=SW[6];
  17. 2'b111:LEDR=SW[7];
  18.  
  19. endcase
  20. endmodule
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