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- module prova(SW,in2,LEDR);
- input [7:0] SW;
- input[2:0] in2;
- output[0:0] LEDR;
- always@(SW or in2)
- case(in2)
- 2'b000:LEDR=SW[0];
- 2'b001:LEDR=SW[1];
- 2'b010:LEDR=SW[2];
- 2'b011:LEDR=SW[3];
- 2'b100:LEDR=SW[4];
- 2'b101:LEDR=SW[5];
- 2'b110:LEDR=SW[6];
- 2'b111:LEDR=SW[7];
- endcase
- endmodule
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