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  1. Index: /home/mbertens/src/coreboot/src/mainboard/Kconfig
  2. ===================================================================
  3. --- /home/mbertens/src/coreboot/src/mainboard/Kconfig (revision 5355)
  4. +++ /home/mbertens/src/coreboot/src/mainboard/Kconfig (working copy)
  5. @@ -96,6 +96,8 @@
  6. bool "VIA"
  7. config VENDOR_WINENT
  8. bool "Win Enterprises"
  9. +config VENDOR_NOKIA
  10. + bool "Nokia"
  11.  
  12. endchoice
  13.  
  14. @@ -359,6 +361,11 @@
  15. default "Win Enterprise"
  16. depends on VENDOR_WINENT
  17.  
  18. +config MAINBOARD_VENDOR
  19. + string
  20. + default "Nokia"
  21. + depends on VENDOR_NOKIA
  22. +
  23. source "src/mainboard/a-trend/Kconfig"
  24. source "src/mainboard/abit/Kconfig"
  25. source "src/mainboard/advantech/Kconfig"
  26. @@ -405,6 +412,7 @@
  27. source "src/mainboard/tyan/Kconfig"
  28. source "src/mainboard/via/Kconfig"
  29. source "src/mainboard/winent/Kconfig"
  30. +source "src/mainboard/nokia/Kconfig"
  31.  
  32. config BOARD_ROMSIZE_KB_128
  33. bool
  34. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/Kconfig
  35. ===================================================================
  36. --- /home/mbertens/src/coreboot/src/mainboard/nokia/Kconfig (revision 0)
  37. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/Kconfig (revision 0)
  38. @@ -0,0 +1,29 @@
  39. +##
  40. +## This file is part of the coreboot project.
  41. +##
  42. +## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  43. +##
  44. +## This program is free software; you can redistribute it and/or modify
  45. +## it under the terms of the GNU General Public License as published by
  46. +## the Free Software Foundation; either version 2 of the License, or
  47. +## (at your option) any later version.
  48. +##
  49. +## This program is distributed in the hope that it will be useful,
  50. +## but WITHOUT ANY WARRANTY; without even the implied warranty of
  51. +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  52. +## GNU General Public License for more details.
  53. +##
  54. +## You should have received a copy of the GNU General Public License
  55. +## along with this program; if not, write to the Free Software
  56. +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  57. +##
  58. +
  59. +choice
  60. + prompt "Mainboard model"
  61. + depends on VENDOR_NOKIA
  62. +
  63. +##source "src/mainboard/nokia/ip330/Kconfig"
  64. +source "src/mainboard/nokia/ip530/Kconfig"
  65. +
  66. +endchoice
  67. +
  68. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/Kconfig
  69. ===================================================================
  70. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/Kconfig (revision 0)
  71. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/Kconfig (revision 0)
  72. @@ -0,0 +1,54 @@
  73. +##
  74. +## This file is part of the coreboot project.
  75. +##
  76. +## Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  77. +##
  78. +## This program is free software; you can redistribute it and/or modify
  79. +## it under the terms of the GNU General Public License as published by
  80. +## the Free Software Foundation; either version 2 of the License, or
  81. +## (at your option) any later version.
  82. +##
  83. +## This program is distributed in the hope that it will be useful,
  84. +## but WITHOUT ANY WARRANTY; without even the implied warranty of
  85. +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  86. +## GNU General Public License for more details.
  87. +##
  88. +## You should have received a copy of the GNU General Public License
  89. +## along with this program; if not, write to the Free Software
  90. +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  91. +##
  92. +
  93. +config BOARD_NOKIA_IP530
  94. + bool "IP530"
  95. + select ARCH_X86
  96. +## select CPU_INTEL_SLOT_1
  97. + select CPU_INTEL_SOCKET_PGA370
  98. + select NORTHBRIDGE_INTEL_I440BX
  99. + select SOUTHBRIDGE_INTEL_I82371EB
  100. +## select SUPERIO_WINBOND_W83977TF
  101. + select SUPERIO_SMSC_SMSCSUPERIO
  102. + select ROMCC
  103. + select HAVE_PIRQ_TABLE
  104. + select UDELAY_TSC
  105. + select BOARD_ROMSIZE_KB_256
  106. +
  107. +config MAINBOARD_DIR
  108. + string
  109. + default nokia/ip530
  110. + depends on BOARD_NOKIA_IP530
  111. +
  112. +config MAINBOARD_PART_NUMBER
  113. + string
  114. + default "IP530"
  115. + depends on BOARD_NOKIA_IP530
  116. +
  117. +config HAVE_OPTION_TABLE
  118. + bool
  119. + default n
  120. + depends on BOARD_NOKIA_IP530
  121. +
  122. +config IRQ_SLOT_COUNT
  123. + int
  124. + default 6
  125. + depends on BOARD_NOKIA_IP530
  126. +
  127. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/romstage.c
  128. ===================================================================
  129. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/romstage.c (revision 0)
  130. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/romstage.c (revision 0)
  131. @@ -0,0 +1,71 @@
  132. +/*
  133. + * This file is part of the coreboot project.
  134. + *
  135. + * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  136. + *
  137. + * This program is free software; you can redistribute it and/or modify
  138. + * it under the terms of the GNU General Public License as published by
  139. + * the Free Software Foundation; either version 2 of the License, or
  140. + * (at your option) any later version.
  141. + *
  142. + * This program is distributed in the hope that it will be useful,
  143. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  144. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  145. + * GNU General Public License for more details.
  146. + *
  147. + * You should have received a copy of the GNU General Public License
  148. + * along with this program; if not, write to the Free Software
  149. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  150. + */
  151. +
  152. +#include <stdint.h>
  153. +#include <device/pci_def.h>
  154. +#include <arch/io.h>
  155. +#include <device/pnp_def.h>
  156. +#include <arch/romcc_io.h>
  157. +#include <arch/hlt.h>
  158. +#include <stdlib.h>
  159. +#include "pc80/serial.c"
  160. +#include "console/console.c"
  161. +#include "lib/ramtest.c"
  162. +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
  163. +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
  164. +#include "northbridge/intel/i440bx/raminit.h"
  165. +#include "lib/debug.c"
  166. +#include "pc80/udelay_io.c"
  167. +#include "lib/delay.c"
  168. +#include "cpu/x86/mtrr/earlymtrr.c"
  169. +#include "cpu/x86/bist.h"
  170. +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
  171. +
  172. +#define SERIAL_DEV PNP_DEV( 0x3f0, SMSCSUPERIO_SP1 )
  173. +
  174. +static inline int spd_read_byte(unsigned int device, unsigned int address)
  175. +{
  176. + return smbus_read_byte(device, address);
  177. +}
  178. +
  179. +#include "northbridge/intel/i440bx/raminit.c"
  180. +#include "northbridge/intel/i440bx/debug.c"
  181. +
  182. +static void main(unsigned long bist)
  183. +{
  184. + if (bist == 0)
  185. + early_mtrr_init();
  186. +
  187. + smscsuperio_enable_serial( SERIAL_DEV, CONFIG_TTYS0_BASE );
  188. + uart_init();
  189. + console_init();
  190. + report_bist_failure(bist);
  191. +
  192. + /* Enable access to the full ROM chip, needed very early by CBFS. */
  193. + i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
  194. +
  195. + enable_smbus();
  196. + /* dump_spd_registers(); */
  197. + sdram_set_registers();
  198. + sdram_set_spd_registers();
  199. + sdram_enable();
  200. + /* ram_check(0, 640 * 1024); */
  201. +}
  202. +
  203. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/devicetree.cb
  204. ===================================================================
  205. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/devicetree.cb (revision 0)
  206. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/devicetree.cb (revision 0)
  207. @@ -0,0 +1,62 @@
  208. +chip northbridge/intel/i440bx # Northbridge
  209. + device apic_cluster 0 on # APIC cluster
  210. + chip cpu/intel/socket_PGA370 # CPU
  211. + device apic 0 on end # APIC
  212. + end
  213. + end
  214. + device pci_domain 0 on # PCI domain
  215. + device pci 0.0 on end # Host bridge
  216. + device pci 1.0 on end # PCI/AGP bridge
  217. + chip southbridge/intel/i82371eb # Southbridge
  218. + device pci 4.0 on # ISA bridge
  219. + chip superio/smsc/smscsuperio # Super I/O FDC 37C878
  220. + device pnp 2e.0 on # Floppy
  221. + io 0x60 = 0x3f0
  222. + irq 0x70 = 6
  223. + drq 0x74 = 2
  224. + end
  225. + device pnp 2e.3 on # Parallel port
  226. + io 0x60 = 0x378
  227. + irq 0x70 = 7
  228. + drq 0x74 = 4
  229. + end
  230. + device pnp 2e.4 on # COM1
  231. + io 0x60 = 0x3f8
  232. + irq 0x70 = 4
  233. + end
  234. + device pnp 2e.5 on # COM2 / IR
  235. + io 0x60 = 0x2f8
  236. + irq 0x70 = 3
  237. + end
  238. + device pnp 2e.7 on # PS/2 keyboard / mouse
  239. + io 0x60 = 0x60
  240. + io 0x62 = 0x64
  241. + irq 0x70 = 1 # PS/2 keyboard interrupt
  242. + irq 0x72 = 12 # PS/2 mouse interrupt
  243. + end
  244. + device pnp 2e.9 on # Game port
  245. + io 0x60 = 0x201
  246. + end
  247. + device pnp 2e.a on # Power-management events (PME)
  248. + io 0x60 = 0x600
  249. + end
  250. + device pnp 2e.b on # MIDI port (MPU-401)
  251. + io 0x60 = 0x330
  252. + irq 0x70 = 5
  253. + end
  254. + end
  255. + end
  256. + device pci 4.1 on end # IDE
  257. + device pci 4.2 on end # USB
  258. + device pci 4.3 on end # ACPI
  259. + register "ide0_enable" = "1"
  260. + register "ide1_enable" = "1"
  261. + register "ide_legacy_enable" = "1"
  262. + # Enable UDMA/33 for higher speed if your IDE device(s) support it.
  263. + register "ide0_drive0_udma33_enable" = "0"
  264. + register "ide0_drive1_udma33_enable" = "0"
  265. + register "ide1_drive0_udma33_enable" = "0"
  266. + register "ide1_drive1_udma33_enable" = "0"
  267. + end
  268. + end
  269. +end
  270. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/asus_p2b_irq_tables.c
  271. ===================================================================
  272. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/asus_p2b_irq_tables.c (revision 0)
  273. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/asus_p2b_irq_tables.c (revision 0)
  274. @@ -0,0 +1,49 @@
  275. +/*
  276. + * This file is part of the coreboot project.
  277. + *
  278. + * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  279. + *
  280. + * This program is free software; you can redistribute it and/or modify
  281. + * it under the terms of the GNU General Public License as published by
  282. + * the Free Software Foundation; either version 2 of the License, or
  283. + * (at your option) any later version.
  284. + *
  285. + * This program is distributed in the hope that it will be useful,
  286. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  287. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  288. + * GNU General Public License for more details.
  289. + *
  290. + * You should have received a copy of the GNU General Public License
  291. + * along with this program; if not, write to the Free Software
  292. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  293. + */
  294. +
  295. +#include <arch/pirq_routing.h>
  296. +
  297. +const struct irq_routing_table intel_irq_routing_table = {
  298. + PIRQ_SIGNATURE,
  299. + PIRQ_VERSION,
  300. + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
  301. + 0x00, /* Interrupt router bus */
  302. + (0x04 << 3) | 0x0, /* Interrupt router device */
  303. + 0, /* IRQs devoted exclusively to PCI usage */
  304. + 0x8086, /* Vendor */
  305. + 0x122e, /* Device */
  306. + 0, /* Crap (miniport) */
  307. + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
  308. + 0x54, /* Checksum */
  309. + {
  310. + /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
  311. + {0x00,(0x0c<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
  312. + {0x00,(0x0b<<3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
  313. + {0x00,(0x0a<<3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
  314. + {0x00,(0x09<<3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
  315. + {0x00,(0x04<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
  316. + {0x00,(0x01<<3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
  317. + }
  318. +};
  319. +
  320. +unsigned long write_pirq_routing_table( unsigned long addr )
  321. +{
  322. + return ( copy_pirq_routing_table( addr ) );
  323. +}
  324. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/irq_tables.c
  325. ===================================================================
  326. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/irq_tables.c (revision 0)
  327. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/irq_tables.c (revision 0)
  328. @@ -0,0 +1,53 @@
  329. +/*
  330. + * This file is part of the coreboot project.
  331. + *
  332. + * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  333. + *
  334. + * This program is free software; you can redistribute it and/or modify
  335. + * it under the terms of the GNU General Public License as published by
  336. + * the Free Software Foundation; either version 2 of the License, or
  337. + * (at your option) any later version.
  338. + *
  339. + * This program is distributed in the hope that it will be useful,
  340. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  341. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  342. + * GNU General Public License for more details.
  343. + *
  344. + * You should have received a copy of the GNU General Public License
  345. + * along with this program; if not, write to the Free Software
  346. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  347. + */
  348. +
  349. +#include <arch/pirq_routing.h>
  350. +
  351. +const struct irq_routing_table intel_irq_routing_table = {
  352. + PIRQ_SIGNATURE, /* u32 signature */
  353. + PIRQ_VERSION, /* u16 version */
  354. + 32 + 16 * 6, /* Max. number of devices on the bus */
  355. + 0x00, /* Interrupt router bus */
  356. + (0x07 << 3) | 0x0, /* Interrupt router dev */
  357. + 0, /* IRQs devoted exclusively to PCI usage */
  358. + 0x8086, /* Vendor */
  359. + 0x122e, /* Device */
  360. + 0, /* Miniport */
  361. + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
  362. + 0x36, /* Checksum (has to be set to some value that
  363. + * would give 0 after the sum of all bytes
  364. + * for this structure (including checksum).
  365. + */
  366. + {
  367. + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
  368. + {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
  369. + {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
  370. + {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
  371. + {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
  372. + {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
  373. + {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
  374. + }
  375. +};
  376. +
  377. +unsigned long write_pirq_routing_table(unsigned long addr)
  378. +{
  379. + return copy_pirq_routing_table(addr);
  380. +}
  381. +
  382. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/chip.h
  383. ===================================================================
  384. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/chip.h (revision 0)
  385. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/chip.h (revision 0)
  386. @@ -0,0 +1,22 @@
  387. +/*
  388. + * This file is part of the coreboot project.
  389. + *
  390. + * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  391. + *
  392. + * This program is free software; you can redistribute it and/or modify
  393. + * it under the terms of the GNU General Public License as published by
  394. + * the Free Software Foundation; either version 2 of the License, or
  395. + * (at your option) any later version.
  396. + *
  397. + * This program is distributed in the hope that it will be useful,
  398. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  399. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  400. + * GNU General Public License for more details.
  401. + *
  402. + * You should have received a copy of the GNU General Public License
  403. + * along with this program; if not, write to the Free Software
  404. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  405. + */
  406. +
  407. +extern struct chip_operations mainboard_ops;
  408. +struct mainboard_config {};
  409. Index: /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/mainboard.c
  410. ===================================================================
  411. --- /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/mainboard.c (revision 0)
  412. +++ /home/mbertens/src/coreboot/src/mainboard/nokia/ip530/mainboard.c (revision 0)
  413. @@ -0,0 +1,26 @@
  414. +/*
  415. + * This file is part of the coreboot project.
  416. + *
  417. + * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
  418. + *
  419. + * This program is free software; you can redistribute it and/or modify
  420. + * it under the terms of the GNU General Public License as published by
  421. + * the Free Software Foundation; either version 2 of the License, or
  422. + * (at your option) any later version.
  423. + *
  424. + * This program is distributed in the hope that it will be useful,
  425. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  426. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  427. + * GNU General Public License for more details.
  428. + *
  429. + * You should have received a copy of the GNU General Public License
  430. + * along with this program; if not, write to the Free Software
  431. + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  432. + */
  433. +
  434. +#include <device/device.h>
  435. +#include "chip.h"
  436. +
  437. +struct chip_operations mainboard_ops = {
  438. + CHIP_NAME( "NOKIA IP530 Mainboard" )
  439. +};
  440. Index: /home/mbertens/src/coreboot/src/northbridge/intel/i440bx/raminit.h
  441. ===================================================================
  442. --- /home/mbertens/src/coreboot/src/northbridge/intel/i440bx/raminit.h (revision 5355)
  443. +++ /home/mbertens/src/coreboot/src/northbridge/intel/i440bx/raminit.h (working copy)
  444. @@ -22,9 +22,9 @@
  445. #define RAMINIT_H
  446.  
  447. /* The 440BX supports up to four (single- or double-sided) DIMMs. */
  448. -#define DIMM_SOCKETS 4
  449. +#define DIMM_SOCKETS 4
  450.  
  451. /* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */
  452. -#define DIMM_SPD_BASE 0x50
  453. +#define DIMM_SPD_BASE 0x50
  454.  
  455. #endif /* RAMINIT_H */
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