module uart(
input clk,
input rst,
input bcd0,
input bcd1,
output reg tx_out
);

reg [7:0]tx_shr;
reg [2:0]tx_cntr;
reg parity;
reg tx_enable;

always @(posedge clk)begin

    if(rst)begin
        tx_cntr <=0;
        tx_shr <=8'b00000000;
        tx_out <= 1;
    end

if (tx_enable) begin
         if(tx_cntr==0)begin //startbit
         tx_out <= 0;
         end
         tx_shr <= {tx_shr[3:0], bcd0}; //betoltom alsot
         tx_shr <= {tx_shr[7:4], bcd1}; //betoltom felsot
         tx_out <= tx_shr[tx_cntr] ;
         tx_cntr <= tx_cntr+1;

        if(tx_cntr == 7)begin

       parity =  (tx_shr[0] ^ tx_shr[1]) ^
               (tx_shr[2] ^ tx_shr[3]) ^
              (tx_shr[4] ^ tx_shr[5]) ^
             (tx_shr[6] ^ tx_shr[7]);

        end

            if (parity == 0)begin
                tx_out <= 0 ;
                end
            else
                tx_out <= 1 ;

        if (tx_cntr == 7) begin
        tx_out <= 1;
        tx_cntr <= 0;
        end

    end
end

endmodule