-- run for 10ms

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity clk_dividers_tb is
end;

architecture bench of clk_dividers_tb is

component ClockDivider is
    Port (
        inclk : in  STD_LOGIC;
        clk_480: out STD_LOGIC;
        clk_counter : out STD_LOGIC
    );
end component;

  signal inclk: STD_LOGIC;
  signal clk_480: STD_LOGIC;
  signal clk_counter: STD_LOGIC ;

  constant clock_period: time := 10 ns;
  signal stop_the_clock: boolean;

begin

  uut: ClockDivider port map ( inclk=> inclk,
                               clk_480 => clk_480,
                               clk_counter     => clk_counter );

  stimulus: process
  begin


    wait;
  end process;

  clocking: process
  begin
    while not stop_the_clock loop
      inclk <= '0', '1' after clock_period / 2;
      wait for clock_period;
    end loop;
    wait;
  end process;

end;