cordic unit

module atan_const
 (
  input [3:0] itr ,
  output reg [15:0] atan
  );

always @ (*)
  case (itr)
    4'h0 : atan=16'h3244 ;
    4'h1 : atan=16'h1dac ;
    4'h2 : atan=16'h0fae;
    4'h3 : atan=16'h07f5;
    4'h4 : atan=16'h03ff;
    4'h5 : atan=16'h0200;
    4'h6 : atan=16'h0100;
    4'h7 : atan=16'h0080;
    4'h8 : atan=16'h0040;
    4'h9 : atan=16'h0020;
    4'h10 : atan=16'h0010;
    4'h11 : atan=16'h0008;
    4'h12 : atan=16'h0004;
    4'h13 : atan=16'h0002;
    4'h14 : atan=16'h0001;
    default : atan=16'h0000 ;
  endcase
endmodule

module rgst #( parameter w = 8 )
(
  input clk,
  input rst_b,
  input [w-1:0] d,
  input ld,
  input clr,
  output reg [w-1:0] q
);

always @ (posedge clk, negedge rst_b)
  if (!rst_b)
    q <= 1'd0;
  else
    if (clr)
      q <= 1'd0;
  else
    if (ld)
      q <= d;
endmodule

module cntr #(parameter w = 8)
  (
  input clk,
  input rst_b,
  input c_up,
  input clr,
  output reg [w-1 :0] q
  );

always @ (posedge clk, negedge rst_b)
    if (!rst_b)
      q <= 1'd0;
    else
      if (clr)
       q <= 1'd0;
      else
        if(c_up)
          q <= q + 1'd1;
endmodule

module CU
  (
  input [3:0] itr,
  input bgn, clk, rst_b,
  output reg fin, init, ld
  );

  localparam WAIT = 2'd0;
  localparam EXEC = 2'd1;
  localparam END = 2'd2;

  reg [1:0] st, st_next;
  always @(*)
    case(st)
      WAIT: if(!bgn) st_next = WAIT;
            else if(bgn) st_next = EXEC;

      EXEC: if(itr == 15) st_next = END;
            else st_next = EXEC;

      END: st_next = WAIT;

    endcase

    always @(*)
      begin
        fin = 1'd0;
        init =  1'd0;
        ld = 1'd0;

        case(st)
          WAIT: if(bgn)
          begin
                  ld = 1;
                  init = 1;
           end
          EXEC: ld = 1;

          END: fin = 1;

        endcase
      end

    always @ (posedge clk, negedge rst_b)
    if (!rst_b)
      st <= WAIT;
    else
      st <= st_next;
endmodule


module cordic_unit
  (
    input [15:0] theta,
    input bgn, clk, rst_b,
    output[15:0] cos,
    output fin
  );

  wire [15:0] x_out, x_new, y_out, y_new, z_out, z_new, atan;
  wire ld, init;
  wire [3:0] itr;

  atan_const a0( .itr(itr), .atan(atan));
  CU a1( .clk(clk), .rst_b(rst_b), .bgn(bgn), .itr(itr), .fin(fin), .ld(ld), .init(init));

  cntr #(.w(4)) a2
  (
    .clk(clk),
    .c_up(ld),
    .clr(init),
    .q(itr),
    .rst_b(rst_b)

  );

  rgst #(.w(16)) a3
  (
    .clk(clk),
    .rst_b(rst_b),
    .clr(0),
    .ld(ld),
    .d(init) ? 16'h26dd : x_new,
    .q(x_out)
  );

  rgst #(.w(16)) a4
  (
    .clk(clk),
    .rst_b(rst_b),
    .clr(0),
    .ld(ld),
    .d(init) ? 16'h26dd : y_new,
    .q(y_out)
  );

  rgst #(.w(16)) a5
  (
    .clk(clk),
    .rst_b(rst_b),
    .clr(0),
    .ld(ld),
    .d(init) ? 16'h26dd : z_new,
    .q(z_out)
  );

  assign x_new = z_out[15] ? x_out + $unsigned($signed(y_out) >>> itr) : x_out - $unsigned($signed(y_out) >>> itr);
  assign y_new = z_out[15] ? y_out - $unsigned($signed(x_out) >>> itr) : y_out + $unsigned($signed(x_out) >>> itr);
  assign z_new = z_out[15] ?

endmodule