LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use std.textio.all; --


ENTITY TB_ds IS
port (
      saidat: out std_logic_vector(11 downto 0);
END TB_ds;

	architecture comportamento of TB_ds is

component ds is
port (
		entrada: in std_logic_vector(7 downto 0);
		clock: in std_logic;
		saidaindex: out std_logic_vector(3 downto 0);
		saida: out std_logic_vector(11 downto 0)
		);
end component;
   --funcao
   function str_to_stdvec(inp: string) return std_logic_vector is
		variable temp: std_logic_vector(inp'range);
	begin
		for i in inp'range loop
			if (inp(i) = '1') then
				temp(i) := '1';
			elsif (inp(i) = '0') then
				temp(i) := '0';
			end if;
		end loop;
		return temp;
	end function str_to_stdvec;

   --funcao
	function stdvec_to_str(inp: std_logic_vector) return string is
		variable temp: string(inp'left+1 downto 1);
	begin
		for i in inp'reverse_range loop
			if (inp(i) = '1') then
				temp(i+1) := '1';
			elsif (inp(i) = '0') then
				temp(i+1) := '0';
			end if;
		end loop;
		return temp;
	end function stdvec_to_str;

   --entradas e saídas
	signal flag: std_logic := '0';
	signal flag_end, flag_never: std_logic := '0';
	signal flag_end_file: std_logic := '0';
	signal clk: std_logic := '0';
	signal reset: std_logic := '1';
  signal saidaindex: std_logic_vector(3 downto 0);
	signal entrada_ref: std_logic_vector(7 downto 0);
	--signal entrada_blk: REG_ROWS;
	--signal saida: REG_ROWS;

signal sig_start_sad_manager: std_logic := '0';
signal	sig_start_reference_manager : std_logic := '0';
signal start_fill, start_shifts: std_logic := '0';
	signal sig_vector_x: std_logic_vector(4 DOWNTO 0);
	signal sig_vector_y: std_logic_vector(4 DOWNTO 0);

	--col_left: out REG_COLS;
	--col_right: out REG_COLS;

	signal sig_result: std_logic_vector(11 DOWNTO 0); -- resultado do SAD entre o BRB (banco de registradores de bloco)e o BRR (banco de registradores de referencia)

   file infile, outfile: text;

begin
  clockgen :PROCESS
	BEGIN
		clk <= '1', '0' AFTER 20 ns;
		WAIT FOR 40 ns;
	END PROCESS;

  resetgen :PROCESS
	BEGIN
		wait until (clk'event AND clk = '0');
		reset <= '1';
		wait until (clk'event AND clk = '0');
		reset <= '0';
		wait until (clk'event AND clk = '0' and flag_never = '1');
	END PROCESS;

	startFillGen :PROCESS
	BEGIN
		wait until (clk'event AND clk = '0');--0 -- reset
		wait until (clk'event AND clk = '0');--0 -- reset
		start_fill <= '1';
		wait until (clk'event AND clk = '0');--
		start_fill <= '0';
		wait until (clk'event AND clk = '0' and flag_end = '1');
	END PROCESS;

	startShiftsGen :PROCESS
	BEGIN
		wait until (start_fill = '1');
		wait until (clk'event AND clk = '0');--1
		wait until (clk'event AND clk = '0');--2
		wait until (clk'event AND clk = '0');--3
		wait until (clk'event AND clk = '0');--4
		wait until (clk'event AND clk = '0');--5
		wait until (clk'event AND clk = '0');--6
		wait until (clk'event AND clk = '0');--7
		wait until (clk'event AND clk = '0');--8
		wait until (clk'event AND clk = '0');--inserido
		--wait until (clk'event AND clk = '0');--inserido

		start_shifts <= '1';
		wait until (clk'event AND clk = '0');--2
		start_shifts <= '0';
		wait until (clk'event AND clk = '0' and flag_end = '1');

	END PROCESS;

 start_sad_manager:PROCESS
	BEGIN
		wait until (start_shifts = '1');
		sig_start_sad_manager <= '1';
		wait until (clk'event and clk='0');
		sig_start_sad_manager <= '0';
		wait until (clk'event AND clk = '0' and flag_end = '1');
	END PROCESS;


  estimulos_entrada: process
      variable i, j, k: integer;
      variable linha: line;
      variable linhaStr: string(8 downto 1);
      variable linhaVec: std_logic_vector(7 downto 0);
   begin

		FILE_OPEN(infile, "entrada.txt", READ_MODE);
		wait until (clk'event and clk='0' and reset='0');
		while not endfile(infile) loop

			--lendo os valores do bloco
			--i:=0;
			--while(i<8) loop
			--	j:=0;
			--	while (j<8) loop
			--		readline(infile, linha);
			--		read(linha, linhaStr);
			--		entrada_blk(i)(j) <= str_to_stdvec (linhaStr);
			--		j := j+1;
			--	end loop;
			--	i := i+1;
			--end loop;

			--Lendo a primeira posicao da area de pesquisa
		i := 0;
			while(i<8) loop
				j := 0;
				while (j<8) loop
					readline(infile, linha);
					read(linha, linhaStr);
					entrada_ref <= str_to_stdvec(linhaStr);
				  j:= j+1;
				end loop;
				i:= i+1;
				wait until (clk'event and clk = '0');
		end loop;

	 wait until (clk'event and clk = '0' and start_shifts = '1');

			--lendo os dados de entrada para os proximos casamentos (624 casamentos)
			--k := 0;
			--while (k<624) loop --624
				--i:= 0;
				--while(i<8) loop
				--	readline(infile, linha);
				--	read(linha, linhaStr);
				--	entrada_ref(i) <= str_to_stdvec (linhaStr);
				--	i:= i+1;
				--end loop;
				--wait until (clk'event and clk='0');
			--k := k+1;
			--end loop;

			flag <= '1';
			wait until (clk'event and clk='0');
			flag <= '0';

		end loop;
		file_close(infile);
		flag_end_file <= '1';
		wait until (flag_never = '1');
		end process;

		estimulos_saida: process
		variable i,j: integer;
		variable outData: string(12 downto 1);
		variable linha: line;

		begin
		FILE_OPEN(outfile,"saida.txt", WRITE_MODE);
		i:= 0;

		while (flag_end_file /= '1') loop

			wait until (sig_start_sad_manager = '1');
			wait until (clk'event and clk='0'); --1
			wait until (clk'event and clk='0'); --2
			wait until (clk'event and clk='0'); --3
			wait until (clk'event and clk='0'); --4
			wait until (clk'event and clk='0'); --5
			wait until (clk'event and clk='0'); --6
			wait until (clk'event and clk='0'); --7
			wait until (clk'event and clk='0'); --8

			while (flag /= '1') loop
				outData := stdvec_to_str(sig_result);
				write(linha,outData);
				writeline(outfile,linha);
				wait until (clk'event and clk='0');
			end loop;

			i := 0;
			while (i < 7) loop
				outData := stdvec_to_str(sig_result);
				write(linha,outData);
				writeline(outfile,linha);
				i := i + 1;
				wait until (clk'event and clk='0');
			end loop;

			flag_end <= '1';
			wait until (clk'event and clk='0');
			flag_end <= '0';

		end loop;

		file_close(outfile);
	end process;
	saidat<= sig_result;
	diamond: ds
	port map (entrada_ref,clk,saidaindex,sig_result);
end comportamento;