`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   21:40:13 11/05/2018
// Design Name:   counter
// Module Name:   /home/ise/Desktop/counter/tb.v
// Project Name:  counter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module tb;

    // Inputs
    reg rst;
    reg clk;
    reg load;
    reg [5:0] initVal;

    // Outputs
    wire [5:0] cout;

    // Instantiate the Unit Under Test (UUT)
    counter uut (
        .rst(rst),
        .clk(clk),
        .load(load),
        .initVal(initVal),
        .cout(cout)
    );

    initial begin
        // Initialize Inputs
        rst = 0;
        clk = 0;
        #10;
        rst = 1;

        // Wait 100 ns for global reset to finish
        #100;
        rst = 0;
      forever #20 clk = ~clk;
        // Add stimulus here

    end

    initial begin
        initVal = 20;
        forever #100 initVal = {$random} % 1000;
    end

    initial begin
        load = 1;
        forever #100 load = {$random} % 2;
    end

endmodule