LE_C2 help

/Do not change the port declarations
module function_unit (result, VCNZ, OpA, OpB, FS);
input [3:0] FS;
input [7:0] OpA, OpB;
output [7:0] result;
output [3:0] VCNZ;

wire FW1, CW1;
wire [7:0] resultb1;
wire [7:0] resultb2;
wire [4:0] b1V1, b2V1;

block1 BX(result, arithAselect, arithBselect, arithcarryA);
arith_circuit AC(result, FW1, OpA, OpB, FS);
arithmux AX(result, Fw1, LW1, FS);



arith_circuit ac(resultsb1, b1v1, OpA, OpB, FS);
block1 bc(resultsb2, b2v1, OpA, OpB, FS);

   assign result = (FS [3] == 1'b0) ? resultb1:
	                  (FS [1] == 1'b1) ? resultb2: 8'bxxxxxxxx;
	assign VCNZ = (FS [1] == 1'b0) ? b1v1:
	                  (FS[1] == 1'b1) ? b2v1: 4'bxxxx;

endmodule

//Replace these assign statement, Vcnz, OpA, OpB, FS);


//muxes
module arithmux (result4, OpA, OpB, switches);
input [2:0] switches;
input [7:0] OpA, OpB;
output [7:0] result4;
wire [7:0] muxA, muxB;
wire [1:0] Cin, Ra, Rb;


assign muxA=(Ra ==3'b100) ? OpA : //A
				(Ra ==3'b011) ? ~OpA : //~A
				(Ra==3'b101) ? 8'b00000000 : //x
				(Ra==3'b010) ? 8'b00000000 : //X
				8'bxxxxxxxx;

assign muxB=(Rb==3'b001) ? OpB : //B
				(Rb ==3'b110) ? ~OpB : //~B
				(Rb ==3'b000) ? 8'b00000000 : //x
				(Rb ==3'b111) ? 8'b00000000 : //x
				8'bxxxxxxxx;
endmodule

///////////////////////////////////////////////////////////////////////////////

//set 1
module arith_circuit (result2,cout1, A, B, select);
input [2:0] select;
input [7:0] A, B;
output [7:0] result2;
wire [7:0] Awire, Bwire, Cwire;
wire [8:1] carry1;
output cout1;

		arithAselect Ain (A, select, Awire);
		arithBselect Bin (B, select, Bwire);
		arithcarryA Cin (select, Cwire);

		full_adders F0 (result2 [0], carry1 [1], A[0],B[0], Cwire);
		full_adders F1 (result2 [1], carry1 [2], A[1],B[1],carry1 [1]);
		full_adders F2 (result2 [2], carry1 [3], A[2],B[2],carry1 [2]);
		full_adders F3 (result2 [3], carry1 [4], A[3],B[3],carry1 [3]);
		full_adders F4 (result2 [4], carry1 [5], A[4],B[4],carry1 [4]);
		full_adders F5 (result2 [5], carry1 [6], A[5],B[5],carry1 [5]);
		full_adders F6 (result2 [6], carry1 [7], A[6],B[6],carry1 [6]);
		full_adders F7 (result2 [7], carry1 [8], A[7],B[7],carry1 [7]);

assign cout1 =carry1[8];
endmodule
//calling  function

module full_adders(sum,cout, a, b, cin);
input a, b, cin;
output sum, cout;

assign sum = a^b^cin,
		cout =	a&b | (cin&(a^b));
endmodule
////////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////////

// block 1

module block1 (result, OpA, OpB, switches);
input [2:0] switches;
input [7:0] OpA, OpB;
output [7:0] result;
wire [7:0] muxB1;

// Replace this assign statement with your Verilog code.
// The operation of the arithmetic circuit is defined in the  specification.
assign muxB1  =(switches[2:0]==3'b000)?{4'b0000, OpB[3:0]}:
					(switches[2:0]==3'b001)?~OpA:
					(switches[2:0]==3'b010)?8'b00000000:
					(switches[2:0]==3'b100)?~OpB:
					(switches[2:0]==3'b110)?OpA|OpB:
					(switches[2:0]==3'b101)?~(OpA|OpB):
					(switches[2:0]==3'b011)?~(OpA&OpB):
					(switches[2:0]==3'b111)?{OpB[4:0],3'b000}:	8'b00000000;
assign result= muxB1;
endmodule