module controlUnit(regWrite, pcSrc, regDst, aluOp, aluSrc, branch, memWrite, memRead, memtoReg, address, funct, immediate, rs, rt, rd, shamt, type, opcode, zeroFlag, instruction, clk);
    output reg regWrite, aluSrc, branch, memWrite, memRead, memtoReg, regDst, pcSrc = 0;
    output reg [2:0] aluOp;
    input zeroFlag, clk;
    input [31:0] instruction;
    output reg [25:0] address = 0;
    output reg [5:0] funct = 0;
    output reg [15:0] immediate  = 0;
    output reg [4:0] rs = 0;
    output reg [4:0] rt = 0;
    output reg [4:0] rd = 0;
    output reg [4:0] shamt = 0;
    output reg [2:0] type = 0;
    output [5:0] opcode;
    assign opcode = instruction[31:26];

    always@(posedge clk)
    begin
        if(instruction[31:26]==0)
        begin
            address = 0;
            rs = instruction[25:21];
            rt = instruction[20:16];
            rd = instruction[15:11];
            shamt = instruction[10:6];
            funct = instruction[5:0];
        end
    else
        begin
            rs = instruction[25:21];
            rt = instruction[20:16];
            address = instruction[15:0];
        end
    end

    always@(instruction)
    begin
    if (opcode == 0)
        begin
            branch = 0 ;
            pcSrc = 0 ;
            regWrite = 1 ;
            regDst = 1 ;
            aluSrc = 0 ;
            memRead = 0 ;
            memWrite = 0 ;
            memtoReg=0;
            if(funct == 6'h24)
                aluOp = 3'b010;
            else if (funct == 6'h25)
                aluOp = 3'b100;
            else if (funct == 6'h20)
                aluOp = 3'b000;
            else if (funct == 6'h22)
                aluOp = 3'b001;
            else if (funct == 6'h2A)
                aluOp = 3'b101;
            else if (funct == 6'h2)
                aluOp = 3'b110;
            else if (funct == 6'h0)
                aluOp = 3'b111;
            end
        else if (opcode == 6'h8) //ADI
        begin
            branch = 0 ;
            pcSrc = 1 ;
            regWrite = 1 ;
            regDst = 0 ;
            aluSrc = 1 ;
            aluOp = 3'b000;
            memRead = 0 ;
            memWrite = 0 ;
            memtoReg= 0;
        end
        else if (opcode == 6'hD) //ORI
        begin
            branch = 0 ;
            pcSrc = 1 ;
            regWrite = 1 ;
            regDst = 0 ;
            aluSrc = 1 ;
            aluOp = 3'b100;
            memRead = 0 ;
            memWrite = 0 ;
            memtoReg= 0;
        end
        else if (opcode == 6'hC) //ANDI
        begin
            branch = 0 ;
            pcSrc = 1 ;
            regWrite = 1 ;
            regDst = 0 ;
            aluSrc = 1 ;
            aluOp = 3'b010;
            memRead = 0 ;
            memWrite = 0 ;
            memtoReg= 0;
        end
        else if(opcode == 6'h23) //LW
        begin
            branch = 0 ;
            pcSrc = 0 ;
            regWrite = 1 ;
            regDst = 0 ;
            aluSrc = 1 ;
            aluOp = 3'bxxx;
            memRead = 1 ;
            memWrite = 0 ;
            memtoReg= 1;
        end
        else if (opcode == 6'h2B) //SW
        begin
            branch = 0 ;
            pcSrc = 0 ;
            regWrite = 0 ;
            regDst = 1'bx ;
            aluSrc = 1 ;
            aluOp = 3'bxxx;
            memRead = 0 ;
            memWrite = 1 ;
            memtoReg= 1'bx;
        end
        else if (opcode == 6'h4) //BEQ
        begin
            branch = 1 ;
            pcSrc = 1 ;
            regWrite = 0 ;
            regDst = 1'bx ;
            aluSrc = 0 ;
            aluOp = 3'bxxx;
            memRead = 0 ;
            memWrite = 0 ;
            memtoReg= 1'bx;
        end
        else if(opcode ==6'h5) //BNE
        begin
            branch = 1 ;
            pcSrc = 1 ;
            regWrite = 0 ;
            regDst = 1'bx ;
            aluSrc = 0 ;
            aluOp = 3'bxxx;
            memRead = 0 ;
            memWrite = 1 ;
            memtoReg= 1'bx;
        end
    end
endmodule

module mux_2x1_32b(result,i1,i2,select);
    output [31:0] result ;
    input [31:0] i1;
    input [31:0] i2;
    input select ;
    assign result= (select)?i1:i2;
endmodule

module mux_2x1_5b(result,i1,i2,select);
    output [4:0] result;
    input [4:0] i1,i2;
    input select ;
    assign result = (select)?i1:i2;
endmodule

module ALU(out, zeroflag, input1, input2, aluOperation, clk);
    input [31:0] input1, input2;
    input [2:0] aluOperation;
    input clk;
    output reg [31:0] out;
    output reg zeroflag = 1'b0;

    always@(posedge clk)
    begin
        if(input1 == input2)
            zeroflag = 1;
        else
            zeroflag = 0;
    end

    always@(posedge clk)
    begin
    case(aluOperation)
        0: out = input1 + input2;
        1: out = input1 - input2;
        2: out = input1 & input2;
        3: out = input1 << input2;
        4: out = input1 | input2;
        5: out = input1 < input2;
        6: out = input1 >> input2 ;
        default : out = 31'b0;
    endcase
    end
endmodule

module id_stage(pcSrc, memToReg, regWrite, memWrite, branch, memRead, aluSrc, aluOp, regDst, pc_out, read_data_1, read_data_2, sign_extended_bit, rs, rt, rd, pc_in, instruction,writeData ,clk);
     output pcSrc, memToReg, memRead, memWrite, branch, zero, regWrite;
     output aluSrc, regDst;
     output[2:0] aluOp;
     output [31:0] pc_out;
     output [31:0] read_data_1, read_data_2, sign_extended_bit ;
     input [31:0] pc_in, instruction, writeData;
     input clk;
     wire [25:0] address;
     wire [5:0] funct;
     wire [15:0] immediate;
     output wire [4:0] rs, rt, rd;
     wire [4:0] shamt;
     wire [2:0] type;
     wire [5:0] opcode;

    assign opcode = instruction[31:26];

    controlUnit ctrlunit(regWrite, pcSrc, regDst, aluOp, aluSrc, branch, memWrite, memRead, memtoReg, address, funct, immediate, rs, rt, rd, shamt, type, opcode, zero, instruction, clk);
    assign sign_extended_bit = $signed(immediate);
    rf rf(read_data_1, read_data_2, clk, rs, rt, rd, writeData, regWrite);
endmodule

module rf(read_data_1, read_data_2, clk, read_reg_1, read_reg_2, write_reg, write_data, regWrite);
    output reg [31:0] read_data_1, read_data_2;
    input clk;
    input [4:0] read_reg_1, read_reg_2, write_reg;
    input [31:0] write_data;
    input regWrite;
    reg [31:0] registers[31:0];

    always@(read_reg_1, read_reg_2)
    begin
        read_data_1 <= (read_reg_1==0)? 32'b0 : registers[read_reg_1];
        read_data_2 <= (read_reg_2==0)? 32'b0 : registers[read_reg_2];
    end

    always @(posedge clk)
    begin
        if(regWrite)
        begin
            registers[write_reg] <= write_data;
        end
    end
endmodule

module instruction_memory(instruction, read_address);
    parameter N = 1;
    output [31:0] instruction;
    input [31:0] read_address;
    reg [31:0] memory [0:0];
    initial
    begin
        $readmemb("instructions.txt", memory);
    end
    assign instruction = memory[read_address];
endmodule

module if_stage(pc, instruction, pcSrc, offset, clk);
    output reg [31:0] pc = 32'b0;
    output [31:0] instruction;

    input pcSrc, clk;
    input [31:0] offset;

    always@(posedge clk)
        begin
            pc = (pcSrc)?(offset):(pc+1);
        end
    instruction_memory mem_(instruction, pc);
endmodule

module shift_add(result, in1, in2);
    output reg [31:0] result;
    input [31:0] in1, in2;
    reg input2;

    always@(in1, in2)
    begin
        input2 = in2 << 2;
        result = in1 + input2;
    end
endmodule

module ex_stage(new_pc, zero, aluResult, muxout, aluSrc, aluOp, regDst, pc, rs_in, rt_in, sign_extended_bit, rt, rd, clk);
    output zero;
    output [31:0] new_pc;
    output [31:0] aluResult;
    output [4:0] muxout;
    input [31:0] pc;
    input [2:0] aluOp;
    input [31:0] rs_in, rt_in, sign_extended_bit ;
    input clk, aluSrc, regDst;
    input [4:0] rt, rd;
    shift_add shiftadd(new_pc, pc, sign_extended_bit); //new_pc is the output of the adder
    wire [31:0] selected_operand ;
    mux_2x1_32b mux32(selected_operand, rt_in, sign_extended_bit, aluSrc); // selected_operand  is the value ouput of the mux
    ALU alu(aluResult, zero, rs_in, selected_operand, aluOp, clk);
    mux_2x1_5b mux5(muxout, rt, rd, regDst); //2x1MuxOut is the output of the lower mux
endmodule

module main;
    reg clk = 1'b0;
    wire pcSrc = 1'b0;
    wire [31:0] pc;
    wire [31:0] instruction;
    wire [31:0] offset;
    wire regWrite, aluSrc, branch, memWrite, memRead, memtoReg, regDst;
    wire [25:0] address;
    wire [5:0] funct;
    wire [15:0] immediate;
    wire [4:0] rs;
    wire [4:0] rt;
    wire [4:0] rd;
    wire [4:0] shamt;
    wire [2:0] type;
    wire [2:0] aluOp;
    wire [31:0] pc_out, pc_in, read_data_1, read_data_2, sign_extended_bit, writeData;
    wire [4:0] Rt_field, Rd_field;
    wire [4:0] muxout;
    wire [31:0] aluResult;


    if_stage if_stage(pc, instruction, pcSrc, offset, clk);
    id_stage id_stage(pcSrc, memToReg, regWrite, memWrite, branch, memRead, aluSrc, aluOp, regDst, pc_out, read_data_1, read_data_2, sign_extended_bit, rs, rt, rd, pc, instruction, writeData,clk);
    ex_stage ex_stage(offset, zero, aluResult, muxout, aluSrc, aluOp, regDst, pc, read_data_1, read_data_2, sign_extended_bit, rt, rd, clk);

    initial #300 $finish;
    initial
        begin
            repeat (1)
            #10 clk = ~clk;
        end

    initial
    begin
        $monitor("Clk:%d, PC:%d, I:%d, PCSrc: %d, memToReg: %d, regWrite: %d, memWrite: %d, branch: %d, memRead: %d, aluSrc: %d, aluOp: %d, regDst: %d, pc_out: %d, read_data_1: %d, read_data_2: %d, seb: %d, rs: %d, rt: %d, rd: %d, writedata: %d, offset: %d, zero: %d, result: %d, muxout: %d, aluSrc: %d",
        clk, pc, instruction, pcSrc, memToReg, regWrite, memWrite, branch, memRead, aluSrc, aluOp, regDst, pc_out, read_data_1, read_data_2, sign_extended_bit, rs, rt, rd, writeData, offset, zero, aluResult, muxout, aluSrc);
    end

endmodule