[ericb@ace fw]$ ls
bin2hex.py  console.c   lnk-app.lds    spi.c       usb_desc_data.h
boot.elf    console.h   lnk-boot.lds   spi.h       usb_ep0.c
boot.hex    firmware.c  Makefile       start.S     usb.h
boot.S      led.c       mini-printf.c  usb.c       usb_priv.h
config.h    led.h       mini-printf.h  usb_desc.c
[ericb@ace fw]$ git log
commit c138c61984b5e0098591d8b2b40300831529770e (HEAD -> usb, origin/master, origin/HEAD, master)
Author: Sylvain Munaut <tnt@246tNt.com>
Date:   Sun Dec 29 13:09:01 2019 +0100

    cores/e1: Add option to use an external LIU instead of the iCE40 as PHY

    Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

commit f147c005dbd20b552e0158b7f56ae760084589a5
Author: Sylvain Munaut <tnt@246tNt.com>
Date:   Wed Jun 12 20:19:16 2019 +0200

    cores/e1: Minor synth improvement on CRC core

    Writing the condition like this prevents yosys from creating a Set/Reset
    FF which can improve packing (avoid a different control set)

    Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

commit 21300d8cfe7f1efa804ed18f3fe1646446541af2
Author: Sylvain Munaut <tnt@246tNt.com>
Date:   Sat May 11 07:27:18 2019 +0200

    cores/e1: Fix CRC error marker in BD out fifo

    bd_done isn't aligned with df_valid so can't use the latter as the
    clock enable

    Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

<and lots more of this...>