ARTIQ EFC patch

diff --git a/artiq/gateware/targets/efc.py b/artiq/gateware/targets/efc.py
index 385e05479..e3ac2c325 100644
--- a/artiq/gateware/targets/efc.py
+++ b/artiq/gateware/targets/efc.py
@@ -29,14 +29,15 @@ class Satellite(BaseSoC, AMPSoC):
     }
     mem_map.update(BaseSoC.mem_map)

-    def __init__(self, gateware_identifier_str=None, hw_rev="v1.1", **kwargs):
+    def __init__(self, gateware_identifier_str=None, hw_rev="v1.1", drtio_100mhz=False, **kwargs):
+        clk_freq = 100e6 if drtio_100mhz else 125e6
         BaseSoC.__init__(self,
                  cpu_type="vexriscv",
                  hw_rev=hw_rev,
                  cpu_bus_width=64,
                  sdram_controller_type="minicon",
                  l2_size=128*1024,
-                 clk_freq=125e6,
+                 clk_freq=clk_freq,
                  **kwargs)
         AMPSoC.__init__(self)
         add_identifier(self, gateware_identifier_str=gateware_identifier_str)
@@ -107,7 +108,7 @@ class Satellite(BaseSoC, AMPSoC):
         fix_serdes_timing_path(platform)

         self.config["DRTIO_ROLE"] = "satellite"
-        self.config["RTIO_FREQUENCY"] = "125.0"
+        self.config["RTIO_FREQUENCY"] = "100.0" if drtio_100mhz else "125.0"

         shuttler_io = [
             ('dac_spi', 0,
@@ -251,11 +252,14 @@ def main():
                         help="Hardware revision")
     parser.add_argument("--gateware-identifier-str", default=None,
                         help="Override ROM identifier")
+    parser.add_argument("--drtio100mhz", action="store_true", default=False,
+                        help="DRTIO systems only - use 100MHz RTIO clock")
     args = parser.parse_args()

     argdict = dict()
     argdict["gateware_identifier_str"] = args.gateware_identifier_str
     argdict["hw_rev"] = args.hw_rev
+    argdict["drtio_100mhz"] = args.drtio100mhz

     soc = Satellite(**argdict)
     build_artiq_soc(soc, builder_argdict(args))