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  1. Info: Importing module blinky
  2. Info: Rule checker, verifying imported design
  3. Info: Checksum: 0x7587905e
  4.  
  5. Info: constrained 'i_clk' to bel 'X0/Y8/io1'
  6. Info: constrained 'o_led' to bel 'X13/Y12/io1'
  7.  
  8. Info: Packing constants..
  9. Info: Packing IOs..
  10. Info: Packing LUT-FFs..
  11. Info: Packing non-LUT FFs..
  12. Info: Packing carries..
  13. Info: Packing RAMs..
  14. Info: Placing PLLs..
  15. Info: Packing special functions..
  16. Info: Promoting globals..
  17. Info: promoting i_clk (fanout 32)
  18. Info: promoting $abc$452$auto$dff2dffe.cc:158:make_patterns_logic$392 [reset] (fanout 31)
  19. Info: Constraining chains...
  20. Info: Checksum: 0xe4cf01bc
  21.  
  22. Info: Annotating ports with timing budgets for target frequency 12.00 MHz
  23. Info: Checksum: 0x1cda906a
  24.  
  25. Info: Device utilisation:
  26. Info: ICESTORM_LC: 97/ 1280 7%
  27. Info: ICESTORM_RAM: 0/ 16 0%
  28. Info: SB_IO: 2/ 112 1%
  29. Info: SB_GB: 2/ 8 25%
  30. Info: ICESTORM_PLL: 0/ 1 0%
  31. Info: SB_WARMBOOT: 0/ 1 0%
  32.  
  33. Info: Placed 2 cells based on constraints.
  34. Info: Creating initial placement for remaining 99 cells.
  35. Info: initial placement placed 99/99 cells
  36. Info: Initial placement time 0.01s
  37. Info: Running simulated annealing placer.
  38. Info: at iteration #1: temp = 1.000000, timing cost = 27, wirelen = 1239
  39. Info: at iteration #5: temp = 0.364500, timing cost = 35, wirelen = 1208
  40. Info: at iteration #10: temp = 0.239148, timing cost = 29, wirelen = 1181
  41. Info: at iteration #15: temp = 0.205040, timing cost = 29, wirelen = 1141
  42. Info: at iteration #20: temp = 0.185048, timing cost = 31, wirelen = 1073
  43. Info: at iteration #25: temp = 0.150723, timing cost = 32, wirelen = 1048
  44. Info: at iteration #30: temp = 0.136028, timing cost = 35, wirelen = 921
  45. Info: at iteration #35: temp = 0.116627, timing cost = 30, wirelen = 1033
  46. Info: at iteration #40: temp = 0.105256, timing cost = 30, wirelen = 885
  47. Info: at iteration #45: temp = 0.094993, timing cost = 31, wirelen = 827
  48. Info: at iteration #50: temp = 0.081445, timing cost = 30, wirelen = 830
  49. Info: at iteration #55: temp = 0.077373, timing cost = 33, wirelen = 734
  50. Info: at iteration #60: temp = 0.063020, timing cost = 30, wirelen = 866
  51. Info: at iteration #65: temp = 0.051331, timing cost = 32, wirelen = 720
  52. Info: at iteration #70: temp = 0.044010, timing cost = 29, wirelen = 706
  53. Info: at iteration #75: temp = 0.039719, timing cost = 32, wirelen = 598
  54. Info: at iteration #80: temp = 0.032351, timing cost = 39, wirelen = 582
  55. Info: at iteration #85: temp = 0.026350, timing cost = 34, wirelen = 659
  56. Info: at iteration #90: temp = 0.022592, timing cost = 27, wirelen = 626
  57. Info: at iteration #95: temp = 0.020389, timing cost = 34, wirelen = 637
  58. Info: at iteration #100: temp = 0.017481, timing cost = 29, wirelen = 542
  59. Info: at iteration #105: temp = 0.014988, timing cost = 33, wirelen = 518
  60. Info: Legalising relative constraints...
  61. Info: moved 17 cells, 1 unplaced (after legalising chains)
  62. Info: average distance 0.906718
  63. Info: maximum distance 1.414214
  64. Info: moved 18 cells, 0 unplaced (after replacing ripped up cells)
  65. Info: average distance 0.911901
  66. Info: maximum distance 1.414214
  67. Info: at iteration #110: temp = 0.014239, timing cost = 28, wirelen = 402
  68. Info: at iteration #115: temp = 0.012208, timing cost = 30, wirelen = 477
  69. Info: at iteration #120: temp = 0.009943, timing cost = 33, wirelen = 508
  70. Info: at iteration #125: temp = 0.008525, timing cost = 29, wirelen = 377
  71. Info: at iteration #130: temp = 0.007309, timing cost = 32, wirelen = 392
  72. Info: at iteration #135: temp = 0.007309, timing cost = 23, wirelen = 290
  73. Info: at iteration #140: temp = 0.006267, timing cost = 23, wirelen = 326
  74. Info: at iteration #145: temp = 0.006267, timing cost = 19, wirelen = 250
  75. Info: at iteration #150: temp = 0.005656, timing cost = 22, wirelen = 250
  76. Info: at iteration #155: temp = 0.005373, timing cost = 25, wirelen = 217
  77. Info: at iteration #160: temp = 0.005104, timing cost = 24, wirelen = 193
  78. Info: at iteration #165: temp = 0.004376, timing cost = 22, wirelen = 195
  79. Info: at iteration #170: temp = 0.003950, timing cost = 20, wirelen = 163
  80. Info: at iteration #175: temp = 0.003950, timing cost = 19, wirelen = 146
  81. Info: at iteration #180: temp = 0.003002, timing cost = 17, wirelen = 134
  82. Info: at iteration #185: temp = 0.002401, timing cost = 16, wirelen = 122
  83. Info: at iteration #190: temp = 0.001537, timing cost = 16, wirelen = 118
  84. Info: at iteration #195: temp = 0.000630, timing cost = 16, wirelen = 116
  85. Info: at iteration #200: temp = 0.000258, timing cost = 16, wirelen = 114
  86. Info: at iteration #205: temp = 0.000084, timing cost = 16, wirelen = 114
  87. Info: at iteration #210: temp = 0.000028, timing cost = 16, wirelen = 114
  88. Info: at iteration #215: temp = 0.000009, timing cost = 16, wirelen = 114
  89. Info: at iteration #220: temp = 0.000003, timing cost = 16, wirelen = 114
  90. Info: at iteration #225: temp = 0.000001, timing cost = 16, wirelen = 114
  91. Info: at iteration #230: temp = 0.000000, timing cost = 16, wirelen = 114
  92. Info: at iteration #235: temp = 0.000000, timing cost = 16, wirelen = 114
  93. Info: at iteration #236: temp = 0.000000, timing cost = 16, wirelen = 114
  94. Info: SA placement time 0.56s
  95.  
  96. Info: Max frequency for clock 'i_clk_$glb_clk': 87.93 MHz (PASS at 12.00 MHz)
  97.  
  98. Info: Max delay posedge i_clk_$glb_clk -> <async>: 2.02 ns
  99.  
  100. Info: Slack histogram:
  101. Info: legend: * represents 1 endpoint(s)
  102. Info: + represents [1,1) endpoint(s)
  103. Info: [ 71960, 72453) |*******************************
  104. Info: [ 72453, 72946) |
  105. Info: [ 72946, 73439) |
  106. Info: [ 73439, 73932) |
  107. Info: [ 73932, 74425) |
  108. Info: [ 74425, 74918) |**
  109. Info: [ 74918, 75411) |
  110. Info: [ 75411, 75904) |
  111. Info: [ 75904, 76397) |*
  112. Info: [ 76397, 76890) |***
  113. Info: [ 76890, 77383) |***
  114. Info: [ 77383, 77876) |***
  115. Info: [ 77876, 78369) |*****
  116. Info: [ 78369, 78862) |*
  117. Info: [ 78862, 79355) |****
  118. Info: [ 79355, 79848) |***
  119. Info: [ 79848, 80341) |***
  120. Info: [ 80341, 80834) |***
  121. Info: [ 80834, 81327) |*
  122. Info: [ 81327, 81820) |********************************
  123. Info: Checksum: 0x49ef480b
  124.  
  125. Info: Routing..
  126. Info: Setting up routing queue.
  127. Info: Routing 236 arcs.
  128. Info: | (re-)routed arcs | delta | remaining
  129. Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs
  130. Info: 243 | 6 237 | 6 237 | 0
  131. Info: Routing complete.
  132. Info: Route time 0.02s
  133. Info: Checksum: 0xd9648797
  134.  
  135. Info: Critical path report for clock 'i_clk_$glb_clk' (posedge -> posedge):
  136. Info: curr total
  137. Info: 0.5 0.5 Source $auto$alumacc.cc:474:replace_alu$25.slice[7].adder_LC.O
  138. Info: 0.6 1.1 Net counter[7] budget 0.000000 ns (7,5) -> (6,5)
  139. Info: Sink $abc$452$auto$blifparse.cc:492:parse_blif$479_LC.I0
  140. Info: 0.4 1.6 Source $abc$452$auto$blifparse.cc:492:parse_blif$479_LC.O
  141. Info: 0.6 2.2 Net $abc$452$auto$alumacc.cc:474:replace_alu$16.BB[7] budget 0.000000 ns (6,5) -> (5,6)
  142. Info: Sink $nextpnr_ICESTORM_LC_1.I1
  143. Info: 0.3 2.4 Source $nextpnr_ICESTORM_LC_1.COUT
  144. Info: 0.0 2.4 Net $nextpnr_ICESTORM_LC_1$O budget 0.000000 ns (5,6) -> (5,6)
  145. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[8].carry$CARRY.CIN
  146. Info: 0.1 2.5 Source $auto$alumacc.cc:474:replace_alu$16.slice[8].carry$CARRY.COUT
  147. Info: 0.0 2.5 Net $auto$alumacc.cc:474:replace_alu$16.C[9] budget 0.000000 ns (5,6) -> (5,6)
  148. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[9].carry$CARRY.CIN
  149. Info: 0.1 2.7 Source $auto$alumacc.cc:474:replace_alu$16.slice[9].carry$CARRY.COUT
  150. Info: 0.0 2.7 Net $auto$alumacc.cc:474:replace_alu$16.C[10] budget 0.000000 ns (5,6) -> (5,6)
  151. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[10].carry$CARRY.CIN
  152. Info: 0.1 2.8 Source $auto$alumacc.cc:474:replace_alu$16.slice[10].carry$CARRY.COUT
  153. Info: 0.0 2.8 Net $auto$alumacc.cc:474:replace_alu$16.C[11] budget 0.000000 ns (5,6) -> (5,6)
  154. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[11].carry$CARRY.CIN
  155. Info: 0.1 2.9 Source $auto$alumacc.cc:474:replace_alu$16.slice[11].carry$CARRY.COUT
  156. Info: 0.0 2.9 Net $auto$alumacc.cc:474:replace_alu$16.C[12] budget 0.000000 ns (5,6) -> (5,6)
  157. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[12].carry$CARRY.CIN
  158. Info: 0.1 3.1 Source $auto$alumacc.cc:474:replace_alu$16.slice[12].carry$CARRY.COUT
  159. Info: 0.0 3.1 Net $auto$alumacc.cc:474:replace_alu$16.C[13] budget 0.000000 ns (5,6) -> (5,6)
  160. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[13].carry$CARRY.CIN
  161. Info: 0.1 3.2 Source $auto$alumacc.cc:474:replace_alu$16.slice[13].carry$CARRY.COUT
  162. Info: 0.0 3.2 Net $auto$alumacc.cc:474:replace_alu$16.C[14] budget 0.000000 ns (5,6) -> (5,6)
  163. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[14].carry$CARRY.CIN
  164. Info: 0.1 3.3 Source $auto$alumacc.cc:474:replace_alu$16.slice[14].carry$CARRY.COUT
  165. Info: 0.2 3.5 Net $auto$alumacc.cc:474:replace_alu$16.C[15] budget 0.190000 ns (5,6) -> (5,7)
  166. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[15].carry$CARRY.CIN
  167. Info: 0.1 3.6 Source $auto$alumacc.cc:474:replace_alu$16.slice[15].carry$CARRY.COUT
  168. Info: 0.0 3.6 Net $auto$alumacc.cc:474:replace_alu$16.C[16] budget 0.000000 ns (5,7) -> (5,7)
  169. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[16].carry$CARRY.CIN
  170. Info: 0.1 3.8 Source $auto$alumacc.cc:474:replace_alu$16.slice[16].carry$CARRY.COUT
  171. Info: 0.0 3.8 Net $auto$alumacc.cc:474:replace_alu$16.C[17] budget 0.000000 ns (5,7) -> (5,7)
  172. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[17].carry$CARRY.CIN
  173. Info: 0.1 3.9 Source $auto$alumacc.cc:474:replace_alu$16.slice[17].carry$CARRY.COUT
  174. Info: 0.0 3.9 Net $auto$alumacc.cc:474:replace_alu$16.C[18] budget 0.000000 ns (5,7) -> (5,7)
  175. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[18].carry$CARRY.CIN
  176. Info: 0.1 4.0 Source $auto$alumacc.cc:474:replace_alu$16.slice[18].carry$CARRY.COUT
  177. Info: 0.0 4.0 Net $auto$alumacc.cc:474:replace_alu$16.C[19] budget 0.000000 ns (5,7) -> (5,7)
  178. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[19].carry$CARRY.CIN
  179. Info: 0.1 4.1 Source $auto$alumacc.cc:474:replace_alu$16.slice[19].carry$CARRY.COUT
  180. Info: 0.0 4.1 Net $auto$alumacc.cc:474:replace_alu$16.C[20] budget 0.000000 ns (5,7) -> (5,7)
  181. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[20].carry$CARRY.CIN
  182. Info: 0.1 4.3 Source $auto$alumacc.cc:474:replace_alu$16.slice[20].carry$CARRY.COUT
  183. Info: 0.0 4.3 Net $auto$alumacc.cc:474:replace_alu$16.C[21] budget 0.000000 ns (5,7) -> (5,7)
  184. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[21].carry$CARRY.CIN
  185. Info: 0.1 4.4 Source $auto$alumacc.cc:474:replace_alu$16.slice[21].carry$CARRY.COUT
  186. Info: 0.0 4.4 Net $auto$alumacc.cc:474:replace_alu$16.C[22] budget 0.000000 ns (5,7) -> (5,7)
  187. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[22].carry$CARRY.CIN
  188. Info: 0.1 4.5 Source $auto$alumacc.cc:474:replace_alu$16.slice[22].carry$CARRY.COUT
  189. Info: 0.2 4.7 Net $auto$alumacc.cc:474:replace_alu$16.C[23] budget 0.190000 ns (5,7) -> (5,8)
  190. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[23].carry$CARRY.CIN
  191. Info: 0.1 4.8 Source $auto$alumacc.cc:474:replace_alu$16.slice[23].carry$CARRY.COUT
  192. Info: 0.0 4.8 Net $auto$alumacc.cc:474:replace_alu$16.C[24] budget 0.000000 ns (5,8) -> (5,8)
  193. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[24].carry$CARRY.CIN
  194. Info: 0.1 5.0 Source $auto$alumacc.cc:474:replace_alu$16.slice[24].carry$CARRY.COUT
  195. Info: 0.0 5.0 Net $auto$alumacc.cc:474:replace_alu$16.C[25] budget 0.000000 ns (5,8) -> (5,8)
  196. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[25].carry$CARRY.CIN
  197. Info: 0.1 5.1 Source $auto$alumacc.cc:474:replace_alu$16.slice[25].carry$CARRY.COUT
  198. Info: 0.0 5.1 Net $auto$alumacc.cc:474:replace_alu$16.C[26] budget 0.000000 ns (5,8) -> (5,8)
  199. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[26].carry$CARRY.CIN
  200. Info: 0.1 5.2 Source $auto$alumacc.cc:474:replace_alu$16.slice[26].carry$CARRY.COUT
  201. Info: 0.0 5.2 Net $auto$alumacc.cc:474:replace_alu$16.C[27] budget 0.000000 ns (5,8) -> (5,8)
  202. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[27].carry$CARRY.CIN
  203. Info: 0.1 5.3 Source $auto$alumacc.cc:474:replace_alu$16.slice[27].carry$CARRY.COUT
  204. Info: 0.0 5.3 Net $auto$alumacc.cc:474:replace_alu$16.C[28] budget 0.000000 ns (5,8) -> (5,8)
  205. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[28].carry$CARRY.CIN
  206. Info: 0.1 5.5 Source $auto$alumacc.cc:474:replace_alu$16.slice[28].carry$CARRY.COUT
  207. Info: 0.0 5.5 Net $auto$alumacc.cc:474:replace_alu$16.C[29] budget 0.000000 ns (5,8) -> (5,8)
  208. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[29].carry$CARRY.CIN
  209. Info: 0.1 5.6 Source $auto$alumacc.cc:474:replace_alu$16.slice[29].carry$CARRY.COUT
  210. Info: 0.0 5.6 Net $auto$alumacc.cc:474:replace_alu$16.C[30] budget 0.000000 ns (5,8) -> (5,8)
  211. Info: Sink $auto$alumacc.cc:474:replace_alu$16.slice[30].carry$CARRY.CIN
  212. Info: 0.1 5.7 Source $auto$alumacc.cc:474:replace_alu$16.slice[30].carry$CARRY.COUT
  213. Info: 0.5 6.2 Net $nextpnr_ICESTORM_LC_2$I3 budget 0.560000 ns (5,8) -> (5,9)
  214. Info: Sink $nextpnr_ICESTORM_LC_2.I3
  215. Info: 0.3 6.5 Source $nextpnr_ICESTORM_LC_2.O
  216. Info: 1.3 7.8 Net $abc$452$auto$alumacc.cc:491:replace_alu$18[30] budget 33.570000 ns (5,9) -> (6,5)
  217. Info: Sink $abc$452$auto$blifparse.cc:492:parse_blif$464_LC.I1
  218. Info: 0.4 8.2 Source $abc$452$auto$blifparse.cc:492:parse_blif$464_LC.O
  219. Info: 1.6 9.8 Net $abc$452$auto$dff2dffe.cc:158:make_patterns_logic$398 budget 34.300999 ns (6,5) -> (6,5)
  220. Info: Sink $abc$452$auto$blifparse.cc:492:parse_blif$481_LC.CEN
  221. Info: 0.1 9.9 Setup $abc$452$auto$blifparse.cc:492:parse_blif$481_LC.CEN
  222. Info: 5.0 ns logic, 4.9 ns routing
  223.  
  224. Info: Critical path report for cross-domain path 'posedge i_clk_$glb_clk' -> '<async>':
  225. Info: curr total
  226. Info: 0.5 0.5 Source $abc$452$auto$blifparse.cc:492:parse_blif$480_LC.O
  227. Info: 1.3 1.8 Net o_led budget 82.792999 ns (9,9) -> (13,12)
  228. Info: Sink o_led$sb_io.D_OUT_0
  229. Info: 0.5 ns logic, 1.3 ns routing
  230.  
  231. Info: Max frequency for clock 'i_clk_$glb_clk': 101.28 MHz (PASS at 12.00 MHz)
  232.  
  233. Info: Max delay posedge i_clk_$glb_clk -> <async>: 1.81 ns
  234.  
  235. Info: Slack histogram:
  236. Info: legend: * represents 1 endpoint(s)
  237. Info: + represents [1,1) endpoint(s)
  238. Info: [ 73459, 73877) |********************************
  239. Info: [ 73877, 74295) |
  240. Info: [ 74295, 74713) |*
  241. Info: [ 74713, 75131) |
  242. Info: [ 75131, 75549) |
  243. Info: [ 75549, 75967) |
  244. Info: [ 75967, 76385) |
  245. Info: [ 76385, 76803) |*
  246. Info: [ 76803, 77221) |***
  247. Info: [ 77221, 77639) |***
  248. Info: [ 77639, 78057) |**
  249. Info: [ 78057, 78475) |***
  250. Info: [ 78475, 78893) |***
  251. Info: [ 78893, 79311) |**
  252. Info: [ 79311, 79729) |****
  253. Info: [ 79729, 80147) |**
  254. Info: [ 80147, 80565) |***
  255. Info: [ 80565, 80983) |***
  256. Info: [ 80983, 81401) |
  257. Info: [ 81401, 81819) |*********************************
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