package main

import (
	"fmt"
	"github.com/tggo/periph/devices/si5351"
	"log"
	"periph.io/x/periph/host"
	"periph.io/x/periph/conn/i2c/i2creg"
		"flag"
	"time"
)

func main() {
	fmt.Println("starting")



	// Make sure periph is initialized.
	if _, err := host.Init(); err != nil {
		log.Fatal(err)
	}

	// Use i2creg I²C bus registry to find the first available I²C bus.
	b, err := i2creg.Open("1")
	if err != nil {
		log.Fatalf("failed to open I²C: %v", err)
	}
	defer b.Close()


	d, err := si5351.New(b, 0x60, &si5351.DefaultOpts)
	if err != nil {
		log.Fatalf("failed to initialize si5351: %v", err)
	}
	fmt.Println("end create device")

	d.UpdateSysStatus()
	d.UpdateIntStatus()

	//fmt.Printf("%v\n", d)

	//fmt.Println("Set Output #0 to 13.703704 MHz")
	//// vco = 25 MHz * (24 + 2 / 3) = 616.67 MHz

	//var p1,p2,p3, pllFreq int64

	// 25 mhz * (p1 + p2 / p3)
	//p1 = 24
	//p2 = 2
	//p3 = 3
	//p1 = 24
	//p2 = 666800
	//p3 = 1000000
	//p1, p2, p3  = d.PLLCalc(894762000)
	//
	//vco := 25 * (float64(p1)+float64(p2)/float64(p3))
	//d.SetupPLL(0, p1, p2, p3)
	//
	//
	////vco mhz / (p1 + p2 / p3)
	//p1 = 66
	//p2 = 0
	//p3 = 1
	//freq := vco  / (float64(p1)+float64(p2)/float64(p3))
	//d.SetupMultisynth(0, 0, p1, p2 , p3)
	//fmt.Printf("vco: %v, freq: %v\n", vco, freq)
	//d.EnableOutputs(true)


	PfFreq := flag.Int("pf", 8000000, "an int")
	freq := flag.Int("freq", 3650000, "an int")
	cycle := flag.Int("cycle", 0, "number of cycle or not (zero)")
	cycleDealy := flag.Int("delay", 100, "ms to delay in cycle")
	cycleStep := flag.Int("step", 500, "step in cycle")
	calibrationOffset := flag.Int("calibration", 700, "Hz to calibrate syntezator")

	flag.Parse()


	PF_freq:=int32(*PfFreq)


	d.SetupFreq(1, PF_freq )
	d.OutputEnable(1, true)


	//startFreq := int32(6990000)
	//startFreq := int32(7000000)
	startFreq := int32(*freq-*calibrationOffset)
	//startFreq := int32(3740000)
	//startFreq := int32(0)


	fmt.Println("freq:", startFreq)
	fmt.Println("clk0:", startFreq+PF_freq)

	//p1,p2,p3, pllFreq := d.CalcMultiSynth( int64(startFreq),0)
	//fmt.Println("-MuS---- pllFreq: ", pllFreq, " p1,p2,p3:",p1,p2,p3)
	//// vco = 25 * ( 65 + 0 / 1 )
	//pp1,pp2,pp3 := d.PLLCalc(si5351.PLLA, pllFreq)
	//fmt.Println("-PLL---- pllFreq: ", pllFreq, " pp1,pp2,pp3:",pp1,pp2,pp3)
	//d.SetupPLL(0, pp1, pp2, pp3)
	//d.SetupMultisynth(0, 0, p1, p2 , p3)
	//d.EnableOutputs(false)

	d.SetupFreq(0, startFreq+PF_freq )
	d.OutputEnable(0, true)

	//d.SetupFreq(1, startFreq )
	//d.OutputEnable(1, true)
	//
	//d.SetupFreq(2, 1100000 )
	//d.OutputEnable(2, true)


	//// SIMPLE SWITCHING
	//for i := 0; i<50; i++ {
	//	d.OutputEnable(0, true)
	//	time.Sleep(3 * time.Millisecond)
	//	d.OutputEnable(0, false)
	//	time.Sleep(3 * time.Millisecond)
	//
	//}
	//
	//d.OutputEnable(0, false)

	//
	//// OLD METHOD
	//for i := 0; i<100; i++  {
	//	freq:= int64(startFreq + i*10)
	//
	//	fmt.Println(freq)
	//	//d.EnableOutputs(false)
	//	//d.Reset()
	//	p1,p2,p3, pllFreq = d.CalcMultiSynth( freq,0)
	//	//pp1,pp2,pp3 := d.PLLCalc(si5351.PLL_A, pllFreq)
	//	//d.SetupPLL(0, pp1, pp2, pp3)
	//	d.SetupPLLFreq(0, int32(pllFreq))
	//	//d.SetupMultiSynth(0, 0, p1, p2 , p3)
	//	d.SetupMultiSynthNew(0, 0, p1, p2 , p3, false, 0, 0)
	//	//d.EnableOutputs(true)
	//	d.OutputEnable(0, true)
	//
	//	time.Sleep(30 * time.Millisecond)
	//}
	//
	//


	//
	//
	// NEW METHOD
	if *cycle > 0 {
	for i := 0; i<*cycle; i++  {

		freq:= int64(startFreq + int32(i * *cycleStep ))

		fmt.Println("Freq: ", freq )
		d.SetupFreq(0,  int32(freq)+ PF_freq)
		////d.EnableOutputs(false)
		////d.Reset()
		//p1,p2,p3, pllFreq = d.CalcMultiSynth( freq,0)
		////pp1,pp2,pp3 := d.PLLCalc(si5351.PLL_A, pllFreq)
		////d.SetupPLL(0, pp1, pp2, pp3)
		//d.SetupPLLFreq(0, int32(pllFreq))
		////d.SetupMultiSynth(0, 0, p1, p2 , p3)
		//d.SetupMultiSynthNew(0, 0, p1, p2 , p3, false, 0, 0)
		////d.EnableOutputs(true)
		d.OutputEnable(0, true)

		time.Sleep(time.Duration(*cycleDealy) * time.Millisecond)
	}
	}




	//
	//
	//
	//d.Reset()
	//fmt.Println(  600/25 )


	//d.SetupMultisynth(0, 0, 45, 1 , 2)


	/* Setup Multisynth 1 to 13.55311MHz (PLLB/45.5) */
	//d.SetupMultisynth(0, 0, 45, 1 , 2)

	//// out = 616.67 MHz / 45 = 13.703704 MHz
	//d.SetupMultisynth(0, 0, 45, 0 , 1)


	//// si.setupRdiv(0, si.R_DIV_64)

	//d.SetupPLL(0, 24, 2, 3)

	//d.SetupFreq(0, 13.703704)






	//fmt.Println("enabling")

	//d.EnableOutputs(false)


	//d.EnableOutputs(false)
	//d.EnableOutputs(true)

	//time.Sleep(25000 * time.Millisecond)
	//d.OutputEnable(0, false)
	//d.OutputEnable(1, false)

	fmt.Println("ending")
}