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Apr 19th, 2018
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3.  
  4. -- warning: this file will not be saved if:
  5. -- * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
  6. -- * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
  7. ENTITY b1kompl IS PORT(
  8. b: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
  9. y: OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  10. );
  11. END b1kompl;
  12.  
  13. ARCHITECTURE arch OF b1kompl IS
  14.  
  15. BEGIN
  16.  
  17. y(1) <= (not(b(1))) after 10 ns;
  18. y(0) <= (not(b(0))) after 10 ns;
  19.  
  20. END arch;
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