module clks(
    input clk,
    output [15:0] led
    );

    reg tenMHz = 0;
    reg oneMHz = 0;
    reg hunkHz = 0;
    reg tenkHz = 0;
    reg [15:0] count = 0;
    assign led[0] = count[0]; //50MHz
    assign led[1] = count[1]; //25MHz
    assign led[2] = count[2]; //12.5MHz
    assign led[3] = count[3]; //6.25MHz
    assign led[4] = count[4]; //3.13MHz
    assign led[5] = count[5]; //1.56MHz
    assign led[6] = count[6]; //0.78MHz
    assign led[7] = count[7]; //0.39MHz
    assign led[8] = count[8]; //195kHz
    assign led[9] = count[9]; //97.7kHz
    assign led[10] = count[10]; //48.8kHz
    assign led[11] = count[11]; //24.4kHz

    assign led[12] = tenMHz; //10Mhz
    assign led[13] = oneMHz; //1MHz
    assign led[14] = hunkHz; //100kHz
    assign led[15] = tenkHz; //10kHz

    always @(posedge clk) begin
        count = count + 1;

        if(count % 10 == 0) tenMHz = ~tenMHz;
        else if(count % 100 == 0) oneMHz = ~oneMHz;
        else if(count % 1000 == 0) hunkHz = ~hunkHz;
        else if(count % 10000 == 0) tenkHz = ~tenkHz;


    end

endmodule