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  1.  
  2. `timescale 1 ns / 1 ps
  3.  
  4. module axis_red_pitaya_dac #
  5. (
  6.   parameter integer DAC_DATA_WIDTH = 14,
  7.   parameter integer AXIS_TDATA_WIDTH = 32
  8. )
  9. (
  10.   // PLL signals
  11.   input  wire                        aclk,
  12.   input  wire                        ddr_clk,
  13.   input  wire                        locked,
  14.  
  15.   // DAC signals
  16.   output wire                        dac_clk,
  17.   output wire                        dac_rst,
  18.   output wire                        dac_sel,
  19.   output wire                        dac_wrt,
  20.   output wire [DAC_DATA_WIDTH-1:0]   dac_dat,
  21.  
  22.   // Slave side
  23.   output wire                        s_axis_tready,
  24.   input  wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
  25.   input  wire [DAC_DATA_WIDTH-1:0]   gain_data,
  26.   input  wire                        s_axis_tvalid
  27. );
  28.  
  29.   reg [DAC_DATA_WIDTH-1:0] int_dat_a_reg;
  30.   reg [DAC_DATA_WIDTH-1:0] int_dat_b_reg;
  31.   reg int_rst_reg;
  32.  
  33.   wire [DAC_DATA_WIDTH-1:0] int_dat_a_wire;
  34.   wire [DAC_DATA_WIDTH-1:0] int_dat_b_wire;
  35.  
  36.   assign int_dat_a_wire = s_axis_tdata[DAC_DATA_WIDTH-1:0];
  37.   assign int_dat_b_wire = gain_data;
  38.  
  39.   genvar j;
  40.  
  41.   always @(posedge aclk)
  42.   begin
  43.     if(~locked | ~s_axis_tvalid)
  44.     begin
  45.       int_dat_a_reg <= {(DAC_DATA_WIDTH){1'b0}};
  46.       int_dat_b_reg <= {(DAC_DATA_WIDTH){1'b0}};
  47.     end
  48.     else
  49.     begin
  50.       int_dat_a_reg <= {int_dat_a_wire[DAC_DATA_WIDTH-1], ~int_dat_a_wire[DAC_DATA_WIDTH-2:0]};
  51.       int_dat_b_reg <= {int_dat_b_wire[DAC_DATA_WIDTH-1], ~int_dat_b_wire[DAC_DATA_WIDTH-2:0]};
  52.     end
  53.     int_rst_reg <= ~locked | ~s_axis_tvalid;
  54.   end
  55.  
  56.   ODDR ODDR_rst(.Q(dac_rst), .D1(int_rst_reg), .D2(int_rst_reg), .C(aclk), .CE(1'b1), .R(1'b0), .S(1'b0));
  57.   ODDR ODDR_sel(.Q(dac_sel), .D1(1'b0), .D2(1'b1), .C(aclk), .CE(1'b1), .R(1'b0), .S(1'b0));
  58.   ODDR ODDR_wrt(.Q(dac_wrt), .D1(1'b0), .D2(1'b1), .C(ddr_clk), .CE(1'b1), .R(1'b0), .S(1'b0));
  59.   ODDR ODDR_clk(.Q(dac_clk), .D1(1'b0), .D2(1'b1), .C(ddr_clk), .CE(1'b1), .R(1'b0), .S(1'b0));
  60.  
  61.   generate
  62.     for(j = 0; j < DAC_DATA_WIDTH; j = j + 1)
  63.     begin : DAC_DAT
  64.       ODDR ODDR_inst(
  65.         .Q(dac_dat[j]),
  66.         .D1(int_dat_a_reg[j]),
  67.         .D2(int_dat_b_reg[j]),
  68.         .C(aclk),
  69.         .CE(1'b1),
  70.         .R(1'b0),
  71.         .S(1'b0)
  72.       );
  73.     end
  74.   endgenerate
  75.  
  76.   assign s_axis_tready = 1'b1;
  77.  
  78. endmodule
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