----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03/21/2019 10:45:15 AM
-- Design Name:
-- Module Name: main - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk : in STD_LOGIC;
           sw  : in STD_LOGIC_VECTOR (15 downto 0);
           btn : in STD_LOGIC_VECTOR (4 downto 0);
           led : out STD_LOGIC_VECTOR (15 downto 0);
           cat : out STD_LOGIC_VECTOR (6 downto 0);
           an  : out STD_LOGIC_VECTOR (7 downto 0);
           dp  : out STD_LOGIC);
end main;

architecture Behavioral of main is

signal s : std_logic_vector (31 downto 0) := x"0000";

begin

    sum_8b0: entity WORK.sum_8b port map (
                    x => sw (15 downto 8),
                    y => sw (7 downto 0),
                    tin => '0',
                    s => s (7 downto 0),
                    tout => s(8));

    ssd_0: entity WORK.ssd port map (
                    data => s,
                    clk => clk,
                    cat => cat,
                    an => an);

end Behavioral;