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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date: 03/21/2019 10:45:15 AM
  6. -- Design Name:
  7. -- Module Name: main - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool Versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20.  
  21.  
  22. library IEEE;
  23. use IEEE.STD_LOGIC_1164.ALL;
  24.  
  25. -- Uncomment the following library declaration if using
  26. -- arithmetic functions with Signed or Unsigned values
  27. --use IEEE.NUMERIC_STD.ALL;
  28.  
  29. -- Uncomment the following library declaration if instantiating
  30. -- any Xilinx leaf cells in this code.
  31. --library UNISIM;
  32. --use UNISIM.VComponents.all;
  33.  
  34. entity main is
  35.     Port ( clk : in STD_LOGIC;
  36.            sw  : in STD_LOGIC_VECTOR (15 downto 0);
  37.            btn : in STD_LOGIC_VECTOR (4 downto 0);
  38.            led : out STD_LOGIC_VECTOR (15 downto 0);
  39.            cat : out STD_LOGIC_VECTOR (6 downto 0);
  40.            an  : out STD_LOGIC_VECTOR (7 downto 0);
  41.            dp  : out STD_LOGIC);
  42. end main;
  43.  
  44. architecture Behavioral of main is
  45.  
  46. signal s : std_logic_vector (31 downto 0) := x"0000";
  47.  
  48. begin
  49.  
  50.     sum_8b0: entity WORK.sum_8b port map (
  51.                     x => sw (15 downto 8),
  52.                     y => sw (7 downto 0),
  53.                     tin => '0',
  54.                     s => s (7 downto 0),
  55.                     tout => s(8));
  56.                    
  57.     ssd_0: entity WORK.ssd port map (
  58.                     data => s,
  59.                     clk => clk,
  60.                     cat => cat,
  61.                     an => an);
  62.  
  63. end Behavioral;
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