counter_5

module counter(input logic clk,reset, output logic[3:0] result);
typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7} state;
state st;
state newst = S0;
always_ff@ (posedge clk)
begin
st = newst;
end
always_ff@ (posedge clk)
begin
if(reset)
begin
    result = 0;
end
else
case(st)
S0:
begin
result = 0;
newst = S1;
end
S1:
begin
result = 8;
newst = S2;
end
S2:
begin
result = 12;
newst = S3;
end
S3:
begin
result = 14;
newst = S4;
end
S4:
begin
result = 15;
newst = S5;
end
S5:
begin
result = 7;
newst = S6;
end
S6:
begin
result = 3;
newst = S7;
end
S7:
begin
result = 1;
newst = S0;
end
endcase
end
endmodule