kirill_76rus

counter_5

Dec 25th, 2020
806
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  1. module counter(input logic clk,reset, output logic[3:0] result);
  2. typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7} state;
  3. state st;
  4. state newst = S0;
  5. always_ff@ (posedge clk)
  6. begin
  7. st = newst;
  8. end
  9. always_ff@ (posedge clk)
  10. begin
  11. if(reset)
  12. begin
  13.     result = 0;
  14. end
  15. else
  16. case(st)
  17. S0:
  18. begin
  19. result = 0;
  20. newst = S1;
  21. end
  22. S1:
  23. begin
  24. result = 8;
  25. newst = S2;
  26. end
  27. S2:
  28. begin
  29. result = 12;
  30. newst = S3;
  31. end
  32. S3:
  33. begin
  34. result = 14;
  35. newst = S4;
  36. end
  37. S4:
  38. begin
  39. result = 15;
  40. newst = S5;
  41. end
  42. S5:
  43. begin
  44. result = 7;
  45. newst = S6;
  46. end
  47. S6:
  48. begin
  49. result = 3;
  50. newst = S7;
  51. end
  52. S7:
  53. begin
  54. result = 1;
  55. newst = S0;
  56. end
  57. endcase
  58. end
  59. endmodule
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